IP178Gx
Data Sheet
8 Port 10/100 Ethernet Integrated Switch
(85nm /Extreme Low Power, PWMT® and AFT® )
Features
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General Description
8 port Embedded 10/100 PHY Switch Controller
IP178G Support 8 100BaseTX
IP178GH/GI support 8 100BaseTX or 6 100Base
TX + 2 FX
100M PHY support IEEE802.3az at full duplex
10M PHY only support 10BaseTe
Support Auto MDI-MDIX function
Power Management Tool (PWMT®)
- APS, auto-power saving while Link-off
- IEEE 802.3az protocol based power saving
- WOL+®, light traffic power saving
- PWD, force-off power saving
Support Auto Factory Test (AFT®)
Single Power 3.3V supply
Built in 1.1V core voltage LDO Regulator
Two Priority queues per port
Support 802.1p & DiffServ based QoS
QoS
- Port base
- 802.1p
- IP DiffServ IPV4/IPV6
- TCP/UDP port number
- Pins configure ports priority (VIP port)
Support max forwarding packet length 1552/1536
bytes option
Embedded 448K bits packet buffer
Support port mirror function
Support 1k MAC address
Support broadcast storm protection
Support port trunking (Link Aggregation)
Support 16 VLAN (IEEE Std 802.1q)
- Port-based/Tagged-based VLAN
- Support Port-based insert, remove tag
Built-in 50 ohm resistors for simplifying BOM
85nm Process
Package and operation temperature
- IP178G/GH: 68 Pin QFN, 0~70℃
- IP178GI: 68 Pin QFN, -40~85℃
IP178Gx is fabricated with advanced CMOS
(85nm) technology and only requires a 3.3V single
power supply. This feature makes IP178GX used
very low power consume, such as the full load
operation (100Mbps full duplex 8 ports), it only
takes 0.95W.
IP178Gx also supports Power Management Tool
(PWMT®) for IEEE 802.3az, APS, WOL+ and PWD
for Green Power. While two link devices have no
IEEE 802.3az capability, IP178Gx use WOL+ to
change link from 100Mbps to 10Mbps for saving
power.
The PWD, force-off power saving of IP178Gx is
designed for power down switch immediately by
pushing a button, user don’t plug out the power
adapter. Push the button again, it will power on
immediately.
Except Low Power and Rich Power Saving
method, IP178Gx supports AFT® for saving
Customer Testing Cost. By using a push button and
cables, IP178Gx will Auto test completely by itself.
Application
8 port 10/100 Dumb switch
6TX+2FX Dumb Switch or 7TX + 1FX Dumb Switch
1 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
Table of Contents
Features..................................................................................................................................................................................1
General Description...............................................................................................................................................................1
Table of Contents...................................................................................................................................................................2
List of Tables...........................................................................................................................................................................5
List of Figures.........................................................................................................................................................................6
Revision History.....................................................................................................................................................................7
Features comparison between IP178D and IP178Gx......................................................................................................8
1 Pin diagram....................................................................................................................................................................9
1.1
IP178Gx Pin diagram (QFN68).............................................................................................. 9
2 IP178Gx application diagram ....................................................................................................................................10
2.1
An 8 TP port switch application............................................................................................ 10
2.2
An 8-port switch mixed with two fiber ports ......................................................................... 10
2.3
TCP/UDP QoS Switch for time-sensitive application from EEPROM setting .......................11
2.4
Switch with VIP ports for specific users from Pin setting ......................................................11
2.5
A 8-port Switch with Port mirror capability setting from EEPROM....................................... 12
3 Pin description.............................................................................................................................................................13
3.1
Analog pins .......................................................................................................................... 13
3.2
MDI (Media Dependent Interface) ....................................................................................... 13
3.3
System clock & reset pins.................................................................................................... 14
3.4
Boundry scan & test mode................................................................................................... 14
3.5
EEPROM interface /SMI (Serial Management interface) .................................................... 15
3.6
Frame priority setting pins.................................................................................................... 16
3.7
Miscellaneous setting pins ................................................................................................... 17
3.8
LED interface ....................................................................................................................... 18
3.9
Power & ground pads .......................................................................................................... 18
4 Functional Description................................................................................................................................................19
4.1
Switch Engine and Queue Management ............................................................................. 19
4.1.1
Switch Engine ......................................................................................................... 19
4.1.2
Packet Forwarding .................................................................................................. 19
4.1.3
Flow control............................................................................................................. 19
4.1.4
Backpressure .......................................................................................................... 19
4.1.5
Broadcast storm protection ..................................................................................... 19
4.2
Rserved Group MAC Address.............................................................................................. 20
4.3
Green Power ........................................................................................................................ 21
4.3.1
Auto Power Saving Mode ....................................................................................... 21
4.3.2
IEEE802.3az EEE (Energy Efficient Ethernet) ....................................................... 21
4.3.3
WOL+ (Wake On LAN Plus) ................................................................................... 21
4.3.4
Force Power Off ...................................................................................................... 22
4.4
Auto Factory Test (AFT) Mode............................................................................................. 23
4.5
Reset.................................................................................................................................... 23
4.6
Serial management interface ............................................................................................... 24
4.7
EEPROM interface............................................................................................................... 25
4.7.1
Example: Configure port based VLAN of IP178Gx................................................. 25
4.8
CoS ...................................................................................................................................... 26
4.8.1
Port base priority..................................................................................................... 26
4.8.2
VIP ports ................................................................................................................. 26
4.8.3
Frame base priority ................................................................................................. 27
4.8.3.1
VLAN tag and TCP/IP TOS ........................................................................... 27
4.8.3.2
IPv4/IPv6 DiffServ ......................................................................................... 28
4.8.3.3
TCP/UDP logical port priority ........................................................................ 29
4.9
Port Mirroring ....................................................................................................................... 29
4.10 Link Aggergation .................................................................................................................. 30
4.11
Buffer Aging.......................................................................................................................... 32
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Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.12
4.13
5
6
7
LED display (normal operation) ........................................................................................... 32
Serial LED Mode.................................................................................................................. 32
4.13.1
Supports link LED only............................................................................................ 32
4.13.2
Supports link, speed, and duplex LED.................................................................... 33
4.14 LED Blink Timing.................................................................................................................. 33
4.15 PAD Driving Calibration ....................................................................................................... 34
4.16 Fiber port configuration ........................................................................................................ 34
Register descriptions ..................................................................................................................................................35
5.1
Register map........................................................................................................................ 35
5.1.1
MII register map ...................................................................................................... 35
PHY registers ..............................................................................................................................................................36
6.1
MII Register.......................................................................................................................... 37
6.2
MMD Control Register ......................................................................................................... 44
6.3
MMD Data Register ............................................................................................................. 45
6.4
LED mode Control Register ................................................................................................. 48
6.5
WOL+ Control Register........................................................................................................ 49
6.6
Register Page mode Control Register ................................................................................. 50
6.7
Switch control registers (I) ................................................................................................... 51
6.8
Test mode control registers.................................................................................................. 52
6.9
Port mirroring control registers............................................................................................. 53
6.10 Debug Regiister ................................................................................................................... 53
6.11
Fiber duplex setting registers............................................................................................... 54
6.12 Backpressure setting registers............................................................................................. 54
6.13 TCP/UDP port priority registers ........................................................................................... 55
6.14 Test mode............................................................................................................................. 55
6.15 CoS control registers – port 0 .............................................................................................. 56
6.16 CoS control registers – port 1 .............................................................................................. 56
6.17 CoS control registers – port 2 .............................................................................................. 56
6.18 CoS control registers – port 3 .............................................................................................. 56
6.19 CoS control registers – port 4 .............................................................................................. 57
6.20 CoS control registers – port 5 .............................................................................................. 57
6.21 CoS control registers – port 6 .............................................................................................. 57
6.22 CoS control registers – port 7 .............................................................................................. 57
6.23 Switch control registers (IV) ................................................................................................. 58
6.24 Reserved Group MAC addresses ........................................................................................ 59
6.25 Switch control registers (V) .................................................................................................. 63
6.26 EEE Timing Parameter ........................................................................................................ 63
6.27 WOL (Wake on LAN)............................................................................................................ 64
6.28 Link Aggregation .................................................................................................................. 65
6.29 VLAN Group Control Register.............................................................................................. 65
6.29.1
VLAN Classification ................................................................................................ 65
6.29.2
VLAN Ingress Rule ................................................................................................. 66
6.29.3
Default VLAN Information ....................................................................................... 67
6.29.4
VLAN TAG Control Register ................................................................................... 67
6.29.5
Port Based VLAN Member Register ....................................................................... 67
6.29.6
Leaky VLAN Control Register................................................................................. 68
6.30 VLAN Table .......................................................................................................................... 68
6.30.1
VLAN Control Register............................................................................................ 68
6.30.2
VLAN Identifier Register ......................................................................................... 68
6.30.3
VLAN Member Register .......................................................................................... 69
Electrical Characteristics ............................................................................................................................................71
7.1
Absolute Maximum Rating ................................................................................................... 71
7.2
Crystal Specifications........................................................................................................... 71
7.3
DC Characteristic................................................................................................................. 71
7.3.1
Operating Conditions .............................................................................................. 71
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Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
8
9
7.3.2
Input Clock .............................................................................................................. 72
7.3.3
I/O Electrical Characteristics................................................................................... 72
7.4
AC Timing............................................................................................................................. 72
7.4.1
Power On Sequence and Reset Timing.................................................................. 72
7.4.2
Serial Management Imierface Timing ..................................................................... 73
7.4.3
EEPROM Timing..................................................................................................... 74
7.4.3.1
Data read cycle ............................................................................................. 74
7.4.3.2
Command cycle ............................................................................................ 74
7.5
Thermal Data ....................................................................................................................... 74
Order Information........................................................................................................................................................75
Package Detail ............................................................................................................................................................76
9.1
68 QFN Outline Dimensions ................................................................................................ 76
9.2
68 QFN PCB footprint .......................................................................................................... 77
4 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
IP178D and IP178Gx Features comparison table ......................................................... 8
Pin description.............................................................................................................. 13
Rserved Group MAC Address table............................................................................. 20
VIP port pin setting table .............................................................................................. 26
TCP/UDP logical port priority table .............................................................................. 29
LED Blink Timing.......................................................................................................... 33
Fiber port Parameter .................................................................................................... 34
MII register map table .................................................................................................. 35
PHY Register Map ....................................................................................................... 36
MMD Control Register table....................................................................................... 44
MMD Data Register table ........................................................................................... 45
LED mode Control Register table .............................................................................. 48
WOL+ Control Register table ..................................................................................... 49
Page control registers table ....................................................................................... 50
Switch control registers (I) table................................................................................. 51
Test mode control registers table ............................................................................... 52
5 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Pin Diagram (IP178Gx) ................................................................................................ 9
WOL+ Application Diagram........................................................................................ 22
Magic Packet Format ................................................................................................. 22
Force Power Off Application Diagram........................................................................ 22
Auto Factory Test Application Diagram ...................................................................... 23
Serial management interface Read / Write Diagram ................................................. 24
EEPROM data format ................................................................................................ 25
VLAN tag and TCP/IP TOS frame.............................................................................. 27
IPv4/IPv6 DiffServ frame............................................................................................ 28
Port Mirroring Security Block Diagram..................................................................... 30
Trunk Channel Behavior Block Diagram .................................................................. 30
Load Balance Block Diagram................................................................................... 31
Serial LED Link/Activity Mode.................................................................................. 32
Serial LED Fully Mode ............................................................................................. 33
Fiber FXSD application circuit.................................................................................. 34
6 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
Revision History
Revision #
Date
Change Description
IP178G/GI-DS-R01
2012/07/06
Initial release
IP178G-DS-R02
2014/06/16
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
IP178G-DS-R03
2014/10/17
1. Modify Pin No.49、50 Description – page 17
2. Modify Pin No.40 AUTO_FACTORY_TEST Type IPL – page 14
IP178Gx-DS-R04
2014/12/03
Add GHI package description.
IP178Gx-DS-R05
2015/03/18
1. Add LED blink behave description – page 33
2. The IP178GHI rename to IP178GI for product management. –All
Add 1.1V power pin description – page 19
Delete default VLAN Information TPID description – page 68
Remove IP178GA / IP178GI description
Add LDO parameter description – page 70
Add MDIO output delay Min. parameter description – page 72
Add PCB footprint – page 76
Add EEPROM interface description – page 25
Add IP178GI for wide operating temperature description
Delete “/109” DVDD pin 36,54 pin description – page 18
Update pin 41 “F_POWER_OFF_LED” description – page 18
Add Serial LED mode Update Fast description – page 48
Update WOL function enable register from Reg 20 to Reg 22 –
page 22
13. Update WOL function enable Reg 22[15:8] default value from ff
to 00– page 64
7 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
Features comparison between IP178D and IP178Gx
Table 1 IP178D and IP178Gx Features comparison table
Function
IP178D
IP178G
IP178GH/GI
Process
0.16 um
85 nm
Package
PQFP 128
QFN 68
Switch structure
8 port Embedded 10/100 PHY Switch Controller
Port based priority
Yes
802.1p priority
Support Fiber function
VLAN
Yes
2 ports with FXSD
No
2 ports with FXSD
Port base / insert, remove tag
Tag base
No
IP DiffServ Priority
Yes
Port mirroring
Yes
Pins configure for port-priority
Yes
Reduce IPG function
Yes
TCP/UDP port number priority
Yes
Port trunking
No
Yes
Auto Factory Test (AFT®)
No
Yes
IEEE 802.3az
No
Yes
WOL+®
No
Yes
PWD (Force off power key)
No
Yes
1.9W
0.95W
IC Power consumption (Max)
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Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
1
Pin diagram
1.1
IP178Gx Pin diagram (QFN68)
(8mm X 8mm Top view)
RXIM2
RXIP2
AV10
RXIP1
RXIM1
TXOP1
TXOM1
AV33
TXOM0
TXOP0
RXIM0
RXIP0
PVDD_LDO
VREG_LDO
DVDD
SDA/MDIO
SCL/MDC
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
TXOP2
1
51
WOL_EN
TXOM2
2
50
LINK_LED0/FX_DUPLEX6
AV33
3
49
LINK_LED1/FX_DUPLEX7
TXOM3
4
48
LINK_LED2/SDATA/COS_DIS
TXOP3
5
47
LINK_LED3/SCLK/BF_STM_DIS
RXIM3
6
46
LINK_LED4/RSVD_GMAC_FILTER
RXIP3
7
45
PVDD
BGRES
8
44
LINK_LED5/HIGH_PRI[0]
BGGND
9
43
LINK_LED6/HIGH_PRI[1]
PLLGND
10
42
LINK_LED7/HIGH_PRI[2]
PLLVCC
11
41
F_POWER_OFF_LED/VLAN_DIS
RXIP4
12
40
AUTO_FACTORY_TEST
RXIM4
13
39
PVDD
TXOP4
14
38
TEST
TXOM4
15
37
F_POWER_OFF
AV33
16
36
DVDD
TXOM5
17
35
RESETB
IP178Gx
69 E-Pad Ground
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
TXOP5
RXIM5
RXIP5
AV10
FXSD6(GH/GHI)/GND(G/GI)
RXIP6
RXIM6
TXOP6
TXOM6
AV33
TXOM7
TXOP7
RXIM7
RXIP7
OSCI
X2
FXSD7(GH/GHI)/GND(G/GI)
Exposed pad (pad 69) is system GND, must be soldered to PCB ground plane
Figure 1 Pin Diagram (IP178Gx)
9 / 77
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
2
IP178Gx application diagram
2.1
An 8 TP port switch application
Here shows the application diagram of 8-port switch.
IP178G
Switch engine
MAC 0 MAC 1
MAC 2
MAC 3
MAC 4
MAC 5
MAC 6
MAC 7
PHY 0
PHY 2
PHY 3
PHY 4
PHY 5
PHY 6
PHY 7
PHY 1
TP
2.2
An 8-port switch mixed with two fiber ports
IP178GH/GI
Switch engine
MAC 0 MAC 1
MAC 2
MAC 3
MAC 4
MAC 5
MAC 6
MAC 7
PHY 0
PHY 2
PHY 3
PHY 4
PHY 5
PHY 6
PHY 7
PHY 1
Fiber
MAU
TP
10 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
2.3
TCP/UDP QoS Switch for time-sensitive application from EEPROM setting
IP178Gx
High
Priority
Low
Priority
Low
Priority
Low
Priority
Low
Priority
Low
Priority
Low
Priority
Low
Priority
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
24C01~16
TP
Port 0 received packet with reserved TCP/UDP port number, Port 0 will enable its
ingress port as a high priority port for 300 seconds.
If the other ports received packets with the same reserved port number, it also has the
same behavior as port 0.
2.4
Switch with VIP ports for specific users from Pin setting
IP178Gx
VIP
Port 0
VIP
Port 1
VIP
Port 2
Port 3
Port 4
VIP
Port 5
VIP
Port 6
VIP
Port 7
TP
VIP port setting as follow,
HIGH_PRI[2:0]
IP178GX Pin 42,43,44
001
010
011
101
110
000
111
high priority port number
6, 7
5, 6, 7
7
0, 1
0, 1, 2
0
disable (default)
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Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
2.5
A 8-port Switch with Port mirror capability setting from EEPROM
IP178Gx
Switch engine
24C01~16
MAC 0 MAC 1
MAC 2
MAC 3
MAC 4
MAC 5
MAC 6
MAC 7
PHY 0
PHY 2
PHY 3
PHY 4
PHY 5
PHY 6
PHY 7
PHY 1
TP
Port 7 RX/TX traffic
Port 7 RX/TX traffic
Port 1 could mirror Port 7 RX/TX
traffic via EEPROM setting
Router
12 / 77
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WAN
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
3
Pin description
Table 2 Pin description
Type
Description
Type
Description
I
Input pin
IPL
Input pin with internal pull low 100K ohm
O
P
Output pin
Power or Ground
IPH
Input pin with internal pull high 200K ohm
3.1
Analog pins
Pin No.
Label
Type
Description
LDO Regulator
LDO regulator output
It is an output power pin for 1.1V power source.
LDO regulator input
56
PVDD_LDO
P
It is an input power pin for reference voltage.
IP178Gx includes a LDO regulator to convert 3.3V to 1.1V.
55
3.2
VREG_LDO
P
MDI (Media Dependent Interface)
Pin No.
Transceiver
57, 58,
65, 64,
67, 68,
7, 6,
12, 13
20, 19
23, 24
31 30
59, 60,
63, 62,
1, 2,
5, 4,
14, 15
18, 17
25, 26
29, 28
Label
RXIP0, RXIM0,
RXIP1, RXIM1,
RXIP2, RXIM2,
RXIP3, RXIM3,
RXIP4, RXIM4
RXIP5, RXIM5
RXIP6, RXIM6
RXIP7, RXIM7
TXOP0, TXOM0,
TXOP1, TXOM1,
TXOP2, TXOM2,
TXOP3, TXOM3,
TXOP4, TXOM4
TXOP5, TXOM5,
TXOP6, TXOM6,
TXOP7, TXOM7,
Type
Description
I
TP receive
O
TP transmit
22
34
FXSD6/GND
FXSD7/GND
I
8
BGRES
O
Fiber signal detection of port 6,7 (Only for GH/GI)
Port 6,7 can be configured to be either a TP port or a Fiber
port with this pin. Connect this pin to GND for TP mode,
and do not left this pin floating. Please refer to the
paragraph “I/O Electrical Characteristics” for more detail
information.
In IP178G these pin should be connected to ground.
Band gap resistor.
It is connected GND through a precision resistor
(R=6.19K, 1%) for band gap reference. Please refer to
application circuit for more information.
13 / 77
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
3.3
System clock & reset pins
Pin No.
Label
Type
Description
25MHz system clock input
32
OSCI
I
33
X2
O
It is recommended to connect OSCI and X2 to a 25MHz
crystal.
If the clock source is from another chip or oscillator, the
clock should be active at least for 10ms before pin 35
RESETB de-asserted.
Pin 33 X2 should be left open in this application.
Crystal pin
A 25Mhz crystal can be connected to OSCI and X2.
Reset
It is a low active input pad with Schmitt trigger. The reset
time must be hold for more than 10 ms. If an R/C reset
circuit is used; the capacitor should be connected to GND
as shown in the figure.
35
RESETB
PVDD
IPH
R
RESETB
C
3.4
Boundry scan & test mode
Pin No.
Label
Type
Description
38
TEST
IPL
Test mode enable
It should be connected to GND for normal operation
40
AUTO_FACTO
RY_TEST
IPL
Auto Factory Test (AFT®) enable pin
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
3.5
EEPROM interface /SMI (Serial Management interface)
Pin No.
Label
Type
Description
EEPROM (only 24C01~16 supported)
52
SCL/MDC
IPL/I
After reset, it is used as clock pin SCL of EEPROM. Its
period is longer than 10us. IP178Gx stops reading
EEPROM if it finds there is no 0x55AA pattern in address 0.
After reading EEPROM, this pin will switch to SMI mode
MDC input.
53
SDA/MDIO
IPH,
I/O
After reset, it is used as data pin SDA of EEPROM.
A bi-directional multi-drop bus for accessing the internal
registers.
It’s recommended to add a 4.7K pull up resistor connecting
to PVDD and a 30pf capacitor connecting to ground.
After reading EEPROM, this pin will switch to SMI mode
MDIO for read/write internal register.
15 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
3.6
Frame priority setting pins
Pin No.
Label
Type
Description
Port based priority setting, bit 0
It is an input signal during reset and its value is latched at
the end of reset. It acts as a link LED of port 5 after reset.
44
HIGH_PRI[0]
IPH/O
VIP port setting as follow,
HIGH_PRI [2:0]
Pin 42, 43, 44 –IP178Gx
high priority port number
001
010
011
101
110
000
111
Port based priority setting, bit 1
43
HIGH_PRI[1]
IPH/O
6, 7
5, 6, 7
7
0, 1
0, 1, 2
0
disable (default)
For the port based priority setting, reference HIGH_PRI[0]
setting as detail.
It is an input signal during reset and its value is latched at
the end of reset. This pin acts as a link LED of port 6 after
reset.
Port based priority setting, bit 2
42
HIGH_PRI[2]
IPH/O
For the port based priority setting, reference HIGH_PRI[0]
setting as detail.
It is an input signal during reset and its value is latched at
the end of reset. This pin acts as a link LED of port 7 after
reset
Class of service disable
Packets with high priority tag are handled as high priority
packets if the function is enabled.
48
COS_DIS
IPH/O
1: COS disabled (default)
0: COS enable.
It is an input signal during reset and its value is latched at
the end of reset. It acts as a link LED of port 2 after reset.
16 / 77
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
3.7
Pin No.
Miscellaneous setting pins
Label
Type
Description
Misc.
Force Power Off function for power saving setting pin
37
F_POWER_OFF
IPH/I
It should be connected to PVDD for normal operation; pull
low 3 seconds to enable Force Power Off function.
Home VLAN setting enable setting pin.
Port 0~Port 6 are all individual VLAN and only send to port 7.
41
VLAN_DIS
IPH/O
1: disable (default)
0: enable
It is an input signal during reset and its value is latched at the
end of reset. This pin acts as a F_POWER_OFF_LED after
reset
Reserved group address filtering
46
RSVD_GMAC_FILTER
IPH/O
It configures how to process the reserved group address,
detail see 4.2.
Broadcast storm protection enable
This function defined in MII register 20.1[6]
1: disable (default)
0: enable
47
BF_STM_DIS
IPH/O A port begins to drop incoming packets if it receives
broadcast packets more than the threshold defined in MII
register 20.9[15:14]
It is an input signal during reset and its value is latched at the
end of reset. This pin acts as a link LED of port 3 after reset
Port 7 fiber port half duplex setting pin
49
FX_DUPLEX7
IPH/O
1: port 7 is full duplex in fiber mode (default)
0: port 7 is half duplex in fiber mode
Port 6 fiber port half duplex setting pin
50
FX_DUPLEX6
IPH/O
1: port 6 is full duplex in fiber mode (default)
0: port 6 is half duplex in fiber mode
Wake on LAN enable
51
WOL_EN
IPL/O
1: enable
0: disable (default)
17 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
3.8
LED interface
Pin No.
Label
Type
Description
LED
50
49
48
47
46
44
43
42
LINK_LED0
LINK_LED1
LINK_LED2
LINK_LED3
LINK_LED4
LINK_LED5
LINK_LED6
LINK_LED7
41
F_POWER_OF
F_LED
LINK LED
The detail functions are illustrated in 4.12~4.13. It
should be connected to PVDD through a LED and
resistor.
Application circuit
IPH/O
LINK_LEDX
F_POWER_OFF_LED
R
PVDD
Force Power Off function LED
It is always low in normal operation and it becomes high
if "Force Power Off" function is enabled by pulling low
pin 37 for more than 3 seconds.
Serial LED (Enable by MII page 3 register 16)
48
SDATA
IPH/O LED serial data
LED serial clock
47
SCLK
PH/O
It is a 312.5KHz clock.
3.9
Power & ground pads
Pin No.
Label
Type
Description
9
BGGND
P
Ground of band gap circuit
10
11
PLLGND
PLLVCC
P
P
Ground of PLL circuit
Power of PLL circuit
36,54
DVDD
P
1.1V Core power
These pins must be connect to pin 55 VREG_LDO via a
resister or bead, do not connect to external power supply
21,66
AV10
P
1.1V Analog power
These pins must be connect to pin 55 VREG_LDO via a
resister or bead, do not connect to external power supply
3,16
27,61
AV33
P
3.3V Analog power
39,45,
PVDD
P
3.3V power
E-pad GND
P
Exposed pad for system ground, must be soldered to
PCB ground plane
69
18 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4
Functional Description
4.1
Switch Engine and Queue Management
4.1.1
Switch Engine
IP178Gx integrates an 8-port switch controller, SSRAM, and 8 10/100 Ethernet transceivers. Each of the
transceivers complies with the IEEE 802.3, IEEE 802.3u, and IEEE 802.3x specifications. IP178Gx
offers all the rich features of a high-speed broadband wire Internet services including non-blocking
switch fabric
4.1.2
Packet Forwarding
IP178Gx utilizes the “store & forward” method to handle packet transfer. IP178Gx begins to forward
a packet to a destination port after the entire packet is received. A received packet will be forwarded to
the destination port only if it is error free; otherwise, it will be discarded.
4.1.3
Flow control
IP178Gx jams or pauses a port, which causes output queue over the threshold. Its link partner will defer
transmission after detecting the jam or pause frame. A port of IP178Gx defers transmission when it
receives a jam or a pause frame. The source address (SA) of pause control frame will be [ IP178Gx OUI
(0090C3), port number]. For example, the SA of port 1 pause control frame will be “ 00 90 C3 00 00 01”.
When CoS is enabled, IP178Gx may disable the flow control function for a short term to guarantee the
bandwidth of high priority packets. A port disables its flow control function for 2 ~ 3 seconds when it
receives a high priority packet. It doesn’t transmit pause frame or jam pattern during the period but it still
responses to pause frame or jam pattern.
The flow control function can be enabled by programming registers 0.4[11:10] ~ 7.4[11:10] for 8 PHY.
4.1.4
Backpressure
In half duplex mode, the IP178Gx supports backpressure flow control. When set BK_EN of MII
register 20.1[8] to “1”, the packets in buffer reach the threshold, IP178Gx generates a jam pattern to back
off the link partner. IP178Gx supports carrier-sense based backpressure. When the carrier-sense based
backpressure is enabled, MII register 20.1[7] is set to “0”, and IP178Gx transmits null packets
continuously to prevent link partner’s transmission when the buffer is not available.
4.1.5
Broadcast storm protection
A port of IP178Gx begins to drops broadcast packets if the received broadcast packets are more than the
threshold defined in MII register 21.9[15:14] BF_STM_THR_SEL [1:0] in 10ms (100Mbps) or 100ms
(10Mbps)
The function can be enabled by pulling low pin 47 BF_STM_DIS or programming MII register 20.1[6].
IP178Gx handles multicast frame as a broadcast frame in broadcast storm protection function if MII
register 21.30[12] is set to “0”
19 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.2
Rserved Group MAC Address
The table shows the reserved group address for standard use and how frames are processed.
Table 3 Rserved Group MAC Address table
Action
MAC Address
01-80-c2-00-00-00
01-80-c2-00-00-01
01-80-c2-00-00-02
01-80-c2-00-00-03
01-80-c2-00-00-04
01-80-c2-00-00-05
01-80-c2-00-00-06
01-80-c2-00-00-07
01-80-c2-00-00-08
01-80-c2-00-00-09
01-80-c2-00-00-0A
01-80-c2-00-00-0B
01-80-c2-00-00-0C
01-80-c2-00-00-0D
01-80-c2-00-00-0E
01-80-c2-00-00-0F
01-80-c2-00-00-10
01-80-c2-00-00-11to1F
01-80-c2-00-00-20
01-80-c2-00-00-21
01-80-c2-00-00-22to2F
01-80-c2-00-00-30to3F
01-80-c2-00-00-40to4F
Protocol
RSVD_GMAC_FILTER=1
RSVD_GMAC_FILTER =0
(default)
Bridge Group Address
MAC Control of IEEE 802.3
Slow protocol address:
802.3ad LACP, 802.3ah OAM
802.1x
Reserved for future media
access method
Reserved for future media
access method
Reserved for future bridge use
Reserved for future bridge use
Provider bridge group address
Reserved for future bridge use
Reserved for future bridge use
Reserved for future bridge use
Reserved for future bridge use
Provider bridge GVRP address
802.1AB LLDP
Reserved for future bridge use
All bridges address
Others
GMRP
GVRP
Reserved for future use
802.1ag
Others
20 / 77
Copyright © 2014, IC Plus Corp.
Forward
Drop
Forward
Drop
Forward
Forward
Forward
Forward
Drop
Forward
Drop
Forward
Drop
Drop
Drop
Drop
Drop
Drop
Drop
Drop
Forward
Drop
Drop
Forward
Drop
Drop
Drop
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
Forward
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.3
Green Power
IP178Gx provides various power management modes to save the power consumption. In addition
to the power down mode defined on IEEE802.3, two extra power saving modes are used to further
reduce the system power consumption.
4.3.1
Auto Power Saving Mode
IP178Gx will automatically enter this mode if no cable link is established. After entering this mode,
IP178Gx will shutdown unnecessary function and issue the link pulse at a rate lower than the regular rate
specified on IEEE 802.3.
4.3.2
IEEE802.3az EEE (Energy Efficient Ethernet)
In order to enter this mode, the PHY part should declare the EEE capability during the
auto-negotiation phase.
It’s the higher layer’s responsibility to memorize the link partner’s wakeup time and wakeup the link
partner before sending data. The higher layer means a mechanism that can evaluate the packet buffer
utilization and wake the link partner before sending the data. In general speaking, this mechanism
probably consists of at least one of the following items: the packet buffer manager, the application
program and OS.
The EEE module works well at LPI (Low Power Idle) mode when
1. Link at full-duplex and
2. Auto-negotiation is enabled in both local and remote PHYs and
3. 100Mbps full duplex and
4. EEE ability is supported in both local & remote PHYs and
5. EEE_EN (Reg 22.0[7:0]) is enabled for EEE function via default value and
6. SLEEP_TIMER (Reg 22.1[11:0]) is the default value for EEE sleep timer and
7. WAKE_TIME (Reg 22.2~9) is the default value for EEE wake time.
4.3.3
WOL+ (Wake On LAN Plus)
IP178Gx not only consumes low power, but also provides various energy-saving methods to save
the power. These combined methods make IP178Gx a “green” PHY. The following pictures show the
method.
IP178G
No-Traffic leads it to sleep
IP178G
Packet wakes it up
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Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
Figure 2 WOL+ Application Diagram
The IP178Gx WOL+ function will be active if a port’s RX is in idle state for a period time and this
port WOL+ function is enabled (by pin 51 or Reg 22.10[15:8]). This period time can be configured by
WOL+ timer register (Reg22.10[1:0]).
This port will be wake up if
a) Sense magic packet;
b) Sense link change;
c) Sense any packet;
The packet format of Magic packet is showing as follows, source address=0x112233445566 for
example, repeat this source address 16 times at least.
Received Packet
0xFFFFFFFFFFFF
0X112233445566
0X112233445566
0X112233445566
0X112233445566
0X112233445566
0X112233445566
>16 times
Figure 3 Magic Packet Format
.
4.3.4
Force Power Off
When “Force power off enable” (pin 37) is pull low for 3 seconds, IP178Gx will enter force power off
mode. If “Force power off enable” pin pull low for 3 seconds again, IP178Gx will return normal mode.
The expired timer (default value is 3 seconds) is configurable in “FORCE_POWER_OFF_TIME” (MII
Register 21.10[7:6]).
IP178Gx
Force ON / OFF
( rBOM = 1 push buttom,the others take care by the chip.)
Figure 4 Force Power Off Application Diagram
22 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.4
Auto Factory Test (AFT) Mode
IP178Gx implements an AFT mechanism, which is very useful for switch pre-test as Figure 4 AFT
system diagrams. When this function is triggered by hardware pin AFT, IP178Gx physical ports are
connected either port-pairs loopback or self-loopback and then IP178Gx will generate frames for TX of
all ports and LED will flash.
For example, port1 and port2 are connected to each other (loopback). Check the LED of port1 and
port2 is light-on, and then trigger this AFT function and wait a moment trigger again. If the test result is
passed (no CRC or packet loss), show LED of port1 and port2 light-on. Otherwise, show LED light-off
when CRC or packet loss is happened.
Procedure:
1. Power On
2. Wait for someone Push AFT button to start test
3. IP178Gx transmit packet and LED flash
4. If Push AFT button then goto step 5, else goto step 3
5. LED Show the test result, goto step 2
PVDD
IP178Gx
AFT
P0
P1
P2
P3
P4
P5
P6
P7
RJ45 Cable loopback
Pin1Ù Pin3
Pin2Ù Pin6
External loopback path
Figure 5 Auto Factory Test Application Diagram
4.5
Reset
Hardware Reset: Hardware pin RESETB should be asserted LOW at least for 10ms to reset
IP178Gx, and gets initial values from pins, registers and EEPROM after reset.
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Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.6
Serial management interface
User can access IP178Gx’s MII registers through serial management interface with pin MDC and MDIO.
Its format is shown in the following table. To access MII register in IP178Gx, MDC should be at least one
more cycle than MDIO. That is, a complete command consists of 32 bits MDIO data and at least 33 MDC
clocks. When the SMI is idle, MDIO is in high impedance.
System diagram
CPU
IP178Gx
MDC
MDIO
MDC
MDIO
Frame
format
Read
Operation
Write
Operation
Figure 6 Serial management interface Read / Write Diagram
MDC
z
z
MDIO
1..1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1..1
idle
op
start code
write
A A A A A R R R R R TA b b b b b b b b b b b b b b b b
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
4 3 2 1 0 4 3 2 1 0
PHY address =
Reg address =
5 4 3 2 1 0
Register data
01h
00h
idle
MDC
MDIO
z
z
z
1..1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1..1
idle
op
start code
read
A A A A A R R R R R TA b b b b b b b b b b b b b b b b
1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
4 3 2 1 0 4 3 2 1 0
PHY address =
Reg address =
5 4 3 2 1 0
Register data
01h
00h
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Copyright © 2014, IC Plus Corp.
idle
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.7
EEPROM interface
IP178Gx supports EEPROM1 interface to program configuration registers during power-on reset.
When power on and EEPROM is present, if the fist 16-bit data match 0x55AA and then the data read
from EEPROM until that command-end pattern is read-in.
The EEPROM contents should be configured to three blocks: Command-Start, command and
Command-End. Each command contains the full address (PHY address + register address) that you
wish to configure as well as 16-bit data, for detail information shown as the following figure.
Offset
00
7
EEPROM
0xAA
0
Command-Start
01
0x55
02
SMI PHY Address
03
SMI Register
04
SMI Data High Byte
05
SMI Data Low Byte
06
SMI PHY Address
07
SMI Register
08
SMI Data High Byte
09
SMI Data Low Byte
.
.
.
.
st
1 Write
Command
nd
2 Write
Command
.
.
.
.
4*(N-1)+2
SMI PHY Address
4*(N-1)+3
SMI Register
4*(N-1)+4
SMI Data High Byte
4*(N-1)+5
SMI Data Low Byte
4*(N-1)+6
0x55
4*(N-1)+7
0xAA
th
N Write
Command
Command-End
Figure 7 EEPROM data format
1
Only 24C01, 24C02, 24C04, 24C08 & 24C16 supported.
4.7.1
Example: Configure port based VLAN of IP178Gx
Member set: Group A – Port 0, 1, 4
Group B – Port 2, 3, 4
IP178Gx Register Setting:
Phy 23.16 = 16’h8c8c
Phy 23.17 = 16’hffd0
Phy 23.18 = 16’hdcd0
Serial EEPROM data: AA 55 17 10 8C 8C 17 11 FF D0 17 12 DC D0 55 AA
25 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.8
CoS
IP178Gx supports two types of CoS. One is port base priority function and the other is frame base
priority function. IP178Gx supports two levels of priority queues. A high priority packet will be queued to
the high priority queue to share more bandwidth. The ratio of bandwidth of high priority and low priority
queue is defined in MII register 20.1[15].
4.8.1
Port base priority
The packets received from high priority port will be handled as high priority frames if the port base priority
is enabled. It is enabled by programming the corresponding bit in MII register 21.0[9] ~ 21.7[9]. Each
port of IP178Gx can be configured as a high priority port individually.
4.8.2
VIP ports
This port based priority function can active either by register or pin setting. There are three pins dedicate
for enabling the port based priority function. The follow illustration shows the pin setting part of the port
based priority function.
Table 4 VIP port pin setting table
IP178Gx pin number
Pin name
42
HIGH_PRI[2]
HIGH[2:0]
001
010
011
101
110
000
111
43
HIGH_PRI[1]
High priority port
6, 7
5, 6, 7
7
0, 1
0, 1, 2
0
Disable (default)
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Copyright © 2014, IC Plus Corp.
44
HIGH_PRI[0]
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.8.3
Frame base priority
4.8.3.1
VLAN tag and TCP/IP TOS
IP178Gx examines the specific bits of VLAN tag and TCP/IP TOS for priority frames if the frame base
priority is enabled. The packets will be handled as high priority frames if the tag value meets the high
priority requirement, that is, VLAN tag or TCP/IP TOS field bigger than 3. It is enabled by programming
the corresponding bit in MII register 21.0[10]~21.7[10]. The frame base priority function of each port can
be enabled individually.
IP178Gx supports an easy way to enable a sub set of CoS function without programming MII registers.
Frame base priority function of all ports is enabled if pin 48 COS_DIS is pulled low. The setting in register
takes precedence of the setting on pins.
VLAN field
TCI difinition
TYPE= 8100 TCI(Tag Control Information)
Byte
12~13
14~15
ToS field
TYPE= 0800
Byte
12~13
bit [15:13] : User ptiority 7~0
bit 12 : Canoical Format Indicator (CFI)
bit [11:0] : VLAN ID
IP178Gx uses bit[15:13] to define priority.
IP header difinition
IP header
14~15
Byte 14
bit [7:0] : IP protocol version number & header length
bit [11:0] : VLAN ID
IP178Gx uses bit[15:13] to define priority.
Byte 15 : Service type
bit [7:5] : IP Priority (Precedence) from 7~0
bit 4 : No Delay (D)
bit 3 : High Throughput
bit 2 : High Reliability (R)
bit [1:0] : Reserved
IP178Gx uses bit[7:5] to define priority.
0~3 : Low priority
4~7 : High priority
Figure 8 VLAN tag and TCP/IP TOS frame
27 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.8.3.2
IPv4/IPv6 DiffServ
IP178Gx checks the DiffServ field of a IPv4 frame or Traffic class field [7:2] (TC[7:2]) of a IPv6 frame and
uses them to decide the frame’s priority if MII register 21.30.[13] DIFFSERV_EN is enabled. IP178Gx
uses DiffServ or TC[7:2] as index to select one of 64 bits. If the bit is “1”, the received frame is handled as
a high priority frame. IP178Gx recognize the following DSCP (Differentiated Service Code Point) Octet
as high priority frame.
6’b101110
6’b001010
6’b010010
6’b011010
6’b100010
6’b11x000
IPv4 frame format
6 byte
Preamble
SFD
DA
6 byte
4 byte
2 byte
SA
802.1Q tag
(optional)
TYPE=0800
2 byte
DATA
VER=0100
Header
Size
DiffServ
RES
4 bit
4 bit
6 bit
2 bit
FCS
IPv6 frame format
6 byte
Preamble
SFD
DA
6 byte
4 byte
2 byte
SA
802.1Q tag
(optional)
TYPE=86DD
2 byte
DATA
FCS
VER=0110
Traffic Class[7:2]
RES
----
4 bit
6 bit
2 bit
4 bit
Figure 9 IPv4/IPv6 DiffServ frame
28 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.8.3.3
TCP/UDP logical port priority
IP178Gx can configure the ingress port frame priority by using the TCP/UDP frame logical port number.
When the incoming IP packet with TCP or UDP protocols, the 16 bits destination or source port field in
the TCP/UDP header can be used for assign the frame priority. It means the source’s logical port or the
destination’s logical port in the incoming packet match any of the pre-defined logical ports, the incoming
frame will give a high priority mark and put it in the high priority queue.
TCP/UDP logical port priority function of all ports is enabled if pin 48 COS_DIS is pulled high. The logical
port priority of each pre-defined port number or user defined range of logical port number can be enabled
individually by programming the corresponding bit in the MII register 20.14[5:0].
Table 5 TCP/UDP logical port priority table
Pre-defined logical ports list
Service
TCP
SSH
22
HTTPs
443
RDP
3389
XWIN
6000
Description
secure shell
secure HTTP (SSL)
Windows Remote Desktop Protocol
X11 – used for X-Windows
When the “LPP_AGING_EN (MII register 20.14[15:8])” function enable, once receive a IP frame with
TCP/UDP protocol and the logical port number is the pre-defined port number, the ingress port will treat
as a port based high priority port for 300 seconds. After the internal timer expired, the ingress port will
change back to previous behavior
These pre-defined logical ports can be enable individually by programming MII register 20.14[3:0] or
EEPROM register 10[3:0].
User defined range logical ports list (defaulting setting)
Service
TCP
Description
telnet
23
Remote terminal protocol
VNC
5800
VNC remote desktop protocol
For the user defined range logical ports, it contains two set of range and can be changed by
programming via MII register or EEPROM register. Each range consists of a high and low limit register to
set the TCP or UDP logical port range. The high limit port number can not large than the low limit port
number. The default logical port number of range 0 and 1 are default set to 23 and 5800, for this case the
high and low limit port number is the same value. If an incoming IP frame with TCP/UDP port number is
between the low and high limit, it will be treated as a high priority frame.
4.9
Port Mirroring
There are some circumstances that the network administrator requires to monitor the network
status. The port mirroring function can help the network administrator diagnose the network.
A port mirroring function can be accomplished through assigning 1 to 7 monitored ports and a
snooping port. The IP178Gx supports four kinds of monitoring methods: RX(ingress), TX(egress),
RX-and-TX, and RX-or-TX. This function can be enabled by programming the corresponding bit in MII
registers 20.3 ~ 20.4.
For example, if designer wants to monitor the output traffic of port5 and port4 as shown in the
following figure. He has to write “2’b01” to register 20.3[14:13] to choose monitor method to be TX traffic,
write 0x30 to registers 20.4[7:0] to select port5 and port4 to be monitored ports, write 1’b1 and 3’b000 to
registers 20.3[15] and 20.4[15:13] to select port0 as a monitoring port. IP178Gx will copy tx traffic of
port5 and port4 to port0.
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Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
Figure 10 Port Mirroring Security Block Diagram
4.10 Link Aggergation
Link aggregation is used to provide a large throughput between two network nodes by using the
method of grouping a set of ports. If some of ports are in a trunk group, all ports in that trunk group shall
be in the same VLAN group.
Each trunk group may comprise 2 to 6 ports. Designer can configure the trunk group members
individually by writing non-zero values to the corresponding bits of a port in the registers 22.12[7:0] and
22.13[7:0] for trunk group 0 and trunk group 1. A trunk channel works as if a “big” port with multiple times
of bandwidth. If the destination port of a packet is un-link, IP178Gx forwards the packet to the other port
of the trunk (auto recovery).
port2
Trunk 0:
port1
port0
Port1 un-link
Traffic is changed from port1
to port0
Figure 11 Trunk Channel Behavior Block Diagram
To fully utilize the bandwidth in a trunk channel, IP178Gx supports load balance function. A physical
port of a trunk forwards a packet only if the trunk group of the packet matches the group setting of the
port. That is, when a packet is forwarded to a port in a trunk, its destination port is according to trunk
group.
The aggregation mode determines which index would be used to search aggregation mask table.
Here provide four ways: the four LSB of the SMAC, the four LSB of the DMAC, the four LSB of the SMAC
xor DMAC, and Source port ID.
Link aggregation function only uses a 3-bit index to search aggregation mask table. To achieve it,
the aggregation index selection is used to extract a 3-bit index from the mentioned in AGGR_MODE.
If the destination port of a trunk is un-link, the packet will be forward the port shifted by 2. If the port
is un-link, too, the packet will be forward the port shifted by 3. For example, if port 3 is un-link, its packet
will be forwarded to port 5. If port 5 is un-link, too, the packet will be forwarded to port 4.
30 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
Packet
Trunk 0:
Source port ID
DA
SA
Hashing
(2 LSB)
Register 22.12[7:0]
defines the group to be
forwarded
port0
port1
Trunk
ID
(2 bits)
Trunk 1:
Register 22.13[7:0]
defines the group to
be forwarded
port3
port4
port5
destination port shifted
due to un-link
Register 22.11[2:0]
Figure 12 Load Balance Block Diagram
Link aggregation example:
Here have two trunk groups.
Trunk 0: port 0, 1
Trunk 1: port 5, 6, 7
The link aggregation parameters are set as:
AGGR_MODE: The aggregation mode determines which index would be used to search aggregation
mask table. Here provide four ways:
The four LSB of the SMAC
The four LSB of the DMAC
The four LSB of the SMAC xor DMAC
Source port ID
PHY22 REG11[2:0] = 0x0
(AGGR_MODE = SMAC)
AGGR_IDX_SEL: Link aggregation function only uses a 3-bit index to search aggregation mask table. To
achieve it, the aggregation index selection is used to extract 3-bit index from the mentioned in
AGGR_MODE.
PHY22 REG11[4:3] = 0x0
(AGGR_IDX_SEL = index[2:0])
AGGR_GROUP: The port mask is logically grouping a set of ports.
PHY22 REG21[7:0] = 0x03
(AGGR_GROUP0: port 0 and port 1)
PHY22 REG22[7:0] = 0xe0
(AGGR_GROUP1: port 5, 6, 7)
Aggregation mask table:
PHY22 REG14[7:0] = 8’b0011_1101
PHY22 REG15[7:0] = 8’b0101_1110
PHY22 REG16[7:0] = 8’b1001_1101
PHY22 REG17[7:0] = 8’b0011_1110
PHY22 REG18[7:0] = 8’b0101_1101
PHY22 REG19[7:0] = 8’b1001_1110
PHY22 REG20[7:0] = 8’b0011_1101
PHY22 REG21[7:0] = 8’b0101_1110
(AGGR_MASK0)
(AGGR_MASK1)
(AGGR_MASK2)
(AGGR_MASK3)
(AGGR_MASK4)
(AGGR_MASK5)
(AGGR_MASK6)
(AGGR_MASK7)
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Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.11 Buffer Aging
When buffer aging was enabled, a frame stayed in output port for transmission is discarded if buffer
aging time has exceeded one second. The buffer aging time is the maximum delay time for transmission
on output port. This function can be set from MII register 20.13[13].
4.12 LED display (normal operation)
Normal operation
LED_O_SEL[1:0]
00
01
10
11
LINK_LED
SPEED_LED
FDX_LED
Off: 100 Mbps link fail
On: 100 Mbps link ok
Flash: TX/RX
Off: no collision
Flash: collision
Off: 10 Mbps link fail
On: 10 Mbps link ok
Flash: TXRX
Off: link fail
On: link ok
Off: 10 Mbps
On: 100 Mbps
Off: half duplex
On: full duplex
Flash: collision
Off: 100 Mbps link fail
On: 100 Mbps link ok
Flash: TX/RX
Off: link fail
On: link ok
Flash: TX/RX
Off: half duplex
On: full duplex
Flash: collision
Off: 10 Mbps
On: 100 Mbps
Off: 10 Mbps link fail
On: 10 Mbps link ok
Flash: TXRX
Off: half duplex
On: full duplex
Flash: collision
Flash behavior: Off 105ms Æ On 105ms Æ Off 105ms Æ …
4.13 Serial LED Mode
IP178Gx supports serial LED mode and can be setting MII register SERIAL_LED_EN to 1 by MII
page3 register 16[12].
There are no enough pins for LED and IP178Gx sends out LED information through pin 47 (SCLK) and
pin 48 (SDATA). It is necessary to use TTL chip to decode and drive LED. The application circuit is
shown below.
IP178Gx supports two types of serial LED mode and can be setting by MII page3 register 16[11]. The
default value is 0 (SERIAL_LED_MODE = 0) and can be setting to 1 by MII page3 register 16[11].
4.13.1
Supports link LED only
IP178GX supports link LED only when setting SERIAL_LED_MODE to 1 and SERIAL_LED_EN to
1.
PVDD
SDATA
SCLK
PVDD
A
CLK
74HC164
B
RESET
CLR
QA
PORT 7 LINK/ACT LED
QB
PORT 6 LINK/ACT LED
QC
PORT 5 LINK/ACT LED
QD
PORT 4 LINK/ACT LED
QE
PORT 3 LINK/ACT LED
QF
PORT 2 LINK/ACT LED
QG
PORT 1 LINK/ACT LED
QH
PORT 0 LINK/ACT LED
Figure 13 Serial LED Link/Activity Mode
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.13.2
Supports link, speed, and duplex LED
IP178Gx supports link, speed, and duplex LED when setting SERIAL_LED_MODE to 0 and
SERIAL_LED_EN to 1.
PVDD
SDATA
A
SCLK
CLK
PVDD
74HC164
B
RESET
CLR
QA
PORT 7 LINK/ACT LED
QB
PORT 6 LINK/ACT LED
QC
PORT 5 LINK/ACT LED
QD
PORT 4 LINK/ACT LED
QE
PORT 3 LINK/ACT LED
QF
PORT 2 LINK/ACT LED
QG
PORT 1 LINK/ACT LED
QH
PORT 0 LINK/ACT LED
PVDD
A
CLK
74HC164
B
CLR
QA
PORT 7 SPEED LED
QB
PORT 6 SPEED LED
QC
PORT 5 SPEED LED
QD
PORT 4 SPEED LED
QE
PORT 3 SPEED LED
QF
PORT 2 SPEED LED
QG
PORT 1 SPEED LED
QH
PORT 0 SPEED LED
PVDD
A
CLK
74HC164
B
CLR
QA
PORT 7 DUP/COL LED
QB
PORT 6 DUP/COL LED
QC
PORT 5 DUP/COL LED
QD
PORT 4 DUP/COL LED
QE
PORT 3 DUP/COL LED
QF
PORT 2 DUP/COL LED
QG
PORT 1 DUP/COL LED
QH
PORT 0 DUP/COL LED
Figure 14 Serial LED Fully Mode
4.14 LED Blink Timing
Table 6 LED Blink Timing
LED mode
Serial mode update period
Blinking speed
10ms
Active LED blink
Off 105ms Æ On 105ms Æ Off 105ms Æ …
Collision LED blink
Off 105ms Æ On 105ms Æ Off 105ms Æ …
Although the blinking period is the same for all ports, the LED of different port may
blink in differnet phase.
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
4.15 PAD Driving Calibration
This function illustrates the interface between switch and high speed pad groups for pad driving
calibration. In default the pad driving capability sets by switch MII register (PHY address 21
Reg10.[14:12). It also can automatically calibrate to determine pad driving and feedback it to the final
pad driving current.
4.16 Fiber port configuration
Port 6 and 7 of IP178GH/GI can be configured to be a fiber port or a TP port individually. A port becomes
a fiber port if its FXSDx is connected to a fiber MAU or pulled to high. A port becomes a TP port if it’s
FXSDx is pulled low.
Table 7 Fiber port parameter
Parameter
Fiber Rx common mode Voltage
Fiber Rx differential mode Voltage
PVDD = 3.3V
Voltage on FXSDx
< 0.4 V
> 1.2 V < 1.7 V
> 1.95 V < 3.3 V
TP port
Yes
---
Symbol
VFRC
VFRD
MIN.
0.4
Fiber port
-Yes
Yes
Type
AVDD*0.6
-
Fiber signal detect
-Off
On
MAX.
-
Uuit
V
V
Condition
Fiber unplugged
Fiber plugged
VCC_O
R1
SD
Fiber
MAU
R2
IP178GH
/GHI
FXSD
R1
R2
R3
R3
3V
1K
100
910
5V
470
300
330
Figure 15 Fiber signal detect application circuit
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
5
Register descriptions
The IP178Gx can be configured via external EEPROM interface at boot time. During operation,
IP178Gx registers are accessible via SMI interface.
5.1
Register map
5.1.1
MII register map
Table 8 MII register map table
15
14
13
12
11
10
20.0
20.1
priority
_rate
Reduce
drop16
_ipg
20.2
20.3
20.4
9
8
7
input
_filter
tmode_sel
port_mirror
_en
6
4
3
2
aging
port_mirror_mode
learn_dis_
pause
CRC_counter
thr_
setting
read_thr
pause_flag
wait_
backoff
share_high_threshold
unit_default_threshold
share_low_threshold
20.9
pkt_high_threshold
pkt_low_threshold
20.10
unit_high_threshold
unit_low_threshold
mon_en
unit_low_num
20.12
share_high_num
fiber_duplex[7:6]
20.14
buf_
src_blk_
aging_en protect
port_backpressure_en[7:0]
userdef_range
_en[1:0]
lpp_aging_en[7:0]
20.15
predef_port_en[3:0]
userdef_range0_high[15:0]
20.16
userdef_range0_low[15:0]
20.17
userdef_range1_high[15:0]
20.18
20.19
modbck
sel_tx_port_mirror
pause_trigger
20.8
20.13
0
sel_rx_port_mirror
sel_mirror_port
20.6
20.11
1
hash_ mode
20.5
20.7
5
Software Reset Register ( 55 AA )
modify_
bf_stm
carrier_ bk_en bp_kind
_en
algorithm
userdef_range1_low[15:0]
fast_
mode
test_latin
21.0
port0
_cos_en
port0_
high_
priority
21.1
port1
_cos_en
port1_
high_
priority
21.2
port2
_cos_en
port2_
high_
priority
21.3
port3
_cos_en
port3_
high_
priority
21.4
port4
_cos_en
port4_
high_
priority
21.5
port5
_cos_en
port5_
high_
priority
21.6
port6
_cos_en
port6_
high_
priority
21.7
port7
_cos_en
port7_
high_
priority
test_sel
21.8
21.9
21.10
bf_stm_ thr_sel
share_full _thr_sel unit_default_thr_sel
driver[2:0]
unit_low_thr_sel unit_high_thr_sel
bf_stm
hp_dis_f
twopart
_en
low_en
_qm
allpass
Predrop
_en
pkt_low_thr_sel
pkt_high_thr_sel
analog_off_time
21.11~29
21.30
diffserv_en bf_ffff_only
special_add_forward
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IP178G-DS-R05
IP178Gx
Data Sheet
6
PHY registers
Table 9 PHY Register Map
Page
0
Register
0
Control Register
Description
Default
Note
PHY 0~7
0
1
Status Register
PHY 0~7
0
2
PHY Identifier 1 Register
PHY 0~7
0
3
PHY Identifier 2 Register
PHY 0~7
0
0
4
5
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
PHY 0~7
PHY 0~7
0
6
Auto-Negotiation Expansion Register
PHY 0~7
0
7
Auto-Negotiation Next Page Transmit Register
PHY 0~7
0
8
Auto-Negotiation Link Partner Next Page Register
PHY 0~7
0
0
13
14
MMD Access Control Register
MMD Access Address Data Register
PHY 0~7
PHY 0~7
0
3.0
PCS control 1 register
PHY 0~7
0
3.1
PCS status 1 register
PHY 0~7
0
3.20
EEE capability
PHY 0~7
0
3.22
EEE wake error count
PHY 0~7
0
0
7.60
7.61
EEE advertisement register
EEE link partner ability
PHY 0~7
PHY 0~7
0
16
Special Control Register (APS)
SHARE
0
18
Special Status Register
PHY 0~7
X
20
Page Control Register
SHARE
3
16
LED Control Register
4
16
WOL+ Control Register
Share: 8 ports share the register
X8: Each port has its individual register
X: indicate do not care.
SHARE
SHARE
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IP178G-DS-R05
IP178Gx
Data Sheet
Register descriptions
R/W = Read/Write, SC = Self-Clearing, RO = Read Only, LL = Latching Low, LH = Latching High
6.1
PHY
MII Register
MII
R/W
Description
Default
Control Register
0.15
Reset
RW/ The PHY is reset if user writes “1” to this bit. The reset period is
SC around 2ms. User has to wait for at least 2ms to access IP178Gx.
（according design should delete）
0
0.14
Loop back
1 = Loop back mode
0 = normal operation
When this bit set, IP178Gx will be isolated from the network media,
that is, the assertion of TXEN at the MII will not transmit data on the
R/W network. All MII transmission data will be returned to MII receive
data path in response to the assertion of TXEN.
Bit 0.12 is cleared automatically, if this bit is set. User has to
program bit 0.12 again after loop back test. （according design
should delete）
0
0~7
0.13
Speed Selection
RW 1 = 100Mbps
0 = 10Mbps
It is valid only if bit 0.12 is set to be 0.
1
0~7
0.12
0~7
0.11
0~7
0.10
0~7
0.9
0~7
0~7
0~7
0.8
0~7
0.7
0~7
0[6:0]
RW
R/W
Auto-Negotiation(AN) Enable
1 = Auto-Negotiation Enable
0 = Auto-Negotiation Disable
1
Power Down
1: power down mode
0: normal operation
0
Isolate
IP178Gx doesn’t support this function.
RW Restart Auto-Negotiation
SC 1 = re-starting Auto-Negotiation
0: normal operation
0
0
Duplex mode
R/W 1 = full duplex
0 = half duplex
It is valid only if bit 0.12 is set to be 0.
R/W Collision test
0
RO Reserved
0
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IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
Description
Default
Status Register
0~7
1.15
100Base-T4 capable
1 = 100Base-T4 capable
RO
0 = not 100Base-T4 capable
IP178Gx does not support 100Base-T4. This bit is fixed to be 0.
0~7
1.14
100Base-X full duplex Capable
RO 1 = 100Base-X full duplex capable
0 = not 100Base-X full duplex capable
1
0~7
1.13
100Base-X half duplex Capable
RO 1 = 100Base-X half duplex capable
0 = not 100Base-X half duplex capable
1
0~7
1.12
0~7
1.11
0~7
1.10
0~7
1.9
100Base-T2 half duplex Capable
RO 1 = 100Base-T2 half duplex capable
0 = not 100Base-T2 half duplex capable
0
0~7
0~7
1.8
1.7
RO Extended Status
RO Reserved
0
0
0~7
1.6
0~7
1.5
0~7
1.4
0~7
1.3
10Base-T full duplex Capable
RO 1 = 10Base-T full duplex capable
0 = not 10Base-T full duplex capable
10Base-T half duplex Capable
RO 1 = 10Base-T half duplex capable
0 = not 10Base-T half duplex capable
100Base-T2 full duplex Capable
RO 1 = 100Base-T2 full duplex capable
0 = not 100Base-T2 full duplex capable
1
1
0
MF preamble Suppression
RO 1 = preamble may be suppressed
0 = preamble always required
Auto-Negotiation Complete
1 = Auto-Negotiation complete
0 = Auto-Negotiation in progress
When read as logic 1, indicates that the Auto-Negotiation process
RO has been completed, and the contents of register 4 and 5 are valid.
When read as logic 0, indicates that the Auto-Negotiation process
has not been completed, and the contents of register 4 and 5 are
meaningless. If Auto-Negotiation is disabled (bit 0.12 set to logic 0),
then this bit will always read as logic 0.
Remote fault
1 = remote fault detected
0 = not remote fault detected
RO
When read as logic 1, indicates that IP178Gx has detected a
LH
remote fault condition. This bit is set until remote fault condition
gone and before reading the contents of the register. This bit is
cleared after IP178Gx reset.
Auto-Negotiation Ability
1 = Auto-Negotiation capable
RO 0 = not Auto-Negotiation capable
When read as logic 1, indicates that IP178Gx has the ability to
perform Auto-Negotiation.
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IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
Description
Default
Status Register
1.2
Link Status
1 = Link Pass
0 = Link Fail
RO
When read as logic 1, indicates that IP178Gx has determined a
LL
valid link has been established. When read as logic 0, indicates the
link is not valid. This bit is cleared until a valid link has been
established and before reading the contents of this registers.
0
1.1
Jabber Detect
1 = jabber condition detected
0 = no jabber condition detected
When read as logic 1, indicates that IP178Gx has detected a jabber
RO
condition. This bit is always 0 for 100Mbps operation and is cleared
LH
after IP178Gx reset. When the duration of TXEN exceeds the
jabber timer (21ms), the transmission and loop back functions will
be disabled and the COL is active. After TXEN goes low for more
than 500 ms, the transmitter will be re-enabled.
0
0~7
1.0
Extended capability
1 = Extended register capabilities
RO
0 = No extended register capabilities
IP178Gx has extended register capabilities.
1
PHY
MII
R/W
0~7
0~7
Description
Default
PHY Identifier 1 Register
IP178Gx OUI (Organizationally Unique Identifier) ID, the MSB is 3rd
0~7
2
RO bit of IP178Gx OUI ID, and the LSB is 18th bit of IP178Gx OUI ID. 16’h0243
IP178Gx OUI is 0090C3.
PHY
MII
R/W
Description
Default
PHY Identifier 2 Register
PHY identifier
0~7 3[15:10] RO IP178Gx OUI ID, the MSB is 19th bit of IP178Gx OUI ID, and LSB is
24th bit of IP178Gx OUI ID.
0~7
3[9:4]
RO
Manufacture’s Model Number
IP178Gx model number
0~7
3[3:0]
RO
Revision Number
IP178Gx revision number
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IP178G-DS-R05
IP178Gx
Data Sheet
MII register 4 of PHY0~7 (Each PHY has its own MII register 4 with different PHY address)
PHY
MII
R/W
Description
Default
Auto-Negotiation Advertisement Register
1 = Next pages are supported
0 = Next pages are not supported
0~7
4.15
R/W
0~7
4.14
RO Reserved by IEEE, write as 0, ignore on read
0
0~7
4.13
Remote Fault
R/W 1 = Advertises that this port has detected a remote fault.
0 = There is no remote fault.
0
0~7
4.12
RO Reserved for future IEEE use, write as 0, ignore on read
0
0
Asymmetric PAUSE
0~7
4.11
RW 1 = Asymmetric flow control is supported
0 = Asymmetric flow control is not supported
PAUSE
RW 1 = Symmetric flow control is supported
0 = Symmetric flow control is not supported
1
0~7
4.10
0~7
4.9
RO 100BASE-T4 Not supported
0
0~7
4.8
100BASE-TX full duplex
R/W 1 = 100BASE-TX full duplex is supported
0 = 100BASE-TX full duplex is not supported
1
0~7
4.7
100BASE-TX
R/W 1 = 100BASE-TX is supported
0 = 100BASE-TX is not supported
1
0~7
4.6
10BASE-T full duplex
R/W 1 = 10BASE-T full duplex is supported
0 = 10BASE-T full duplex is not supported
1
0~7
4.5
10BASE-T
R/W 1 = 10BASE-T is supported
0 = 10BASE-T is not supported
1
0~7
4[4:0]
RO
Selector Field
Use to identify the type of message being sent by Auto-Negotiation.
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IP178G-DS-R05
IP178Gx
Data Sheet
MII register 5 of PHY0~7 (Each PHY has its own MII register 5 with different PHY address)
PHY
MII
R/W
Description
Default
Auto-Negotiation Link Partner Ability Register
Next Page
0~7
5.15
RO 1 = Next Page ability is supported by link partner
0 = Next Page ability does not supported by link partner
0~7
5.14
0~7
5.13
0~7
5.12
0
Acknowledge
RO 1 = Link partner has received the ability data word
0 = Not acknowledge
Remote Fault
1 = Link partner indicates a remote fault
RO
0 = No remote fault indicate by link partner
If this bit is set to logic 1, then bit 1.4 (Remote fault) will set to logic 1.
RO Reserved by IEEE for future use, write as 0, and read as 0.
0
0
0
Asymmetric PAUSE
1 = Link partner support Asymmetric PAUSE
RO 0 = Link partner does not support Asymmetric PAUSE
When local or link partner is Auto-negotiation disabled, this bit is read
as 1. The pause resolution is determined by MII Reg4.[11:10].
PAUSE
1 = Link partner support Symmetric PAUSE
RO 0 = Link partner does not support Symmetric PAUSE
When local or link partner is Auto-negotiation disabled, this bit is read
as 1. The pause resolution is determined by MII Reg4.[11:10].
0~7
5.11
0~7
5.10
0~7
5.9
100BASE-T4
RO 1 = Link partner support 100BASE-T4
0 = Link partner does not support 100BASE-T4
0
0~7
5.8
100BASE-TX full duplex
RO 1 = Link partner support 100BASE-TX full duplex
0 = Link partner does not support 100BASE-TX full duplex
0
0~7
5.7
100BASE-TX
RO 1 = Link partner support 100BASE-TX
0 = Link partner does not support 100BASE-TX
0
0~7
5.6
10BASE-T full duplex
RO 1 = Link partner support 10BASE-T full duplex
0 = Link partner does not support 10BASE-T full duplex
0
0~7
5.5
10BASE-T
1 = Link partner support 10BASE-T
RO
0 = Link partner does not support 10BASE-T
When AN is disabled, this bit is set if register 0.13=0
0
0~7
5[4:0]
RO
Selector Field
Protocol selector of the link partner
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
MII register 6 of PHY0~7 (Each PHY has its own MII register 6 with different PHY address)
PHY
MII
R/W
Description
Default
Auto-Negotiation Expansion Register
0~7 6[15:5] RO Reserved
0
0~7
6.4
Parallel Detection Fault
RO/
1 = a fault has been detected via parallel detection function.
LH
0 = a fault has not been detected via parallel detection function.
0
0~7
6.3
Link Partner Next Page Able
RO 1 = Link partner is next page able.
0 = Link partner is not next page able.
0
0~7
6.2
Next Page Able
RO 1 = IP178GX next page able.
0 = IP178GX is not next page able.
1
0~7
6.1
Page Recieved
RO/
1 = A new page has been received.
LH
0 = A new page has not been received.
0
6.0
If AN is enabled, this bit means:
1 = Link partner is Auto-Negotiation able.
RO
0 = Link partner is not Auto-Negotiation able.
In 100FX or AN disabled, then this bit is always equal to 0.
0~7
0
(AN)
(100FX)
MII register 7 of PHY0~7 (Each PHY has its own MII register 7 with different PHY address)
PHY
MII
R/W
Description
Default
Auto-Negotiation Next Page Transmit Register
Next Page
0~7
7.15
RW
Transmit Code Word Bit 15
0
0~7
7.14
RO
Reserved
Transmit Code Word Bit 14
0
0~7
7.13
RW
Message Page
Transmit Code Word Bit 13
1
0~7
7.12
RW
Acknowledge 2
Transmit Code Word Bit 12
0
0~7
7.11
RO
Toggle
Transmit Code Word Bit 11
0
0~7
7[10:0]
RW
Message/Unformatted Field
Transmit Code Word Bit 10:0
1
MII register 8 of PHY0~7 (Each PHY has its own MII register 8 with different PHY address)
PHY
MII
R/W
Description
Auto-Negotiation Link Partner Next Page Register
Next Page
0~7
8.15
RO
Received Code Word Bit 15
0~7
8.14
RO
Acknowledge
Received Code Word Bit 14
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
MII register 8 of PHY0~7 (Each PHY has its own MII register 8 with different PHY address)
PHY
MII
R/W
0~7
8.13
RO
Message Page
Received Code Word Bit 13
0
0~7
8.12
RO
Acknowledge 2
Received Code Word Bit 12
0
0~7
8.11
RO
0~7
8[10:0]
PHY
MII
Description
Default
Toggle
Received Code Word Bit 11
Message/Unformatted Field
RO
Received Code Word Bit 10:0
R/W
0
0
Description
Default
Special Control Register
Advance power saving mode
1 = Enable APS mode (Default)
0 = Disable APS mode
0~7
16.7
RW
1
Please refer to the Power Saving application note for more detail
description.
0~7
16.4
Far end fault function
1 = Far end fault function disable
RW
0 = Far end fault function enable (Default)
This bit is only used for fiber mode.
PHY
MII
R/W
0
Description
Default
Special Status Register
Linkup
0~7 18.14
RO 1 = linkup
0 = unlink
Speed Mode
0~7
18.11
RO 1 = 100 Mbps
0 = 10 Mbps
0
0
Duplex Mode
RO 1 = Full Duplex
0 = Half Duplex
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.
0~7
18.10
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IP178G-DS-R05
IP178Gx
Data Sheet
6.2
MMD Control Register
Table 10 MMD Control Register table
MII register 13 of PHY0~7 (Each PHY has its own MII register 13 with different PHY address)
PHY
MII
R/W
Description
Default
MMD Access Control Register
Function
00 = address
0~7 13[15:14] R/W 01 = data, no post increment
10 = data, post increment on reads and writes
11 = data, post increment on writes only
0
0~7
13[13:5]
RO
Reserved
Write as 0, ignore on read
0
0~7
13[4:0]
R/W
DEVAD
Device Address
0
MII register 14 of PHY0~7 (Each PHY has its own MII register 14 with different PHY address)
PHY
MII
R/W
Description
Default
MMD Access Address Data Register
Address Data
If 13.15:14 = 00, MMD DEVAD’s address register.
0~7 14[15:0] R/W
Otherwise, MMD DEVAD’s data register as indicated by the
contents of its address register
0
Example 1, Read 0.3.20 (Read Data from MMD register 3.20 of PHY address 0):
1.
Write 0.13 = 0x0003 //MMD DEVAD 3
2.
Write 0.14 = 0x0014 //MMD Address 20
3.
Write 0.13 = 0x4003 //MMD Data command for MMD DEVAD 3
4.
Read 0.14
//Read MMD Data from 0.3.20
Example 2, Write 1.7.60 = 0x3210 (Write 0x3210 Data to MMD register 7.60 of PHY address 1):
1.
Write 1.13 = 0x0007 //MMD DEVAD 7
2.
Write 1.14 = 0x003C //MMD Address 60
3.
Write 1.13 = 0x4007 //MMD Data command for MMD DEVAD 7
4.
Write 1.14 = 0x3210 //Write MMD Data 0x3210 to 1.7.60
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
6.3
MMD Data Register
Table 11 MMD Data Register table
MMD register 3.0 of PHY0~7 (Each PHY has its own MMD register 3.0 with different PHY address)
PHY
MII
R/W
Description
Default
PCS control 1 Register
0~7
3.0[15:11]
RO
0~7
3.0.10
R/W
Reserved
Ignore when read
Clock stop enable
1 = PHY may stop xMII Rx clock during LPI（IP178Gx doesn’t
support）
0
0
0 = Clock not stoppable
0~7
3.0[9:0]
RO
Reserved
Ignore when read
0
MMD register 3.1 of PHY0~7 (Each PHY has its own MMD register 3.1 with different PHY address)
PHY
MII
R/W
Description
Default
PCS status 1 Register
RO
Reserved
Ignore when read
0~7
3.1[15:12]
0~7
3.1.11
Tx LPI received
RO/LH 1 = Tx PCS has received LPI
0 = LPI not received
0
0~7
3.1.10
Rx LPI received
RO/LH 1 = Rx PCS has received LPI
0 = LPI not received
0
0~7
3.1.9
RO
0~7
3.1.8
RO
0~7
3.1.7
RO
0~7
3.1.6
RO
Clock stop capable
1 = The MAC may stop the xMII Tx clock during LPI
0 = Clock not stoppable
0
0~7
3.1[5:0]
RO
Reserved
Ignore when read
0
0
Tx LPI indication
1 = Tx PCS is currently receiving LPI
0 = PCS is not currently receiving LPI
Rx LPI indication
1 = Rx PCS is currently receiving LPI
0 = PCS is not currently receiving LPI
Reserved
Ignore on read
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0
0
0
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IP178G-DS-R05
IP178Gx
Data Sheet
MMD register 3.20 of PHY0~7 (Each PHY has its own MMD register 3.20 with different PHY address)
PHY
MII
R/W
Description
Default
EEE capability Register
0~7
3.20[15:7] RO
Reserved
Ignore when read
0
10GBASE-KR EEE
RO 1 = EEE is supported for 10GBASE-KR
0 = EEE is not supported for 10GBASE-KR
0
0~7
3.20.6
0~7
3.20.5
0~7
3.20.4
0~7
3.20.3
10GBASE-T EEE
RO 1 = EEE is supported for 10GBASE-T
0 = EEE is not supported for 10GBASE-T
0
0~7
3.20.2
1000BASE-T EEE
RO 1 = EEE is supported for 1000BASE-T
0 = EEE is not supported for 1000BASE-T
0
0~7
3.20.1
100BASE-TX EEE
RO 1 = EEE is supported for 100BASE-TX
0 = EEE is not supported for 100BASE-TX
1
0~7
3.20.0
RO
10GBASE-KX4 EEE
RO 1 = EEE is supported for 10GBASE-KX4
0 = EEE is not supported for 10GBASE-KX4
1000BASE-KX EEE
RO 1 = EEE is supported for 1000BASE-KX
0 = EEE is not supported for 1000BASE-KX
Reserved
Ignore when read
0
0
0
MMD register 3.22 of PHY0~7 (Each PHY has its own MMD register 3.22 with different PHY address)
PHY
MII
R/W
EEE wake error count
0~7
Description
Default
EEE wake error count
Count wake time faults where IP178Gx fails to complete its normal wake
3.22[15:0] RO
0x0000
sequence within the time required for the specific PHY type.
This register keeps the value before reading the contents of the register.
MMD register 7.60 of PHY0~7 (Each PHY has its own MMD register 7.60 with different PHY address)
PHY
MII
R/W
Description
EEE advertisement Register
Reserved
0~7 7.60[15:7] RO
Ignore when read
10GBASE-KR EEE
0~7
7.60.6
RO 1 = Advertise that the 10GBASE-KR has EEE capability
0 = Do not advertise that the 10GBASE-KR has EEE capability
10GBASE-KX4 EEE
0~7
7.60.5
RO 1 = Advertise that the 10GBASE-KX4 has EEE capability
0 = Do not advertise that the 10GBASE-KX4 has EEE capability
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Default
0
0
0
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
MMD register 7.60 of PHY0~7 (Each PHY has its own MMD register 7.60 with different PHY address)
PHY
MII
R/W
Description
0~7
7.60.4
0~7
7.60.3
0~7
7.60.2
0~7
7.60.1
100BASE-TX EEE
R/W 1 = Advertise that the 100BASE-TX has EEE capability
0 = Do not advertise that the 100BASE-TX has EEE capability
0~7
7.60.0
RO
Default
1000BASE-KX EEE
RO 1 = Advertise that the 1000BASE-KX has EEE capability
0 = Do not advertise that the 1000BASE-KX has EEE capability
10GBASE-T EEE
RO 1 = Advertise that the 10GBASE-T has EEE capability
0 = Do not advertise that the 10GBASE-T has EEE capability
1000BASE-T EEE
RO 1 = Advertise that the 1000BASE-T has EEE capability
0 = Do not advertise that the 1000BASE-T has EEE capability
0
0
0
1
Reserved
Ignore when read
0
MMD register 7.61 of PHY0~7 (Each PHY has its own MMD register 7.61 with different PHY address)
PHY
MII
R/W
EEE link partner ability
0~7
7.61[15:7]
RO
0~7
7.61.6
RO
0~7
7.61.5
RO
0~7
7.61.4
RO
0~7
7.61.3
RO
0~7
7.61.2
RO
0~7
7.61.1
RO
0~7
7.61.0
RO
Description
Default
Reserved
Ignore when read
10GBASE-KR EEE
1 = Link partner is advertising EEE capability for 10GBASE-KR
0 = Link partner is not advertising EEE capability for 10GBASE-KR
10GBASE-KX4 EEE
1 = Link partner is advertising EEE capability for 10GBASE-KX4
0 = Link partner is not advertising EEE capability for 10GBASE-KX4
1000BASE-KX EEE
1 = Link partner is advertising EEE capability for 1000BASE-KX
0 = Link partner is not advertising EEE capability for 1000BASE-KX
10GBASE-T EEE
1 = Link partner is advertising EEE capability for 10GBASE-T
0 = Link partner is not advertising EEE capability for 10GBASE-T
1000BASE-T EEE
1 = Link partner is advertising EEE capability for 1000BASE-T
0 = Link partner is not advertising EEE capability for 1000BASE-T
100BASE-TX EEE
1 = Link partner is advertising EEE capability for 100BASE-TX
0 = Link partner is not advertising EEE capability for 100BASE-TX
Reserved
Ignore when read
0
0
0
0
0
0
0
0
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.
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IP178G-DS-R05
IP178Gx
Data Sheet
6.4
LED mode Control Register
Table 12 LED mode Control Register table
MII page3 register16 of PHY0~7 (8 PHYs share the MII register)
page
MII
R/W
Description
Default
LED Control Register
3
LED_SEL[1:0]
LED output mode selection.
LED_SEL[1:0]=2’b00: LED mode 0,
16[15:14] R/W
LED_SEL[1:0]=2’b01: LED mode 1,
LED_SEL[1:0]=2’b10: LED mode 2,
LED_SEL[1:0]=2’b11: LED mode 3 (default)
SERIAL_LED_EN
16.12
RW 1: supports LED serial mode
0: supports LED direct mode (default)
16.11
11
0
SERIAL_LED_MODE
RW 1: supports link LED only
0: supports link, speed, and duplex LED (default)
0
Serial upd fast
RW 1:10ms(default)
0:20ms
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.
16.10
1
LED mode behavior:
LED_SEL[1:0]
LED_LINK[7:0]
LED mode 0
00
100M Link + Activity
(1: 100M Link fail,
Link
0: 100M Link ok and
(1: link fail,
no activity,
0: link ok)
flash: 100M Link ok
and TX/RX activity)
Collision
LED_SPEED[7:0] (1: no collision,
flash: collision)
LED_FULL[7:0]
LED mode 1
01
Speed
(same as mode 3)
10M Link + Activity
(1: 10M Link fail,
0: 10M Link ok and Full/half
(same as mode 3)
no activity,
flash: 10M Link ok
and TX/RX activity)
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LED mode 2
10
LED mode 3
11
100M Link + Activity
(same as mode 0)
Link + Activity
(1: link fail,
0: link ok,
flash: Link ok and
TX/ RX activity)
Full/half
(1: half,
0: full,
flash: collision)
Speed
(1: speed=10M,
0: speed=100M
10M Link + Activity
(same as mode 0)
Full/half
(1: half,
0: full,
flash: collision)
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
6.5
WOL+ Control Register
Table 13 WOL+ Control Register table
MII page4 register16 of PHY0 (8 PHYs share the MII register)
page
MII
R/W
Description
Default
PHY WOL+ Control Register
WOL+ Interrupt Enable
0
Set high to enable WOL+ interrupt
16.[15] RW 1=Enable
0=Disable
Each PHY address can access the register of the corresponding port.
WOL+ Level Trigger
1
This
bit
is
used
to
select
the
output
mode
of
WOL+
interrupt.
16.[14] RW 1=Level trigger (Low goes high or high goes low when WOL+ interrupt)
16.[13]
4
RW
16.[12]
RW
16.[11]
RW
16.[10]
RW
16.[9]
RW
16.[8]
RW
16.[7:1]
RO
16.[0]
RO
0=Edge trigger (Positive pulse or negative pulse when WOL+ interrupt)
WOL+ Positive Trigger
This bit is used to select the polarity of WOL+ interrupt.
1=Low goes high or positive pulse
0=High goes low or negative pulse
Sense Link Change
Set high to enable WOL+ interrupt when link change is sensing.
1=Enable
0=Disable
Sense Magic Packet
Set high to enable WOL+ interrupt when magic packet is receiving.
1=Enable
0=Disable
Sense Any Packet
Set high to enable WOL+ interrupt when any packet is receiving.
1=Enable
0=Disable
Sense DUT
Set high to enable WOL+ interrupt when DUT is sensing WOL+ event.
1=Enable
0=Disable
Each PHY address can access the register of the corresponding port.
WOL+ Down Speed Enable
Set high to enable WOL+ down speed function
1=Enable
0=Disable
Reserved
PHY WOL+ Interrupt Status
The status of PHY WOL+ interrupt is based on the setting of Reg16
Page4 Bit14 and Bit13.
Each PHY address can access the register of the corresponding port.
0
1
1
1
1
1
0x00
1
MII page5 register16 of PHY0 (8 PHYs share the MII register)
page
MII
R/W
Description
PHY WOL+ MAC Address Register 0
WOL+ MAC Address 0 (the most significant word)
5
16[15:0] R/W WOL+ MAC Address = {WOL+_MAC_Address_0,
WOL+_MAC_Address_1, WOL+_MAC_Address_2}
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Default
0x0000
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
MII page6 register16 of PHY0 (8 PHYs share the MII register)
page
MII
R/W
Description
PHY WOL+ MAC Address Register 1
WOL+ MAC Address 1
6
16[15:0] R/W WOL+ MAC Address = {WOL+_MAC_Address_0,
WOL+_MAC_Address_1, WOL+_MAC_Address_2}
Default
0x0000
MII page7 register16 of PHY0 (8 PHYs share the MII register)
page
MII
R/W
Description
Default
PHY WOL+ MAC Address Register 2
WOL+ MAC Address 2 (the least significant word)
7
16[15:0] R/W WOL+ MAC Address = {WOL+_MAC_Address_0,
0x0000
WOL+_MAC_Address_1, WOL+_MAC_Address_2}
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.
Example 1, Read page3 register16 (Read Data from page3 register16 of PHY address 0):
1.
Write 0.20 = 0x0003 //page3
2.
Read 0.16
//Read Data from page3 register16
3.
Write 0.20 = 0x0000 //restore to page0
Example 2, Write page3 register16 = 0x3400 (Write Data 0x3400 to page3 register16 of PHY address 0):
1.
Write 0.20 = 0x0003 //page3
2.
Write 0.16 = 0x3400 //Write Data 0x3400 to page3 register16
3.
Write 0.20 = 0x0000 //restore to page0
6.6
Register Page mode Control Register
Table 14 Page control registers table
MII register 20 of PHY0~7 (8 PHYs share the MII register)
PHY
MII
R/W
Description
Default
Page Control Register
0~7
20[4:0] RW Reg16~31_Page_Sel[4:0]
00000
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.
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IP178G-DS-R05
IP178Gx
Data Sheet
6.7
Switch control registers (I)
Table 15 Switch control registers (I) table
PHY
MII
R/W
Description
Default
EEPROM enable register / Software reset register
EEPROM enable register
This register should be filled with 55AA in EERPOM register 0 and 1.
20
-IP178Gx will examine the specified pattern to confirm if there is a valid
EEPROM. The initial setting is updated with the content of EEPROM
only if the specified pattern 55 AA is found.
20
0
R/W
20
0[15]
R
Empty, all output queue is empty
1: empty
0: not empty
This bit is for debug only.
20
0[13]
20
0[12:4]
20
0[3]
R
PAD_RESET
20
20
0[2]
0[1]
R
R
EE_RESET1
SOFT_RESET
20
0[0]
R
20
1[15]
R
Software reset register
MII register 0 is software reset register. User can reset IP178Gx by
writing 55AA to this register.
BFLL_FULL, free buffer is full
1: full,
0: not full
This bit is for debug only.
Reserved
R/W
EE_RESET
PRIORITY_RATE
1: 8 packets
0: 16 packets
1’b0
Output Queue Scheduling: high priority packet rate
REDUCE_IPG
This function reduce the IPG by random from 0 ~ 20 PPM.
1: enable, 0:disable
20
1[12]
R/W
1'b1
20
1[11]
R/W
Drop16
1: enable, 0:disable
1’b0
20
1[9]
R/W
MOD_CARRIER_ALGORITHM
Modified carrier based collision algorithm
1: enable, 0:disable
1’b0
20
1[8]
R/W
BK_EN, Backpressure enable
1: enable, 0: disable
1’b1
BP_KIND, Backpressure type selection
It is valid only if BK_EN is set to 1’b1.
20
1[7]
1’b0
R/W
0: carrier base backpressure
1: reserved
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IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
20
1[6]
R/W
20
1[3:2]
R/W
Description
Default
BF_STM_EN, Broadcast storm enable
1: enable
P(0)
IP178Gx drops the incoming packet if the number of broadcast packet
in queue is over the threshold.
0: disable
AGING. Aging time of address table selection
An address tag in hashing table will be removed if this function is
turned on and its aging timer expires.
00
Aging time
no aging
01
30s
10
300s
11
reserved
note
2’b10
default
20
1[1]
R/W
MODBCK. Turn on modified back off algorithm
The maximum back off period is limited to 8-slot time if this function is
turned on.
1: turn on, 0: turn off
20
1[0]
R/W
LEARN_DIS_PAUSE
0: Enable to learn the SMAC of the received PAUSE frame.
1: Disable.
6.8
1’b0
1’b0
Test mode control registers
Table 16 Test mode control registers table
PHY
MII
R/W
Description
Default
Test mode control registers
TMODE_SEL. Test mode selection
20 2[15:10] R/W This function is for testing only. The default value must be adopted for
normal operation.
20
20
2[8]
Reserved
2[7]
R/W
INPUT_FILTER
Packet is filtered in input port.
0: no operation (default)
1: perform input filtering when queue full
R/W
HASH_MODE
MAC address table hashing mode
00: direct + CRC mapping (default)
11: direct mapping
20
2[6:5]
20
2[4:1]
6’h00
0
2’b00
Reserved
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IP178G-DS-R05
IP178Gx
Data Sheet
6.9
PHY
Port mirroring control registers
MII
R/W
3[15]
R/W
3[14:13]
R/W
3[12:8]
3[7:0]
R/W
20
Description
Default
PORT_MIRROR_EN
Port Mirror Enable
1: Enable
0: Disable
PORT_MIRROR_MODE
Select a mirror mode to monitor
00: mirror RX (default)
01: mirror TX
10: mirror RX and TX, RX and TX path must be at the different port
11: mirror RX or TX, RX or TX path must be at the same port
Reserved
SEL_RX_PORT_MIRROR
Select the source (receive) port to be mirrored
Set 1 to select the RX path of port to be monitored. Bit0 is for Port0,
bit7 for Port7, and so on.
R/W
SEL_MIRROR_PORT
Select a mirror port to monitor any other port
000: port 0
001: port 1
010: port 2
011: port 3
100: port 4
101: port 5
110: port 6
111: port 7 (default)
4[12:8]
Reserved
4[7:0]
R/W
SEL_TX_PORT_MIRROR
Select the destination (transmit) port to be mirrored
Set 1 to select the TX path of port to be monitored. Bit0 is for Port0,
bit7 for Port7, and so on.
4[15:13]
1’b0
2’b00
8’h01
3’b111
8’h01
6.10 Debug Regiister
PHY
20
MII
5[15:8]
R/W
R/W
5[7:0]
RO
(SC)
CRC_COUNTER
6[15:8]
R/W
(SC)
PAUSE_TRIGGER
6[7:0]
RO
(SC)
PAUSE_FLAG
7[15]
R/W
THR_SETTING
R/W
(SC)
R/W
READ_THR
7[14]
7[13]
7[12:8]
7[7:0]
Description
RESERVED
Default
16’h0
8’h00
8’h00
8’h0
1’b0
1’b0
WAIT_BACKOFF
1’b0
RESERVED
R/W
UNIT_DEFAULT_THRESHOLD
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8’d12
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
8[15:8]
R/W
R/W
Description
SHARE_HIGH_THRESHOLD
Default
8[7:0]
R/W
SHARE_LOW_THRESHOLD
9[15:8]
R/W
PKT_HIGH_THRESHOLD
8’d96
9[7:0]
R/W
PKT_LOW_THRESHOLD
8’d80
10[15:8]
R/W
UNIT_HIGH_THRESHOLD
10[7:0]
R/W
UNIT_LOW_THRESHOLD
11[15]
R/W
MON_EN
11[14:9]
11[8:0]
RESERVED
RO
(SC)
12[15:9]
12[8:0]
1’b0
UNIT_LOW_NUM
9’d224
RESERVED
RO
(SC)
SHARE_HIGH_NUM
9’d224
6.11 Fiber duplex setting registers
PHY
20
MII
R/W
Description
FIBER_DUPLEX
Fiber duplex setting for each port.
1: fiber port is full-duplex
13[15:14] R/W
0: fiber port is half_duplex
bit[15]: port 7 duplex ability setting
bit[14]: port 6 duplex ability setting
Default
2’b11
13.[13]
R/W BUF_AGING_EN
1’b0
13.[12]
R/W SRC_BLK_PROTECT
1’b1
13[11:8]
Reserved
6.12 Backpressure setting registers
PHY
20
MII
13[7:0]
R/W
Description
Default
PORT_BACKPRESSURE_EN
Backpressure ability setting at half-duplex mode for each port. To
ensure this function works correctly, BK_EN (backpressure enable, reg
20.1[8]) should set to logic zero first.
1: enable backpressure ability
0: disable
bit[7] : port 7 enable backpressure ability
8’h00
R/W
bit[6] : port 6 enable backpressure ability
bit[5] : port 5 enable backpressure ability
bit[4] : port 4 enable backpressure ability
bit[3] : port 3 enable backpressure ability
bit[2] : port 2 enable backpressure ability
bit[1] : port 1 enable backpressure ability
bit[0] : port 0 enable backpressure ability
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March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
6.13 TCP/UDP port priority registers
PHY
MII
20
14[15:8]
20
14[7:6]
20
14[5:4]
R/W
Description
Default
LPP_AGING_EN
TCP/UDP logical port priority aging enable
0: disable TCP/UDP logical port priority aging function
1: enable TCP/UDP logical port priority aging function
When this function active, once receive a IP frame with TCP/UDP
protocol and the logical port number is the pre-defined port number, the
ingress port will treat as a port based high priority port for 300 seconds.
After the internal timer expired, the ingress port will change back to
8’h00
R/W previous behavior.
bit[15]:
port 7 logical port priority aging enable
bit[14]:
port 6 logical port priority aging enable
bit[13]:
port 5 logical port priority aging enable
bit[12]:
port 4 logical port priority aging enable
bit[11]:
port 3 logical port priority aging enable
bit[10]:
port 2 logical port priority aging enable
bit[9]:
port 1 logical port priority aging enable
bit[8]:
port 0 logical port priority aging enable
Reserved
USERDEF_RANGE_EN
User defined logic port range enable.
R/W
bit[1]:
user define range 1 register enable
bit[0]:
user define range 0 register enable
PREDEF_PORT_EN
Pre-defined logic port number enable.
bit[3]:
logic port set 3 enable, port 6000
R/W
bit[2]:
logic port set 2 enable, port 3389
bit[1]:
logic port set 1 enable, port 443
bit[0]:
logic port set 0 enable, port 22
2’b11
20
14[3:0]
4’hF
20
15
R/W
USERDEF_RANGE0_HIGH
User defined logic port range 0 high limit
16’d23
20
16
R/W
USERDEF_RANGE0_LOW
User defined logic port range 0 low limit
16’d23
20
17
R/W
USERDEF_RANGE1_HIGH
User defined logic port range 1 high limit
16’d
5800
20
18
R/W
USERDEF_RANGE1_LOW
User defined logic port range 1 low limit
16’d
5800
6.14 Test mode
PHY
MII
20
19[15]
20
19[11:2]
20
19[1:0]
R/W
Description
R/W FAST_MODE
1’b0
R/W TEST_LATIN (only for PHY test mode)
TEST_SEL
0x0: normal mode
R/W
0x1: switch test mode
0x2: phy test mode
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Default
10’h000
2’b00
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
6.15 CoS control registers – port 0
PHY
MII
R/W
0[10]
R/W
0[9]
R/W
21
Description
Default
Port 0 Class of service enable
1: enable, 0: disabled (default)
1’b0
Packets with high priority tag from port 0 are handled as high priority
packets.
Port 0 set to be high priority port
1: enable, 0: disabled (default)
Packets received from port 0 are handled as high priority packets.
1’b0
6.16 CoS control registers – port 1
PHY
MII
R/W
Description
Default
1[10]
R/W
Port 1 Class of service enable
1: enable, 0: disabled (default)
Packets with high priority tag from port 1 are handled as high priority
packets.
1’b0
1[9]
R/W
Port 1 set to be high priority port
1: enable, 0: disabled (default)
Packets received from port 1 are handled as high priority packets.
1’b0
21
6.17 CoS control registers – port 2
PHY
MII
R/W
2[10]
R/W
21
2[9]
R/W
Description
Default
Port 2 Class of service enable
1: enable, 0: disabled (default)
1’b0
Packets with high priority tag from port 2 are handled as high priority
packets.
Port 2 set to be high priority port
1: enable, 0: disabled (default)
Packets received from port 2 are handled as high priority packets.
1’b0
6.18 CoS control registers – port 3
PHY
MII
R/W
3[10]
R/W
21
3[9]
R/W
Description
Default
Port 3 Class of service enable
1: enable, 0: disabled (default)
1’b0
Packets with high priority tag from port 3 are handled as high priority
packets.
Port 3 set to be high priority port
1: enable, 0: disabled (default)
Packets received from port 3 are handled as high priority packets.
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1’b0
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
6.19 CoS control registers – port 4
PHY
MII
R/W
4[10]
R/W
4[9]
R/W
21
Description
Default
Port 4 Class of service enable
1: enable, 0: disabled (default)
1’b0
Packets with high priority tag from port 4 are handled as high priority
packets.
Port 4 set to be high priority port
1: enable, 0: disabled (default)
Packets received from port 4 are handled as high priority packets.
1’b0
6.20 CoS control registers – port 5
PHY
MII
5[10]
R/W
Description
Default
R/W
Port 5 Class of service enable
1: enable, 0: disabled (default)
Packets with high priority tag from port 5 are handled as high priority
packets.
1’b0
R/W
Port 5 set to be high priority port
1: enable, 0: disabled (default)
Packets received from port 5 are handled as high priority packets.
1’b0
21
5[9]
6.21 CoS control registers – port 6
PHY
MII
R/W
6[10]
R/W
21
6[9]
R/W
Description
Default
Port 6 Class of service enable
1: enable, 0: disabled (default)
1’b0
Packets with high priority tag from port 6 are handled as high priority
packets.
Port 6 set to be high priority port
1: enable, 0: disabled (default)
Packets received from port 6 are handled as high priority packets.
1’b0
6.22 CoS control registers – port 7
PHY
MII
R/W
7[10]
R/W
21
7[9]
R/W
Description
Default
Port 7 Class of service enable
1: enable, 0: disabled (default)
1’b0
Packets with high priority tag from port 7 are handled as high priority
packets.
Port 7 set to be high priority port
1: enable, 0: disabled (default)
Packets received from port 7 are handled as high priority packets.
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1’b0
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
6.23 Switch control registers (IV)
PHY
21
MII
R/W
9[15:14]
R/W
9[13:12]
R/W
9[11:10]
R/W
9[9:8]
R/W
9[7:6]
9[3:2]
9[1:0]
Default
UNIT_DEFAULT_THR_SEL[1:0].
Output Queue minimum threshold selection
00: 40 units
01: 32 units
10: 48 units
11: 56 units
2’b00
2’b00
2’b00
R/W
UNIT_LOW_THR_SEL
UNIT_HIGH_THR_SEL[1;0].
Output Queue Flow control ON threshold selection
If share buffer is over share buffer full threshold, Output Queue Flow
control ON threshold will be dynamic changed to 28.
Others,
00: 50 units
01: 70 units
10: 90 units
11: 110 units
Reserved
2’b00
R/W
PREDROP_EN
1: Drop an incoming broadcast packet if any port is congested.
0: forward an incoming broadcast packet to un-congested ports instead
of congested ports.
1’b0
R/W
PKT_LOW_THR_SEL[1:0].
Packet low water mark threshold selection
00: 40 units
01: 30 units
10: 20 units
11: 10 units
2’b00
R/W
PKT_HIGH_THR_SEL[1:0].
Packet high water mark threshold selection
00: 50 units
01: 40 units
10: 30 units
11: 20 units
2’b00
9[5]
9[4]
Description
BF_STM_THR_SEL[1:0].
Broadcast storm threshold selection
00: 2 packets/10ms for 100Mbps port, or 2 packets/100ms for 10Mbps
port,
01: 6 packets/10ms for 100Mbps port, or 6 packets/100ms for 10Mbps
port,
10: 14 packets/10ms for 100Mbps port, or 14 packets/100ms for
10Mbps port,
11: 30 packets/10ms for 100Mbps port, or 30 packets/100ms for
10Mbps port
SHARE_FULL_THR_SEL[1;0].
Share buffer threshold selection
00: 160 units
01: 180 units
10: 140 units
11: 120 units
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2’b00
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
10[15]
R/W
Description
Default
RESERVED
10[14:12] R/W
DRIVER[2:0]
Pad Drive Current
000: 0 mA
001: 1.5 mA
010: 4.6 mA (default)
011: 9.9 mA
100: 9.9 mA
101: 9.9 mA
110: 15.1 mA
111: 18.4 mA
3’b
010
10[11]
R/W
10[10]
R/W
10[9]
R/W
TWOPART
1’b1
R/W
ALLPASS
All packet forwarded include CRC packet.
1’b0
10[8]
BF_STM_EN_QM
HP_DIS_FLOW_EN
Disable flow control when recived high priority packet
1’b0
1’b0
ANALOG_OFF_TIME
The length of time of the push button input must be held low in order to
turn off analog power
10[7:6]
R/W
10[5]
2’b01
0x0: 1.5 sec
0x1: 3 sec (default)
0x2: 4.5 sec
0x3: reserved
RESERVED
6.24 Reserved Group MAC addresses
PHY
MII
R/W
Description
Default
PAUSE_FILTER
21
11[15]
R/W
DA=01-80-c2-00-00-01 & EtherType=0x8808 & Opcode=1
1’b0
1: forward,
0: discard (default).
RSVD_GMAC_FILTER_4
11[14]
R/W
Reserved Group Address
01-80-c2-00-00-40 to FF
1’b1
1: forward (default),
0: discard.
RSVD_GMAC_FILTER_3
11[13]
R/W
Reserved Group Address
01-80-c2-00-00-30 to 3F
1’b1
1: forward (default),
0: discard.
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IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
Description
Default
RSVD_GMAC_FILTER_2
11[12]
R/W
Reserved Group Address
01-80-c2-00-00-22 to 2F
1’b0
1: forward,
0: discard (default).
RSVD_GMAC_FILTER_2
11[11]
R/W
GVRP
GARP VLAN Registration Protocol
01-80-c2-00-00-21
1’b0
1: forward,
0: discard (default).
RSVD_GMAC_FILTER_2
11[10]
R/W
GMRP
GARP Multicast Registration Protocol
01-80-c2-00-00-20
1’b0
1: forward,
0: discard (default).
RSVD_GMAC_FILTER_1
11[9]
R/W
Reserved Group Address
01-80-c2-00-00-10 to 1F
1’b1
1: forward (default),
0: discard.
RSVD_GMAC_FILTER_1
11[8]
R/W
ABM
All LANs Bridge Management Group address
1’b0
1: forward,
0: discard (default).
RSVD_GMAC_FILTER_0
11[7]
R/W
Reserved Group Address
01-80-c2-00-00-04 to 0F
1’b0
1: forward,
0: discard (default).
RSVD_GMAC_FILTER_0
11[6]
R/W
LLDP
Std 802.1AB Link Layer Discovery Protocol address
01-80-C2-00-00-0E
1’b1
1: forward (default),
0: discard.
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IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
Description
Default
RSVD_GMAC_FILTER_0
11[5]
R/W
MVRP
Provider Bridge MVRP Address
01-80-C2-00-00-0D
1’b0
1: forward,
0: discard (default).
RSVD_GMAC_FILTER_0
11[4]
R/W
PBGA
Provider Bridge Group Address
01-80-C2-00-00-08
1’b0
1: forward,
0: discard (default).
RSVD_GMAC_FILTER_0
11[3]
R/W
802.1x
802.1x PAE Address
01-80-C2-00-00-03
1’b1
1: forward (default),
0: discard.
RSVD_GMAC_FILTER_0
11[2]
R/W
SP
Slow Protocol (Link Aggregation and 802.3 OAM)
01-80-C2-00-00-02
1’b1
1: forward (default),
0: discard.
RSVD_GMAC_FILTER_0
11[1]
R/W
MAC_CTRL
MAC Control of Std IEEE 802.3
01-80-C2-00-00-01
(Not include PAUSE and 802.3ah)
1’b0
1: forward,
0: discard (default).
RSVD_GMAC_FILTER_0
11[0]
R/W
BGA
Bridge Group Address
01-80-C2-00-00-00
1’b1
1: forward (default),
0: discard.
12[15:11] R/W
RESERVED
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IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
Description
Default
RSVD_FUTURE_0_FILTER
Reserved for Future Standardization 0
12[10:2]
9’h
000
01-80-c2-00-00-04 to 0F
1: forward.
0: discard (default),.
RSVD_MAC_CTRL_FILTER
Reserved MAC Control Opcode
12[1]
R/W
DA=01-80-c2-00-00-01 & EtherType=0x8808 & Opcode=0x0007-0xffff
1’b0
1: forward,
0: discard (default).
MPCP_FILTER
Multi-Poin Control Protocol
12[0]
R/W
Five message as follows:
1. GATE
DA=01-80-c2-00-00-01 & EtherType=0x8808 & Opcode=2
2. REPORT
DA=01-80-c2-00-00-01 & EtherType=0x8808 & Opcode=3
3. REGISTER_REQ
DA=01-80-c2-00-00-01 & EtherType=0x8808 & Opcode=4
4. REGISTER
DA=individual MAC EtherType=0x8808 & Opcode=5
5. REGISTER_ACK
DA=01-80-c2-00-00-01 & EtherType=0x8808 & Opcode=6
1’b0
1: forward,
0: discard (default).
RSVD_FUTURE_1_FILTER
Reserved for Future Standardization 1
13[13:0]
R/W
14’h
0000
01-80-c2-00-00-22 to 2F
1: forward,
0: discard (default).
IEEE802.1ag_FILTER
IEEE 802.1ag Filter
14
R/W
16’h
FFFF
01-80-c2-00-00-30 to 3F
1: forward (default),
0: discard.
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IP178Gx
Data Sheet
6.25 Switch control registers (V)
PHY
MII
30[15:8]
R/W
R/W
Description
Default
[15:14]: Reserved
[13]: DIFFSERV_EN
[12]: BF_FFFF_ONLY
1: broadcast DA=FFFFFFFF
0: broadcast DA=FFFFFFFF and multicast frame
8’h0d
[11:8]: reserved
21
30[7]
R/W
30[6:2]
FWD_MAC_CTL
Forward MAC control frame, the MAC control frame is identified by
Ether/Type field (0x8808).
1: forward (default),
0: discard.
1’b1
Reserved
Drop extra long packet
Max forwarded packet length
30[1:0]
R/W
2’b00
2’b00: 1536 bytes (default)
2’b01: 1552 bytes
2’b10: 1518 bytes
2’b11: resreved
6.26 EEE Timing Parameter
PHY
MII
22
0[15:8]
0[7:0]
R/W
Description
Reserved
EEE_EN[7:0]
Energy Efficient Ethernet Enable for each port
bit[7]: Port 7 enable EEE function
bit[6]: Port 6 enable EEE function
bit[5]: Port 5 enable EEE function
R/W
bit[4]: Port 4 enable EEE function
bit[3]: Port 3 enable EEE function
bit[2]: Port 2 enable EEE function
bit[1]: Port 1 enable EEE function
bit[0]: Port 0 enable EEE function
SLEEP_TIME_UNIT
Sleep Time Unit
1[15:14] R/W 0x0: 1s
0x1: 1ms
0x2: 1us
1[11:0]
Default
R/W
2’d2
SLEEP_TIME
The time to sleep = SLEEP_TIME_UNIT * SLEEP_TIME
WAKE_TIME_UNIT_P0
Wake Up Time Unit for Port 0
2[15:14] R/W 0x0: 1s
0x1: 1ms
0x2: 1us
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8’hFF
12’d15
2’d2
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
Description
Default
WAKE_TIME_P0
Wake Up Time for Port 0
2[11:0] R/W The time to wake = WAKE_TIME_UNIT_P0 * WAKE_TIME_P0
12’d35
The time is between when switch de-assert LPI and when it can send
data.
WAKE_TIME_UNIT_P1
3[15:14] R/W
2’d2
Wake Up Time Unit for Port 1
WAKE_TIME_P1
Wake Up Time for Port 1
WAKE_TIME_UNIT_P2
4[15:14] R/W
Wake Up Time Unit for Port 2
3[11:0]
4[11:0]
R/W
R/W
5[15:14] R/W
5[11:0]
R/W
6[15:14] R/W
6[11:0]
R/W
7[15:14] R/W
7[11:0]
R/W
8[15:14] R/W
8[11:0]
R/W
9[15:14] R/W
9[11:0]
R/W
WAKE_TIME_P2
Wake Up Time for Port 2
12’d35
2’d2
12’d35
WAKE_TIME_UNIT_P3
Wake Up Time Unit for Port 3
WAKE_TIME_P3
Wake Up Time for Port 3
2’d2
12’d35
WAKE_TIME_UNIT_P4
Wake Up Time Unit for Port 4
WAKE_TIME_P4
Wake Up Time for Port 4
2’d2
12’d35
WAKE_TIME_UNIT_P5
Wake Up Time Unit for Port 5
WAKE_TIME_P5
Wake Up Time for Port 5
2’d2
12’d35
WAKE_TIME_UNIT_P6
Wake Up Time Unit for Port 6
WAKE_TIME_P6
Wake Up Time for Port 6
2’d2
12’d35
WAKE_TIME_UNIT_P7
Wake Up Time Unit for Port 7
WAKE_TIME_P7
Wake Up Time for Port 7
2’d2
12’d35
6.27 WOL (Wake on LAN)
PHY
MII
R/W
10[15:8] R/W
Description
WOL_EN[7:0]
Wake on lan enable for each port
10[7:2]
R/W RESERVED
10[1:0]
WOL_TIMER
0x0: disable
R/W 0x1: 3min
0x2: 5min
0x3: 10min
22
P(8’h00)
2’b0
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Default
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
6.28 Link Aggregation
PHY
MII
R/W
11[15:5]
Description
Default
RESERVED
AGGR_IDX_SEL
Aggregation Index Selection
11[4:3]
R/W 2’b00: index[2:0]
2’b01: {index[3], index[1:0]}
2’b10: {index[3:2], index[0]}
2’b11: index[3:1]
2’b00
AGGR_MODE
Aggregation Mode
11[2:0]
R/W 3’b000: SMAC
3’b001: DMAC
3’b010: SMAC xor DMAC
3’b011: Source port
12[7:0]
R/W
13[7:0]
22
3’b000
AGGR_GROUP0
Aggregation Group 0
AGGR_GROUP1
R/W
Aggregation Group 1
8’h00
8’h00
14[7:0]
AGGR_MASK0
R/W Aggregation Port Mask 0
Only one port can be selected in each aggregation group
15[7:0]
R/W
16[7:0]
17[7:0]
18[7:0]
19[7:0]
20[7:0]
AGGR_MASK1
Aggregation Port Mask 1
AGGR_MASK2
R/W
Aggregation Port Mask 2
8’hFF
8’hFF
AGGR_MASK3
Aggregation Port Mask 3
AGGR_MASK4
R/W
Aggregation Port Mask 4
R/W
8’hFF
8’hFF
AGGR_MASK5
Aggregation Port Mask 5
AGGR_MASK6
R/W
Aggregation Port Mask 6
8’hFF
R/W
8’hFF
AGGR_MASK7
Aggregation Port Mask 7
6.29 VLAN Group Control Register
21[7:0]
R/W
6.29.1
VLAN Classification
PHY
MII
23
0[15]
0[14]
8’hFF
8’hFF
R/W
Description
VLAN_TABLE_CLR
Clear the contents of VLAN TABLE register
R/W
1: clear register
(SC)
0: do nothing (default)
Self-clear after set and register cleared
Default
1’b0
RESERVED
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Data Sheet
PHY
MII
0[13]
R/W
PHY
VLAN_CLS[7:0]
VLAN Classification associated with each port
Only active at tagged-based VLAN
0 : use VID to classify VLAN
R/W
-use VID to search VLAN table if tag packet
-use PVID to search VLAN table if untag packet
1 : use PVID to classify VLAN
-always use PVID to search VLAN table
8’h00
TAG_VLAN_EN
Tag-based VLAN enable
8’h00
VLAN Ingress Rule
MII
R/W
2[15:14]
RESERVED
2[13]
1’b0
RESERVED
1[7:0]
6.29.2
Default
UNVID_MODE
Unknown-VID Mode
R/W
0: discard
1 : flood packet
0[12:0]
1[15:8]
Description
R/W
Description
Default
VLAN_DROP_CFI
Drop incoming frame, if the CFI field is not equal to zero.
RSVD_VID[2:0]
Reserved VID
Bit 0
2[12:10] R/W
Bit 1
23
Bit 2
1’b0
The null VID. If set, frames with null VID (priority-tagged frame)
treat as untagged frames.
0: disable
1: enable (default)
VID=1 (default VID)
Replace default VID with PVID
0: disable (default)
1: enable
VID=FFF
Discard frame if the VID is the value FFF
0: disable(default)
1: enable
3’b001
ACCEPTABLE_FRM_TYPE[1:0]
Acceptable Frame Type
2[9:8]
2[7:0]
3
R/W 2’b00 Admit all frames (default)
2’b01 Admit VLAN-tagged frames
2’b10 Admit Untagged frames
2’b11 Reserved
2’b00
VLAN_INGRESS_FILTER[7:0]
VLAN Ingress Filter associated with each port
R/W
If ingress filter for a given port is set, frame shall discard on that port whose
VLAN classification does not include that port in it member set.
8’hFF
RESERVED
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IP178G-DS-R05
IP178Gx
Data Sheet
6.29.3
PHY
Default VLAN Information
MII
R/W
5[15:0]
R/W
VLAN_INFO_0.
Port 0 default VLAN information value (PVID_0)
16’h0001
6[15:0]
R/W
VLAN_INFO_1.
Port 1 default VLAN information value (PVID_1)
16’h0001
7[15:0]
R/W
VLAN_INFO_2.
Port 2 default VLAN information value (PVID_2)
16’h0001
8[15:0]
R/W
VLAN_INFO_3.
Port 3 default VLAN information value (PVID_3)
16’h0001
9[15:0]
R/W
VLAN_INFO_4.
Port 4 default VLAN information value (PVID_4)
16’h0001
10[15:0] R/W
VLAN_INFO_5.
Port 5 default VLAN information value (PVID_5)
16’h0001
11[15:0] R/W
VLAN_INFO_6.
Port 6 default VLAN information value (PVID_6)
16’h0001
12[15:0] R/W
VLAN_INFO_7.
Port 7 default VLAN information value (PVID_7)
16’h0001
23
6.29.4
PHY
MII
Description
Default
VLAN TAG Control Register
R/W
Description
Default
13[7:0]
ADD_TAG[7:0]
Port x adds a VLAN tag of each outgoing packet
Bit 0: Port0
R/W
Bit 1: Port1
…
Bit7: Port7
8’h00
14[7:0]
REMOVE_TAG[7:0]
Port x removes the VLAN tag of each outgoing packet
Bit 0: Port0
R/W
Bit 1: Port1
…
Bit 7: Port7
8’h00
23
6.29.5
PHY
MII
23
15[7:0]
Port Based VLAN Member Register
R/W
Description
Default
PBV_MEMBER_P0[7:0]
R/W Port based VLAN member port
VLAN member port associated with the Port0.
8’hFF
PBV_MEMBER_P1[7:0]
15[15:8] R/W Port based VLAN member port
VLAN member port associated with the Port1.
8’hFF
PBV_MEMBER_P2[7:0]
R/W Port based VLAN member port
VLAN member port associated with the Port2.
8’hFF
PBV_MEMBER_P3[7:0]
16[15:8] R/W Port based VLAN member port
VLAN member port associated with the Port3.
8’hFF
16[7:0]
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Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
Description
Default
PBV_MEMBER_P4[7:0]
R/W Port based VLAN member port
VLAN member port associated with the Port4.
8’hFF
PBV_MEMBER_P5[7:0]
17[15:8] R/W Port based VLAN member port
VLAN member port associated with the Port5.
8’hFF
17[7:0]
PBV_MEMBER_P6[7:0]
R/W Port based VLAN member port
VLAN member port associated with the Port6.
PBV_MEMBER_P7[7:0]
18[15:8] R/W Port based VLAN member port
VLAN member port associated with the Port7.
8’hFF
18[7:0]
6.29.6
PHY
MII
Leaky VLAN Control Register
R/W
19[15:3]
23
19[2:0]
8’hFF
Description
Default
RESERVED
LEAKY_VLAN[2:0]
Bit0: ARP leaky VLAN
R/W Bit1: Unicast forwarding leaky VLAN, DA=individual MAC & DA match
was found
Bit2: Multicast leaky VLAN
3’b000
6.30 VLAN Table
6.30.1
PHY
24
MII
VLAN Control Register
R/W
Description
0[15:0]
VLAN_VALID[15:0]
R/W VLAN filter is valid.
The VLAN filter entry X is valid associated with the VID_X.
6.30.2
VLAN Identifier Register
Description
Default
16’h
0000
PHY
MII
R/W
24
1[11:0]
R/W
VID_0[11:0]
VLAN identifier associated with VLAN 0.
12’h001
2[11:0]
R/W
VID_1[11:0]
VLAN identifier associated with VLAN 1.
12’h002
3[11:0]
R/W
VID_2[11:0]
VLAN identifier associated with VLAN 2.
12’h003
4[11:0]
R/W
VID_3[11:0]
VLAN identifier associated with VLAN 3.
12’h004
5[11:0]
R/W
VID_4[11:0]
VLAN identifier associated with VLAN 4.
12’h005
6[11:0]
R/W
VID_5[11:0]
VLAN identifier associated with VLAN 5.
12’h006
7[11:0]
R/W
VID_6[11:0]
VLAN identifier associated with VLAN 6.
12’h007
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Default
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
Description
8[11:0]
R/W
VID_7[11:0]
VLAN identifier associated with VLAN 7.
12’h008
9[11:0]
R/W
VID_8[11:0]
VLAN identifier associated with VLAN 8.
12’h009
VID_9[11:0]
VLAN identifier associated with VLAN 9.
VID_A[11:0]
11[11:0] R/W
VLAN identifier associated with VLAN A.
1011:0] R/W
VID_B[11:0]
VLAN identifier associated with VLAN B.
VID_C[11:0]
13[11:0] R/W
VLAN identifier associated with VLAN C.
12[11:0] R/W
VID_D[11:0]
VLAN identifier associated with VLAN D.
VID_E[11:0]
15[11:0] R/W
VLAN identifier associated with VLAN E.
14[11:0] R/W
16[11:0] R/W
6.30.3
PHY
MII
24
17[7:0]
VID_F[11:0]
VLAN identifier associated with VLAN F.
Default
12’h00A
12’h00B
12’h00C
12’h00D
12’h00E
12’h00F
12’h010
VLAN Member Register
R/W
Description
Default
VLAN_MEMBER_0[7:0]
R/W VLAN member port
VLAN member port associated with the VID_0.
8’hFF
VLAN_MEMBER_1[7:0]
17[15:8] R/W VLAN member port
VLAN member port associated with the VID_1.
8’hFF
VLAN_MEMBER_2[7:0]
R/W VLAN member port
VLAN member port associated with the VID_2.
8’hFF
18[7:0]
VLAN_MEMBER_3[7:0]
18[15:8] R/W VLAN member port
VLAN member port associated with the VID_3.
VLAN_MEMBER_4[7:0]
19[7:0] R/W VLAN member port
VLAN member port associated with the VID_4.
VLAN_MEMBER_5[7:0]
19[15:8] R/W VLAN member port
VLAN member port associated with the VID_5.
8’hFF
VLAN_MEMBER_6[7:0]
R/W VLAN member port
VLAN member port associated with the VID_6.
8’hFF
VLAN_MEMBER_7[7:0]
20[15:8] R/W VLAN member port
VLAN member port associated with the VID_7.
8’hFF
20[7:0]
69 / 77
Copyright © 2014, IC Plus Corp.
8’hFF
8’hFF
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
PHY
MII
R/W
Description
Default
VLAN_MEMBER_8[7:0]
R/W VLAN member port
VLAN member port associated with the VID_8.
8’hFF
VLAN_MEMBER_9[7:0]
21[15:8] R/W VLAN member port
VLAN member port associated with the VID_9.
8’hFF
21[7:0]
VLAN_MEMBER_A[7:0]
R/W VLAN member port
VLAN member port associated with the VID_A.
VLAN_MEMBER_B[7:0]
22[15:8] R/W VLAN member port
VLAN member port associated with the VID_B.
22[7:0]
8’hFF
8’hFF
VLAN_MEMBER_C[7:0]
R/W VLAN member port
VLAN member port associated with the VID_C.
8’hFF
VLAN_MEMBER_D[7:0]
23[15:8] R/W VLAN member port
VLAN member port associated with the VID_D.
8’hFF
VLAN_MEMBER_E[7:0]
R/W VLAN member port
VLAN member port associated with the VID_E.
8’hFF
VLAN_MEMBER_F[7:0]
24[15:8] R/W VLAN member port
VLAN member port associated with the VID_F.
8’hFF
23[7:0]
24[7:0]
70 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
7
Electrical Characteristics
7.1
Absolute Maximum Rating
Stresses exceed those values listed under Absolute Maximum Ratings may cause permanent damage to
the device. Functional performance and device reliability are not guaranteed under these conditions. All
voltages are specified with respect to GND.
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Ambient Operating Temperature (Ta) (IP178G/GH)
IC Junction Temperature (Tj) (IP178G/GH)
Ambient Operating Temperature (Ta) (IP178GI)
IC Junction Temperature (Tj) (IP178 GI)
7.2
Item
1
2
3
4
5
6
7
8
9
10
11
7.3
– 0.3V to 3.63V
– 0.3V to 3.63V
– 0.3V to 3.63V
– 65°C to 150°C
0°C to 70°C
0°C to 125°C
– 40°C to 85°C
– 40°C to 125°C
Crystal Specifications
Range
Parameter
Nominal Frequency
Oscillation Mode
Frequency Tolerance at 25℃
Temperature Characteristics
Operating Temperature Range
Equivalent Series Resistance
Drive Level
Load Capacitance
Shunt Capacitance
Insulation Resistance
Aging Rate A Year
25.000 MHz
Fundamental Mode
+/- 50 ppm
+/- 50 ppm
-10℃ ~ +70℃
40 ohm Max.
100μW
20 pF
7 pF Max
Mega ohm Min./DC 100V
+/- 5 ppm/year
DC Characteristic
7.3.1
Operating Conditions
Parameter
Core Supply Voltage
Analog Low Supply Voltage
LDO drop voltage
Analog High Supply Voltage
I/O pad Supply Voltage
LDO output current
Power Consumption
Sym.
DVDD
AV10
VLDODRP
AV33
PVDD
ILDO
P100MF
P10MF
PIDLE
Min.
Typ.
Max.
1.05
1.1
1.23
1.0
1.3
3.3
3.45
3.15
130
950
880
180
71 / 77
Copyright © 2014, IC Plus Corp.
Unit
Conditions
V
mA
All port link 100M Full activ
mW All port link 10M Full activ
All port unlink
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
7.3.2
Input Clock
Parameter
Frequency
Frequency Tolerance
7.3.3
Sym.
F
FT
Typ.
25
Max.
-50
+50
Unit
MHz
ppm
Conditions
Unit
Conditions
I/O Electrical Characteristics
Parameter
Input Low Voltage
-LED PAD direct mode
-LED PAD bicolor mode
-NOT LED PAD
Input High Voltage
-LED PAD direct mode
-LED PAD bicolor mode
-NOT LED PAD
X1 Input Low Voltage
X1 Input High Voltage
Output Low Voltage
Output High Voltage
RESETB Threshold
Voltage
7.4
Min.
Sym
Min.
Max.
0.39*PVDD
0.36*PVDD
0.4*PVDD
VIL
0.58*PVDD
0.58*PVDD
0.6*PVDD
VIH
VILosc
VIHosc
VOL
VOH
0.8*PVDD
VTHRST
0.4*PVDD
V
V
0.6
1.5
0.1*PVDD
0.6*PVDD
V
V
V
V
V
AC Timing
7.4.1
Power On Sequence and Reset Timing
Description
X1 valid period before reset released
Reset period
All power source ready before reset released
Time difference between VCC3.3 and VCC1.0 (Tdiff)
3.3V Power
Min.
Typ.
Max.
Unit
10
10
10
-2
-
-
ms
ms
ms
ms
Tdiff
1.1V Power
OSC stable
2.1ms
OSCI (X1)
RESET released
RESET
X1 vaild period
before reset
relaesed
RESET
period
72 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
7.4.2
Serial Management Imierface Timing
Symbol
Tch
Tcl
Tcm
Tmd
Tmh
Tms
Description
MDC High Time
MDC Low Time
MDC period
MDIO output delay
MDIO setup time
MDIO hold time
Min.
Typ.
Max.
Unit
200
200
400
5
10
10
-
20
-
ns
ns
ns
ns
ns
ns
MDC
T ms
T mh
M D IO
W r ite C yc le
MDC
T cl
T ch
Tmd
T cm
M D IO
R e a d C yc le
73 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
7.4.3
EEPROM Timing
7.4.3.1
Data read cycle
Symbol
Description
TSCL
TsSCL
ThSCL
Receive clock period
SDA to SCL setup time
SDA to SCL hold time
Min.
Typ.
Max.
Unit
2
0.5
20480
-
-
ns
ns
ns
Min.
Typ.
Max.
Unit
-
20480
-
5200
ns
ns
T SCL
SCL
T hS C L
SDA
T sSCL
R ead data cycle
7.4.3.2
Command cycle
Symbol
Description
TSCL
TdSCL
Transmit clock period
SCL falling edge to SDA
T SCL
SCL
T dSCL
SDA
Comand cycle
7.5
Thermal Data
IP178Gx
Theta Ja
29.9
25.4
Theta Jc
14.1
12.7
Psi JT
4.3
4.1
74 / 77
Copyright © 2014, IC Plus Corp.
Conditions
2 Layer PCB
4 Layer PCB
Units
o
C/W
o
C/W
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
8
Order Information
Part No.
IP178G/GH
IP178GI
Package
68-Lead QFN
68-Lead QFN
Operating Temperature
0°C to 70°C
-40°C to 85°C
75 / 77
Copyright © 2014, IC Plus Corp.
Notice
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
9
Package Detail
9.1
68 QFN Outline Dimensions
Symbol
A
A1
A3
b
D/E
D2/E2
e
L
R
K
aaa
bbb
ccc
ddd
eee
fff
Dimension in mm
Dimension in inch
MIN
NOM
MAX
MIN
0.80
0.00
0.85
0.02
0.20 REF
0.20
8.00
4.30
0.40 BSC
0.40
----0.10
0.07
0.10
0.05
0.08
0.10
0.90
0.05
0.031
0.000
0.15
7.90
4.15
0.30
0.075
0.20
0.25
8.10
4.45
0.50
-----
NOM
MAX
0.033 0.035
0.001 0.002
0.008 REF
0.006 0.008 0.010
0.311 0.315 0.319
0.163 0.169 0.175
0.016 BSC
0.012 0.016 0.020
0.003
----0.008
----0.004
0.003
0.004
0.002
0.003
0.004
NOTE:
1. CONTROLLING DIMENSION : MILLMETER
2. REFERENCE DOCUMENT : JEDEC MO-220
76 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
IP178Gx
Data Sheet
9.2
68 QFN PCB footprint
IC Plus Corp.
Headquarters
10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,
Hsin-Chu City, Taiwan 300, R.O.C.
TEL: 886-3-575-0275
FAX: 886-3-575-0475
Website: www.icplus.com.tw
Sales Office
4F, No. 106, Hsin-Tai-Wu Road, Sec.1,
Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.
TEL: 886-2-2696-1669
FAX: 886-2-2696-2220
77 / 77
Copyright © 2014, IC Plus Corp.
March 18, 2015
IP178G-DS-R05
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湘ICP备2023018690号
