HEF4027BT,653

HEF4027B Dual JK flip-flop Rev. 11 — 7 December 2021 Product data sheet 1. General description The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data is accepted when nCP is LOW, and transferred to the output on the positive-going edge of the clock. The asynchronous clear-direct (nCD) and set-direct (nSD) are independent and override the nJ, nK, and nCP inputs. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits • • • • • • • • • Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V Specified from -40 °C to +85 °C 3. Applications • • • Registers Counters Control circuits 4. Ordering information Table 1. Ordering information Type number Package HEF4027BT Temperature range Name Description Version -40 °C to +85 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4027B Nexperia Dual JK flip-flop 5. Functional diagram FF 1 9 1SD 10 1J 13 1CP 11 1K 1Q 15 1Q 14 2Q 1 2Q 2 1CD 12 FF 2 7 2SD 6 2J 3 2CP 5 2K 2CD 4 001aae593 Fig. 1. Functional diagram CP C J Q C C C C C C C Q K C C CD SD Fig. 2. 001aae595 Logic diagram of one flip-flop HEF4027B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 2 / 11 HEF4027B Nexperia Dual JK flip-flop 6. Pinning information 6.1. Pinning HEF4027B 2Q 1 16 VDD 2Q 2 15 1Q 2CP 3 14 1Q 2CD 4 13 1CP 2K 5 12 1CD 2J 6 11 1K 2SD 7 10 1J VSS 8 9 1SD 001aae594 Fig. 3. Pin configuration SOT109-1 (SO16) 6.2. Pin description Table 2. Pin description Symbol Pin Description VSS 8 ground supply voltage 1SD, 2SD 9, 7 asynchronous set-direct input (active HIGH) 1J, 2J 10, 6 synchronous input 1K, 2K 11, 5 synchronous input 1CD, 2CD 12, 4 asynchronous clear-direct input (active HIGH) 1CP, 2CP 13, 3 clock input (LOW-to-HIGH edge-triggered) 1Q, 2Q 14, 2 complement output 1Q, 2Q 15, 1 true output VDD 16 supply voltage 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care.; ↑ = positive-going transition. Inputs Outputs nSD nCD nCP nJ nK nQ nQ H L X X X H L L H X X X L H H H X X X H H L L ↑ L L no change no change L L ↑ H L H L L L ↑ L H L H L L ↑ H H nQ nQ HEF4027B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 3 / 11 HEF4027B Nexperia Dual JK flip-flop 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O Conditions Min Max Unit -0.5 +18 V - ±10 mA -0.5 VDD + 0.5 - ±10 mA input/output current - ±10 mA IDD supply current - 50 mA Tstg storage temperature -65 +150 °C Tamb ambient temperature in free air -40 +85 °C Ptot total power dissipation Tamb -40 °C to +85 °C - 500 mW P power dissipation per output - 100 mW VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V V 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Max VDD supply voltage Conditions 3 15 Unit V VI input voltage 0 VDD V Tamb ambient temperature in free air -40 +85 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - 3.75 μs/V VDD = 10 V - 0.5 μs/V VDD = 15 V - 0.08 μs/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions VDD Min Max Min Max Min Max VIH HIGH-level input voltage |IO| < 1 μA 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V VIL VOH VOL LOW-level input voltage HIGH-level output voltage LOW-level output voltage HEF4027B Product data sheet |IO| < 1 μA |IO| < 1 μA |IO| < 1 μA Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 4 / 11 HEF4027B Nexperia Dual JK flip-flop Symbol IOH IOL Parameter Conditions HIGH-level output current LOW-level output current II input leakage current IDD supply current CI VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit Min Max Min Max Min Max VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 VO = 4.6 V 5V - -0.52 - -0.44 - -0.36 mA VO = 9.5 V 10 V - -1.3 - -1.1 - -0.9 mA VO = 13.5 V 15 V - -3.6 - -3.0 - -2.4 mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - ±0.3 - ±0.3 - ±1.0 μA 5V - 4.0 - 4.0 - 30 μA 10 V - 8.0 - 8.0 - 60 μA 15 V - 16.0 - 16.0 - 120 μA - - - - 7.5 - - pF Min Typ Max Unit IO = 0 A input capacitance mA 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C unless otherwise specified; for test circuit see Fig. 7. Symbol Parameter Conditions VDD Extrapolation formula [1] tPHL CP → Q, Q; see Fig. 4 5V 78 ns + (0.55 ns/pF)CL - 105 210 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 93 ns + (0.55 ns/pF)CL - 120 240 ns 10 V 33 ns + (0.23 ns/pF)CL - 45 90 ns 15 V 27 ns + (0.16 ns/pF)CL - 35 70 ns 5V 113 ns + (0.55 ns/pF)CL - 140 280 ns 10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 58 ns + (0.55 ns/pF)CL - 85 170 ns 10 V 27 ns + (0.23 ns/pF)CL - 35 70 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 48 ns + (0.55 ns/pF)CL - 75 150 ns 10 V 24 ns + (0.23 ns/pF)CL - 35 70 ns 15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns 5V 43 ns + (0.55 ns/pF)CL - 70 140 ns 10 V 19 ns + (0.23 ns/pF)CL - 30 60 ns 15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns [2] 10 ns + (1.00 ns/pF)CL - 60 120 ns HIGH to LOW propagation delay CD → Q; see Fig. 4 SD → Q; see Fig. 4 tPLH LOW to HIGH propagation delay CP → Q, Q; see Fig. 4 CD → Q; see Fig. 4 SD → Q; see Fig. 4 tt tsu transition time set-up time HEF4027B Product data sheet see Fig. 4 J, K → CP; see Fig. 5 5V 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V 50 25 - ns 10 V 30 10 - ns 15 V 20 5 - ns All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 5 / 11 HEF4027B Nexperia Dual JK flip-flop Symbol Parameter Conditions VDD th J, K → CP; see Fig. 5 hold time tW pulse width trec recovery time fmax [1] [2] maximum frequency Extrapolation formula [1] Min Typ Max Unit 5V 25 0 - ns 10 V 20 0 - ns 15 V 15 5 - ns CP LOW; minimum width; see Fig. 5 5V 80 40 - ns 10 V 30 15 - ns 15 V 24 12 - ns SD, CD HIGH; minimum width; see Fig. 6 5V 90 45 - ns 10 V 40 20 - ns 15 V 30 15 - ns SD, CD inputs; see Fig. 6 5V +20 -15 - ns 10 V +15 -10 - ns 15 V +10 -5 - ns CP input; J = K = HIGH; see Fig. 5 5V 4 8 - MHz 10 V 12 25 - MHz 15 V 15 30 - MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). tt is the same as tTLH and tTHL. Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (μW) 5V PD = 900 × fi + Σ(fo × CL) × VDD Where: 2 fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VDD = supply voltage in V Σ(fo × CL) = sum of the outputs 2 10 V PD = 4500 × fi + Σ(fo × CL) × VDD 15 V PD = 13200 × fi + Σ(fo × CL) × VDD 2 11.1. Waveforms and test circuit tr VI SD, CD or CP INPUT 0V tf 90 % 10 % VM tPLH VOH Q or Q OUTPUT VOL tPHL 90 % VM 10 % tTLH tTHL 001aah863 VOH and VOL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Fig. 4. Waveforms showing rise, fall, and transition times, and propagation delays HEF4027B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 6 / 11 HEF4027B Nexperia Dual JK flip-flop 1/fmax CP INPUT tW VM th J,K INPUT VM tsu 001aae596 Measurement points are given in Table 9. Fig. 5. Waveforms showing set-up times, hold times, and minimum clock pulse width VI SD INPUT VM 0V tW VI VM CD INPUT 0V tW trec trec VI CP INPUT VM 0V VOH Q OUTPUT VOL 001aae597 VOH and VOL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Fig. 6. Waveforms showing pulse widths and recovery times Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD VDD G VI VO DUT CL RT 001aag182 Test data is given in Table 10. Definitions for test circuit: CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig. 7. Test circuit Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4027B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 7 / 11 HEF4027B Nexperia Dual JK flip-flop 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF4027B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 8 / 11 HEF4027B Nexperia Dual JK flip-flop 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4027B v.11 20211207 Product data sheet - HEF4027B v.10 Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Section 13 added. HEF4027B v.10 20160321 Modifications: • HEF4027B v.9 20111118 Modifications: • • HEF4027B v.8 20111010 HEF4027B v.7 20091125 HEF4027B v.6 Product data sheet - HEF4027B v.9 Type number HEF4027BP (SOT38-4) removed. - HEF4027B v.8 Product data sheet - HEF4027B v.7 Product data sheet - HEF4027B v.6 20090624 Product data sheet - HEF4027B v.5 HEF4027B v.5 20081110 Product data sheet - HEF4027B v.4 HEF4027B v.4 20080703 Product specification - HEF4027B_CNV v.3 HEF4027B_CNV v.3 19950101 Product specification - HEF4027B_CNV v.2 HEF4027B_CNV v.2 19950101 Product specification - - HEF4027B Product data sheet Product data sheet Legal pages updated. Changes in Section 1 and Section 2 All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 9 / 11 HEF4027B Nexperia Dual JK flip-flop 15. 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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 10 / 11 HEF4027B Nexperia Dual JK flip-flop Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................5 11.1. Waveforms and test circuit........................................ 6 12. Package outline.......................................................... 8 13. Abbreviations.............................................................. 9 14. Revision history..........................................................9 15. Legal information......................................................10 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 7 December 2021 HEF4027B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 11 / 11