74HCT4046ADB,118

74HC4046A; 74HCT4046A Phase-locked loop with VCO Rev. 4 — 6 August 2019 Product data sheet 1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • • • • • • • • • Low power consumption VCO-Inhibit control for ON/OFF keying and for low standby power consumption Center frequency up to 17 MHz (typical) at VCC = 4.5 V Choice of three phase comparators: • PC1: EXCLUSIVE-OR • PC2: Edge-triggered J-K flip-flop • PC3: Edge-triggered RS flip-flop Excellent Voltage Controlled Oscillator (VCO) linearity Low frequency drift with supply voltage and temperature variations Operating power supply voltage range: • VCO section 3.0 V to 6.0 V • Digital section 2.0 V to 6.0 V Zero voltage offset due to operational amplifier buffering ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V 3. Applications • • • • • • • FM modulation and demodulation Frequency synthesis and multiplication Frequency discrimination Tone decoding Data synchronization and conditioning Voltage-to-frequency conversion Motor-speed control 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 4. Ordering information Table 1. Ordering information Type number Package 74HC4046AD Name Description Version SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT4046AD 74HC4046ADB 74HCT4046ADB 74HC4046APW 5. Block diagram C1 6 C1A 7 C1B 4 VCO_OUT 3 COMP_IN 14 SIG_IN 4046A PHASE COMPARATOR 1 R2 12 R2 VCO PHASE COMPARATOR 2 R1 11 R1 PHASE COMPARATOR 3 5 INH 10 DEM_OUT PC1_OUT 2 PC2_OUT 13 R3 PCP_OUT 1 R4 PC3_OUT 15 C2 9 VCO_IN RS aaa-020201 Fig. 1. Block diagram 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 2 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 6. Functional diagram COMP_IN 3 Ø SIG_IN Fig. 2. 14 2 PC1_OUT 15 PC3_OUT 13 PC2_OUT 1 PCP_OUT 2 PC1_OUT 14 13 PC2_OUT COMP_IN 3 15 PC3_OUT 1 PCP_OUT SIG_IN C1A 6 C1A 6 C1B 7 C1B 7 R1 11 R2 12 VCO_IN 9 INH 5 4 VCO_OUT VCO 10 DEM_OUT R1 11 R2 12 VCO_IN INH aaa-020202 Logic symbol Fig. 3. ∏ # 4046A 9 10 4 ∏ DEM_OUT # VCO_OUT 5 aaa-020203 IEC logic symbol C1 R2 12 6 7 4 C1A C1B VCO_OUT COMP_IN 3 14 SIG_IN PC1_OUT 2 Vref VCO R2 SD Q R1 11 PC3_OUT 15 Q RD R1 DEM_OUT 10 `1' D Q UP P CP RS Q RD `1' D CP 5 INH 13 PC2_OUT N Q Q RD VCC DOWN GND R3 R4 1 PCP_OUT C2 9 VCO_IN aaa-020204 Fig. 4. Logic diagram 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 3 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 7. Pinning information 7.1. Pinning 74HC4046A 74HCT4046A PCP_OUT 1 16 VCC PC1_OUT 2 15 PC3_OUT COMP_IN 3 14 SIG_IN VCO_OUT 4 13 PC2_OUT INH 5 12 R2 C1A 6 11 R1 C1B 7 74HC4046A 74HCT4046A 1 PC1_OUT 2 16 VCC 15 PC3_OUT COMP_IN 3 14 SIG_IN VCO_OUT 4 13 PC2_OUT INH 5 12 R2 C1A 6 11 R1 C1B 7 10 DEM_OUT GND 8 10 DEM_OUT GND 8 9 9 VCO_IN VCO_IN aaa-029927 aaa-020205 Fig. 5. PCP_OUT Fig. 6. Pin configuration SOT109-1 (SO16) Pin configuration SOT338-1 (SSOP16) and SOT403-1 (TSSOP16) 7.2. Pin description Table 2. Pin description Symbol Pin Description PCP_OUT 1 phase comparator pulse output PC1_OUT 2 phase comparator 1 output COMP_IN 3 comparator input VCO_OUT 4 VCO output INH 5 inhibit input C1A 6 capacitor C1 connection A C1B 7 capacitor C1 connection B GND 8 ground (0 V) VCO_IN 9 VCO input DEM_OUT 10 demodulator output R1 11 resistor R1 connection R2 12 resistor R2 connection PC2_OUT 13 phase comparator 2 output SIG_IN 14 signal input PC3_OUT 15 phase comparator 3 output VCC 16 supply voltage 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 4 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 8. Functional description The 74HC4046A; 74HCT4046A is a phase-locked-loop circuit that comprises a linear VCO and three different phase comparators (PC1, PC2 and PC3). It has a common signal input amplifier and a common comparator input (see Fig. 1). The signal input can be directly coupled to a large voltage signal, or indirectly coupled (with a series capacitor) to a small voltage signal. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 74HC4046A; 74HCT4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op amp techniques. 8.1. VCO The VCO requires one external capacitor C1 (between pins C1A and C1B) and one external resistor R1 (between pins R1 and GND). Alternatively, it requires two external resistors R1 and R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if necessary (see Fig. 4). The high input impedance of the VCO simplifies the design of the low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. In contrast to conventional techniques, where the DEM_OUT voltage is one threshold voltage lower than the VCO input voltage, the DEM_OUT voltage equals the VCO input. If DEM_OUT is used, a series resistor (Rs) should be connected from pin DEM_OUT to GND. If unused, DEM_OUT should be left open. The VCO output (pin VCO_OUT) can be connected directly to the comparator input (pin COMP_IN) or connected via a frequency divider. When the VCO input DC level is held constant, the VCO output signal has a duty cycle of 50 % (maximum expected deviation 1 %). A LOW-level at the inhibit input (pin INH) enables the VCO and demodulator, while a HIGH-level turns off both to minimize standby power consumption. The only difference between the 74HC4046A and 74HCT4046A is the input level specification of the INH input. A HIGH on the INH input disables the VCO section. The input level specification for the SIG_IN and COMP_IN inputs are identical for both 74HC4046A and 74HCT4046A. 8.2. Phase comparators The input signal can be coupled to the self-biasing amplifier at pin SIG_IN, when the signal swing is between the standard HC/T family input logic levels. Capacitive coupling is required for signals with smaller swings. 8.2.1. Phase Comparator 1 (PC1) This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must have a 50 % duty cycle to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: where: • • VDEM_OUT is the demodulator output at pin DEM_OUT VDEM_OUT = VPC1_OUT (via low-pass filter) The phase comparator gain is: 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 5 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO PC1 is fed to the VCO input via the low-pass filter and provided at the demodulator output at pin DEM_OUT (VDEM_OUT). The average output voltage from PC1 is the result of the phase differences of signals (SIG_IN) and the comparator input (COMP_IN). These phase differences are shown in Fig. 7. The average of VDEM_OUT is equal to 0.5VCC when no signal or noise is present at SIG_IN. Using this input, the VCO oscillates at the center frequency (f0). Typical waveforms for the PC1 loop locked at f0 are shown in Fig. 8. The frequency capture range (2fc) is defined as the frequency range of input signals on which the PLL locks when it was initially out-of-lock. The frequency lock range (2fL) is the frequency range of the input signals on which the loop stays locked when it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration remains locked even with very noisy input signals. Typical behavior of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO center frequency. VCC VDEM_OUT (V) 1/2 VCC 0 0 π/2 ØDEM_OUT(rad) π aaa-020206 Fig. 7. Phase comparator 1; average output voltage as a function of input phase difference SIG_IN COMP_IN VCO_OUT PC1_OUT VCC VCO_IN GND aaa-020207 Fig. 8. 74HC_HCT4046A Product data sheet Typical waveforms for PLL using phase comparator 1; loop-locked at f0 All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 6 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 8.2.2. Phase Comparator 2 (PC2) PC2 is a positive edge-triggered phase and frequency detector. When the PLL uses this comparator, positive signal transitions control the loop and the duty cycles of SIG_IN and COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state output stage. The circuit functions as an up-down counter (see Fig. 4) where SIG_IN causes an up-count and COMP_IN a down count. The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is: where: • • VDEM_OUT is the demodulator output at pin DEM_OUT VDEM_OUT = VPC2_OUT (via low-pass filter) The phase comparator gain is: VDEM_OUT is the resultant of the initial phase differences of SIG_IN and COMP_IN as shown in Fig. 9. Typical waveforms for the PC2 loop locked at fo are shown in Fig. 10. When the SIG_IN and COMP_IN frequencies are equal but the phase of SIG_IN leads that of COMP_IN, the p-type output driver at PC2_OUT is held ‘ON’. The time that it is held 'ON’ corresponds with the phase difference (ΦDEM_OUT). When the phase of SIG_IN lags that of COMP_IN, the n-type driver is held ‘ON’. When the SIG_IN frequency is higher than the COMP_IN frequency, the p-type output driver is held ‘ON’ for most of the input signal cycle time. For the remainder of the cycle time, both n- and p-type drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN frequency, the n-type driver is held ‘ON’ for most of the cycle. The voltage at capacitor (C2) of the low-pass filter, connected to PC2_OUT, varies until the phase and frequency of the signal and comparator inputs are equal. At this stable point, the voltage on C2 remains constant as the PC2 output is in 3state and the VCO_IN input is in a high-impedance state. In this condition, the signal at the phase comparator pulse output (PCP_OUT) is a HIGH level and can be used for indicating a locked condition. Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full frequency range of the VCO. The power dissipation due to the low-pass filter is reduced because both n- and p-type output drivers are ‘OFF’ for most of the signal input cycle. The PLL lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. With no signal present at SIG_IN the VCO adjust, via PC2, to its lowest frequency. 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 7 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO VCC VDEM_OUT (V) 1/2 VCC 0 -2π 0 ØDEM_OUT(rad) 2π aaa-020208 Fig. 9. Phase comparator 2; average output voltage as a function of input phase difference SIG_IN COMP_IN VCO_OUT VCC PC2_OUT high impedance OFF - state GND VCO_IN PCP_OUT aaa-020209 Fig. 10. Typical waveforms for PLL using phase comparator 2; loop-locked at f0 8.2.3. Phase Comparator 3 (PC3) PC3 is a positive edge-triggered sequential phase detector using an RS-type flip-flop. When the PLL is using this comparator, positive signal transitions control the loop and the duty factors of SIG_IN and COMP_IN are not important. The transfer characteristic of PC3, assuming ripple (fr = fi) is suppressed, is: where: • • VDEM_OUT is the demodulator output at pin DEM_OUT VDEM_OUT = VPC3_OUT (via low-pass filter) The phase comparator gain is: 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 8 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO PC3 is fed to the VCO via the low-pass filter and present at the demodulator output at pin DEM_OUT. The average output from PC3 is the resultant of the phase differences of SIG_IN and COMP_IN, see Fig. 11. Typical waveforms for the PC3 loop locked at fo are shown in Fig. 12. The phase-to-output response characteristic of PC3 (Fig. 11) differs from PC2 in that the phase angle between SIG_IN and COMP_IN varies between 0° and 360°. It is 180° at the center frequency. Also PC3 gives a greater voltage swing than PC2 for input phase differences. As a result, the ripple content of the VCO input signal is higher. The PLL lock range for this type of phase comparator and the capture range are dependent on the low-pass filter. With no signal present at SIG_IN, the VCO adjusts to its lowest frequency via PC3. VCC VDEM_OUT (V) 1/2 VCC 0 0 π ØDEM_OUT(rad) 2π aaa-020210 Fig. 11. Phase comparator 3; average output voltage as a function of input phase difference SIG_IN COMP_IN VCO_OUT PC3_OUT VCC VCO_IN GND aaa-020211 Fig. 12. Typical waveforms for PLL using phase comparator 3; loop-locked at f0 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 9 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 9. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK IO ICC Min Max -0.5 +7 V VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA output current -0.5 V < VO < VCC + 0.5 V - ±25 mA supply current - +50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] Conditions Tamb = -40 °C to +125 °C [1] Unit For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. 10. Recommended operating conditions Table 4. Recommended operating conditions Symbol Parameter Conditions VCC 74HC4046A supply voltage when VCO is not used 74HCT4046A Unit Min Typ Max Min Typ Max 3.0 5.0 6.0 4.5 5.0 5.5 V 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V - ns/V pin INH VCC = 6.0 V Tamb ambient temperature 74HC_HCT4046A Product data sheet - - 83 - - -40 +25 +125 -40 +25 All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © +125 °C Nexperia B.V. 2019. All rights reserved 10 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 11. Static characteristics 11.1. Static characteristics 74HC4046A Table 5. Static characteristics 74HC4046A At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V Phase comparator section VIH VIL VOH VOL II IOZ HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current OFF-state output current SIG_IN, COMP_IN; DC coupled SIG_IN, COMP_IN; DC coupled PCP_OUT, PCn_OUT; VI = VIH or VIL PCP_OUT, PCn_OUT; VI = VIH or VIL IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V SIG_IN, COMP_IN; VI = VCC or GND VCC = 2.0 V - - ±3 - ±4 - ±5 VCC = 3.0 V - - ±7 - ±9 - ±11 μA VCC = 4.5 V - - ±18 - ±23 - ±27 μA VCC = 6.0 V - - ±30 - ±38 - ±45 μA - - ±0.5 - ±5 - ±10 μA VCC = 3.0 V - 800 - - - - - kΩ VCC = 4.5 V - 250 - - - - - kΩ VCC = 6.0 V - 150 - - - - - kΩ PC2_OUT; VI = VIH or VIL; VO = VCC or GND VCC = 6.0 V RI input resistance 74HC_HCT4046A Product data sheet μA SIG_IN, COMP_IN; VI at self-bias operating point; ΔVI = 0.5 V; see Fig. 13, Fig. 14 and Fig. 15 All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 11 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 3.0 V 2.1 1.7 - 2.1 - 2.1 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 3.0 V - 1.3 0.9 - 0.9 - 0.9 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 μA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VCO section VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage INH INH VCO_OUT; VI = VIH or VIL VCO_OUT; VI = VIH or VIL IO = 20 μA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V C1A, C1B; VI = VIH or VIL IO = 4 mA; VCC = 4.5 V - - 0.40 - 0.47 - 0.54 V IO = 5.2 mA; VCC = 6.0 V - - 0.40 - 0.47 - 0.54 V II input leakage current INH, VCO_IN; VI = VCC or GND - - ±0.1 - ±1 - ±1 μA R1 resistor 1 VCC = 3.0 V to 6.0 V [1] 3 - 300 - - - - kΩ R2 resistor 2 VCC = 3.0 V to 6.0 V [1] 3 - 300 - - - - kΩ C1 capacitor 1 VCC = 3.0 V to 6.0 V 40 - no limit - - - - pF VVCO_IN VCO_IN; over the range specified for R1; input voltage on pin VCO_IN for linearity see Fig. 23 and Fig. 24 VCC = 3.0 V 1.1 - 1.9 - - - - V VCC = 4.5 V 1.1 - 3.4 - - - - V VCC = 6.0 V 1.1 - 4.9 - - - - V 74HC_HCT4046A Product data sheet VCC = 6.0 V All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 12 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 50 - 300 - - - - kΩ VCC = 3.0 V - ±30 - - - - - mV VCC = 4.5 V - ±20 - - - - - mV VCC = 6.0 V - ±10 - - - - - mV - 25 - - - - - Ω - - 8 - 80 - - 3.5 - - - - Demodulator section Rs series resistance at Rs > 300 kΩ, the leakage current can influence VDEM_OUT VCC = 3.0 V to 6.0 V Voffset Rdyn offset voltage VCO_IN to DEM_OUT; VI = VVCO_IN = 0.5VCC; values taken over Rs range; see Fig. 16 dynamic resistance DEM_OUT; VDEM_OUT = 0.5VCC supply current VCO disabled; COMP_IN, INH and SIG_IN at VCC; VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be excluded VCC = 3.0 V to 6.0 V General ICC VCC = 6.0 V CI [1] input capacitance INH 160 μA - pF The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2 are/is > 10 kΩ. 11.2. Static characteristics 74HCT4046A Table 6. Static characteristics 74HCT4046A At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 3.15 2.4 - 3.15 - 3.15 - - 2.1 1.35 - 1.35 - IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -4 μA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V 0.1 - 0.1 - 0.1 V 0.15 0.26 - 0.33 - 0.4 V Phase comparator section VIH VIL VOH VOL II IOZ HIGH-level input voltage SIG_IN, COMP_IN; DC coupled LOW-level input voltage SIG_IN, COMP_IN; DC coupled HIGH-level output voltage PCP_OUT, PCn_OUT; VI = VIH or VIL VCC = 4.5 V VCC = 4.5 V LOW-level output voltage PCP_OUT, PCn_OUT; VI = VIH or VIL input leakage current SIG_IN, COMP_IN; VI = VCC or GND OFF-state output current PC2_OUT; VI = VIH or VIL; VO = VCC or GND IO = 20 μA; VCC = 4.5 V - IO = 4 mA; VCC = 4.5 V - VCC = 5.5 V VCC = 5.5 V 74HC_HCT4046A Product data sheet 0 1.35 V - - ±30 - ±38 - ±45 μA - - ±0.5 - ±5 - ±10 μA All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 V © Nexperia B.V. 2019. All rights reserved 13 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO Symbol Parameter RI input resistance Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 250 - - - - - kΩ 2.0 1.6 - 2.0 - 2.0 - V - 1.2 0.8 - 0.8 - IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -4 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V 0.1 - 0.1 - 0.1 V 0.15 0.26 - 0.33 - 0.4 V 0.54 V SIG_IN, COMP_IN; VI at self-bias operating point; ΔVI = 0.5 V; see Fig. 13, Fig. 14 and Fig. 15 VCC = 4.5 V VCO section VIH VIL VOH VOL HIGH-level input voltage INH LOW-level input voltage INH HIGH-level output voltage VCO_OUT; VI = VIH or VIL LOW-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 0.8 V VCO_OUT; VI = VIH or VIL IO = 20 μA; VCC = 4.5 V - IO = 4 mA; VCC = 4.5 V - 0 C1A, C1B; VI = VIH or VIL IO = 4 mA; VCC = 4.5 V - - 0.40 - 0.47 - - - ±0.1 - ±1 - ±1 μA II input leakage current INH, VCO_IN; VCC = 5.5 V; VI = VCC or GND R1 resistor 1 VCC = 4.5 V [1] 3 - 300 - - - - kΩ R2 resistor 2 VCC = 4.5 V [1] 3 - 300 - - - - kΩ C1 capacitor 1 VCC = 4.5 V 40 - no limit - - - - pF VVCO_IN VCO_IN; over the range specified for R1; input voltage on pin VCO_IN for linearity see Fig. 23 and Fig. 24 1.1 - 3.4 - - - - V 50 - 300 - - - - kΩ - ±20 - - - - - mV - 25 - - - - - Ω - - 8 - 80 - VCC = 4.5 V Demodulator section Rs series resistance at Rs > 300 kΩ, the leakage current can influence VDEM_OUT VCC = 4.5 V Voffset offset voltage VCO_IN to DEM_OUT; VI = VVCO_IN = 0.5VCC; values taken over Rs range; see Fig. 16 VCC = 4.5 V Rdyn dynamic resistance DEM_OUT; VDEM_OUT = 0.5VCC supply current VCO disabled; COMP_IN, INH and SIG_IN at VCC; VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be excluded VCC = 4.5 V General ICC VCC = 6 V 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © 160 μA Nexperia B.V. 2019. All rights reserved 14 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO Symbol Parameter ΔICC Conditions 25 °C VCC = 4.5 V to 5.5 V [1] -40 °C to +125 °C Min Typ Max Min Max Min - 100 360 - 450 - - 3.5 - - - - Unit Max INH; VI = VCC - 2.1 V; COMP_IN and SIG_IN at VCC; VCO_IN at GND; II at pins COMP_IN and SIGN_IN to be excluded additional supply current CI -40 °C to +85 °C input capacitance INH 490 μA - pF The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2 are/is > 10 kΩ. 11.3. Graphs aaa-020213 800 II (µA) RI (kΩ) VI VCC = 3.0 V 600 400 4.5 V 200 self-bias operating point 6.0 V 0 VI (V) aaa-020212 Fig. 13. Typical input resistance curve at SIG_IN and COMP_IN 0 1/2 VCC -0.25 1/2 VCC VI (V) Fig. 14. Input resistance at SIG_IN, COMP_IN with ΔVI = 0.5 V at self-bias point aaa-020215 +60 aaa-020214 +5 Voffset (mV) +40 VCC = 6.0 V II (µA) 1/2 VCC +0.25 4.5 V VCC = 3.0 V +20 3.0 V 4.5 V 0 0 3.0 V 6.0 V -20 4.5 V 6.0 V -5 1/2 VCC -0.25 -40 1/2 VCC VI (V) 1/2 VCC +0.25 Fig. 15. Input current at SIG_IN, COMP_IN with ΔVI = 0.5 V at self-bias point 74HC_HCT4046A Product data sheet 1/2 VCC -2 1/2 VCC 1/2 VCC +2 VVCO_IN (V) ___ Rs = 50 kΩ - - - Rs = 300 kΩ Fig. 16. Offset voltage at demodulator output as a function of VVCO_IN and Rs All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 15 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 12. Dynamic characteristics 12.1. Dynamic characteristics 74HC4046A Table 7. Dynamic characteristics 74HC4046A GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to Unit +125 °C Min Typ Max Min Typ Max Min Max Phase comparator section tpd propagation delay SIG_IN, COMP_IN to PC1_OUT; see Fig. 17 [1] VCC = 2.0 V - 63 200 - - 250 - 300 ns VCC = 4.5 V - 23 40 - - 50 - 60 ns - 18 34 - - 43 - 51 ns VCC = 2.0 V - 96 340 - - 425 - 510 ns VCC = 4.5 V - 35 68 - - 85 - 102 ns VCC = 6.0 V - 28 58 - - 72 - 87 VCC = 2.0 V - 77 270 - - 340 - 405 ns VCC = 4.5 V - 28 54 - - 68 - 81 ns VCC = 6.0 V - 22 46 - - 58 - 69 ns VCC = 2.0 V - 83 280 - - 350 - 420 ns VCC = 4.5 V - 30 56 - - 70 - 84 ns VCC = 6.0 V - 24 48 - - 60 - 71 ns VCC = 2.0 V - 99 325 - - 405 - 490 ns VCC = 4.5 V - 36 65 - - 81 - 98 ns VCC = 6.0 V - 29 55 - - 69 - 83 ns VCC = 2.0 V - 19 75 - - 95 - 110 ns VCC = 4.5 V - 7 15 - - 19 - 22 ns VCC = 6.0 V - 6 13 - - 16 - 19 ns VCC = 2.0 V - 9 - - - - - - mV VCC = 3.0 V - 11 - - - - - - mV VCC = 4.5 V - 15 - - - - - - mV VCC = 6.0 V - 33 - - - - - - mV VCC = 6.0 V SIG_IN, COMP_IN to PCP_OUT; see Fig. 17 SIG_IN, COMP_IN to PC3_OUT; see Fig. 17 ten tdis tt Vi(p-p) enable time disable time transition time SIG_IN, COMP_IN to PC2_OUT; see Fig. 18 SIG_IN, COMP_IN to PC2_OUT; see Fig. 18 PC1_OUT, PC3_OUT, PCP_OUT; see Fig. 17 [1] ns [1] [1] [1] [1] peak-to-peak SIGN_IN, COMP_IN; AC coupled; input voltage fi = 1 MHz 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 16 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to Unit +125 °C Min Typ Max Min Typ Max Min Max VCO section f0 center frequency VVCO_IN = 0.5VCC; duty cycle = 50 %; R1 = 3 kΩ; R2 = ∞ Ω; C1 = 40 pF; see Fig. 21 and Fig. 22 VCC = 3.0 V 7.0 10.0 - - - - - - MHz VCC = 4.5 V 11.0 17.0 - - - - - - MHz 19.0 - - - - - - MHz 13.0 21.0 - - - - - - MHz VCC = 5.0 V - VCC = 6.0 V Δf/f relative frequency variation Δf/ΔT δ R1 = 100 kΩ; R2 = ∞ Ω; C1 = 100 pF; see Fig. 23 and Fig. 24 VCC = 3.0 V - 1.0 - - - - - - % VCC = 4.5 V - 0.4 - - - - - - % VCC = 6.0 V - 0.3 - - - - - - % VCC = 3.0 V - - - - 0.20 - - - %/K VCC = 4.5 V - - - - 0.15 - - - %/K VCC = 6.0 V - - - - 0.14 - - - %/K - 50 - - - - - - % - 24 - - - - - - pF VVCO_IN = 0.5VCC; R1 = 100 kΩ; frequency variation with R2 = ∞ Ω; C1 = 100 pF; temperature see Fig. 19 and Fig. 20 duty cycle VCO_OUT; VCC = 3.0 V to 6.0 V General CPD [1] [2] [3] power dissipation capacitance [2][3] tpd is the same as tPLH and tPHL. tdis is the same as tPLZ and tPHZ. ten is the same as tPZL and tPZH. tt is the same as tTLH and tTHL. Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator sections, see Fig. 25, Fig. 26 and Fig. 27 CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total load switching outputs; 2 Σ(CL x VCC x fo) = sum of outputs. 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 17 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 12.2. Dynamic characteristics 74HCT4046A Table 8. Dynamic characteristics 74HCT4046A GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max SIG_IN, COMP_IN to PC1_OUT - 23 40 - 50 - 60 SIG_IN, COMP_IN to PCP_OUT - 35 68 - 85 - 102 ns SIG_IN, COMP_IN to PC3_OUT - 28 54 - 68 - 81 ns Phase comparator section tpd propagation delay VCC = 4.5 V; see Fig. 17 [1] ns ten enable time SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Fig. 18 [1] - 30 56 - 70 - 84 ns tdis disable time SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Fig. 18 [1] - 36 65 - 81 - 98 ns tt transition time PC1_OUT, PC3_OUT, PCP_OUT; VCC = 4.5 V; see Fig. 17 [1] - 7 15 - 19 - 22 ns Vi(p-p) peak-to-peak input voltage SIGN_IN, COMP_IN; AC coupled; VCC = 4.5 V; fi = 1 MHz - 15 - - - - - mV VCC = 4.5 V 11.0 17.0 - - - - - MHz VCC = 5.0 V VCO section f0 center frequency VVCO_IN = 0.5VCC; duty cycle = 50 %; R1 = 3 kΩ; R2 = ∞ Ω; C1 = 40 pF; see Fig. 21 and Fig. 22 - 19.0 - - - - - MHz Δf/f relative frequency variation R1 = 100 kΩ; R2 = ∞ Ω; C1 = 100 pF; VCC = 4.5 V; see Fig. 23 and Fig. 24 - 0.4 - - - - - % Δf/ΔT frequency variation with temperature VVCO_IN = 0.5VCC; R1 = 100 kΩ; R2 = ∞ Ω; C1 = 100 pF; VCC = 4.5 V; see Fig. 19 and Fig. 20 - - - 0.15 - - - %/K δ duty cycle VCO_OUT; VCC = 4.5 V - 50 - - - - - % - 24 - - - - - pF General CPD [1] [2] [3] power dissipation capacitance [2][3] tpd is the same as tPLH and tPHL. tdis is the same as tPLZ and tPHZ. ten is the same as tPZL and tPZH. tt is the same as tTLH and tTHL. Applies to the phase comparator section only (VCO disabled). For power dissipation of the VCO and demodulator sections, see Fig. 25, Fig. 26 and Fig. 27 CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total load switching outputs; 2 Σ(CL x VCC x fo) = sum of outputs. 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 18 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 12.3. Waveforms and graphs VI SIG_IN COMP_IN VM VM GND tPHL tPLH VOH PC1_OUT PC3_OUT PCP_OUT VM VM VOL tTHL tTLH aaa-020216 VM = 0.5VCC; VI = GND to VCC. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 17. Waveforms showing input (SIG_IN, COMP_IN) to output (PC1_OUT, PC3_OUT, PCP_OUT) propagation delays and the output transition times VI SIG_IN VI SIG_IN VM VM GND GND VI VI COMP_IN VM GND tPZH tPLZ VOH 90 % VM VM GND tPZL tPHZ VOH PC2_OUT COMP_IN VM PC2_OUT VOL VOL 10 % aaa-020218 VM = 0.5VCC; VI = GND to VCC. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 18. Waveforms showing the enable and disable times for PC2_OUT 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 19 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 25 25 25 f f f (%) 20 (%) 20 VCC = 6 V 5V 15 10 3V 5 (%) 20 VCC = 3 V 15 3V 5V A 5V 6V 6V 10 6V 10 5 0 0 -5 -5 -10 -10 -10 -15 -15 -15 -20 -20 -20 3V 4.5 V 5V 6V -5 -25 -50 0 50 (a) 100 150 Tamb (°C) -25 -50 0 50 (b) 100 150 Tamb (°C) 3V 5V 6V 5V 15 5 0 VCC = 3 V -25 -50 0 50 (c) 100 150 Tamb (°C) aaa-020259 To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF. In (b), the frequency stability for R1 = R2 = 10 kΩ at 5 V is also given (curve A). The total VCO bias current sets this curve, and is not simply the addition of the two 10 kΩ stability curves. C1 = 100 pF; VVCO_IN = 0.5VCC; This curve is set as follows: ___ Without offset R2 = ∞ Ω: (a) R1 = 3 kΩ; (b) R1 = 10 kΩ; (c) R1 = 300 kΩ. - - - With offset R1 = ∞ Ω: (a) R2 = 3 kΩ; (b) R2 = 10 kΩ; (c) R2 = 300 kΩ. Fig. 19. Frequency stability of the VCO as a function of ambient temperature 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 20 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 25 25 25 f f f (%) 20 (%) 20 VCC = 6 V 5V 15 10 15 10 5 5 0 0 0 -5 -5 -5 -10 -10 -10 -15 -15 -15 -20 -20 -20 0 50 100 150 Tamb (°C) (a) -25 -50 0 5V 6V 6V 5 -25 -50 VCC = 3 V 15 5V 10 3V (%) 20 VCC = 3 V 50 -25 -50 100 150 Tamb (°C) (b) 0 50 (c) 100 150 Tamb (°C) aaa-020362 To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF. ___ With offset; R1 = ∞ Ω: (a) R2 = 3 kΩ; (b) R2 = 10 kΩ; (c) R2 = 300 kΩ. Fig. 20. Frequency stability of the VCO as a function of ambient temperature 30 80 fVCO (MHz) VCC = 6 V 25 4.5 V fVCO (kHz) VCC = 6 V 60 20 4.5 V 3V 15 40 3V 10 20 5 0 0 2 (a) 4 6 VVCO_IN (V) 0 0 2 (b) 4 6 VVCO_IN (V) aaa-020363 To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF. (a) R1 = 3 kΩ; C1 = 40 pF (b) R1 = 3 kΩ; C1 = 100 nF Fig. 21. Graphs showing VCO frequency as a function of the VCO input voltage 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 21 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 1000 500 VCC = 6 V fVCO (kHz) 800 4.5 V fVCO (Hz) VCC = 6 V 400 4.5 V 600 300 3V 3V 400 200 200 100 0 0 2 4 6 VVCO_IN (V) (a) 0 0 2 (b) 4 6 VVCO_IN (V) aaa-020364 To obtain optimum temperature stability, C1 must be as small as possible but larger than 100 pF. (a) R1 = 300 kΩ; C1 = 40 pF (b) R1 = 300 kΩ; C1 = 100 nF Fig. 22. Graphs showing VCO frequency as a function of the VCO input voltage 10 VCC = 3 V fVCO (%) C1 = 1 µF 5 f 4.5 V f2 6V f0 f0' f1 VCC = 4.5 V C1 = 100 pF 0 V 6V V 4.5 V 0 min 1/2 VCC max C1 = 40 pF VVCO_IN aaa-020365 ΔV = 0.5 V over the VCC range. -5 10 102 R1 (kΩ) 103 R2 = ∞ Ω; ΔV = 0.5 V Fig. 23. Definition of VCO frequency linearity Product data sheet 1 aaa-020367 linearity = 74HC_HCT4046A 3V Fig. 24. Frequency linearity as a function of R1, C1 All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 22 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO aaa-020368 106 aaa-020369 106 PR1 (µW) PR2 (µW) 105 105 104 104 VCC = VCC = 6V 4.5 V 103 102 6V 3V 1 10 102 R1 (kΩ) 4.5 V 103 102 103 R2 = ∞ Ω; CL = 50 pF; VVCO_IN = 0.5VCC; Tamb = 25 °C ___ C1 = 40 pF; - - - C1 = 1 μF 3V 1 10 102 R2 (kΩ) 103 R1 = ∞ Ω; CL = 50 pF; VVCO_IN = GND; Tamb = 25 °C ___ C1 = 40 pF; - - - C1 = 1 μF Fig. 25. Power dissipation as a function of R1 Fig. 26. Power dissipation as a function of R2 aaa-020370 103 PDEM (µW) 102 VCC = 6V 4.5 V 3V 10 102 10 RS (kΩ) 103 R1 = R2 = ∞ Ω; VVCO_IN = 0.5VCC; Tamb = 25 °C Fig. 27. Typical power dissipation of demodulator sections as a function of Rs 13. Application information This information is a guide for the approximation of values of external components to be used with the 74HC4046A; 74HCT4046A in a phase-locked-loop system. References should be made to Fig. 31, Fig. 32 and Fig. 33 as indicated in Table 10. Values of the selected components should be within the ranges shown in Table 9. Table 9. Survey of components Component Value R1 between 3 kΩ and 300 kΩ R2 between 3 kΩ and 300 kΩ R1 + R2 parallel value > 2.7 kΩ C1 > 40 pF 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 23 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO Table 10. Design considerations for VCO section Subject Phase Design consideration comparator VCO frequency without extra offset VCO frequency with extra offset PLL conditions no signal at pin SIG_IN PC1, PC2 or PC3 VCO frequency characteristic. With R2 = ∞ Ω and R1 within the range 3 kΩ < R1 < 300 kΩ, the characteristics of the VCO operation is as shown in Fig. 28a. (Due to R1, C1 time constant a small offset remains when R2 = ∞ Ω). PC1 Selection of R1 and C1. Given f0, determine the values of R1 and C1 using Fig. 31. PC2 or PC3 Given fmax and f0, determine the values of R1 and C1 using Fig. 31; use Fig. 33 to obtain 2fL and then use it to calculate fmin. PC1, PC2 or PC3 VCO frequency characteristic. With R1 and R2 within the ranges 3 kΩ < R1 < 300 kΩ and 3 kΩ < R2 < 300 kΩ. The characteristics of the VCO operation are as shown in Fig. 28b. PC1, PC2 or PC3 Selection of R1, R2 and C1. Given f0 and fL determine the value of product R1C1 by using Fig. 33. Calculate foff from the equation foff = f0 - 1.6fL. Obtain the values of C1 and R2 by using Fig. 32. Calculate the value of R1 from the value of C1 and the product R1C1. PC1 VCO adjusts to f0 with ΦDEM_OUT = 90° and VVCO_IN = 0.5VCC, see Fig. 7 PC2 VCO adjusts to f0 with ΦDEM_OUT = -360° and VVCO_IN = minimum, see Fig. 9 PC3 VCO adjusts to f0 with ΦDEM_OUT = -360° and VVCO_IN = minimum, see Fig. 11 fVCO fmax 2fL f0 fmin 0.9 V 1/2 VCC VCC -0.9 V due to R1, C1 VCC VCO_IN aaa-020371 a. Operating without offset; f0 = center frequency; 2fL = frequency lock range. fVCO fmax f0 2fL fmin foff due to R1, C1 due to R2, C1 0.9 V 1/2 VCC VCC -0.9 V VCC VCO_IN aaa-020372 b. Operating with offset; f0 = center frequency; 2fL = frequency lock range. Fig. 28. Frequency characteristic of VCO 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 24 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO Table 11. General design considerations Subject Phase comparator Design consideration PLL frequency capture range PC1, PC2 or PC3 Loop filter component selection, see Fig. 29 and Fig. 30 PLL locks on harmonics at center frequency PC1 or PC3 yes PC2 no Noise rejection at signal input PC1 high PC2 or PC3 low PC1 fr = 2fi; large ripple content at ΦDEM_OUT = 90° PC2 fr = fi; small ripple content at ΦDEM_OUT = 0° PC3 fr = fi; large ripple content at ΦDEM_OUT = 180° AC ripple content when PLL is locked F(jω) R3 input C2 -1/τ output ω (a) (b) (c) aaa-020446 R3 ≥ 500 Ω. A small capture range (2fc) is obtained if (a) (b) amplitude characteristics (c) pole-zero diagram Fig. 29. Simple loop filter for PLL without offset F(jω) R3 R4 input -1/τ2 output m C2 m= 1/τ3 (a) 1/τ2 -1/τ3 R4 R3 + R4 ω (b) (c) aaa-020447 R3 + R4 ≥ 500 Ω. (a) (b) amplitude characteristics (c) pole-zero diagram Fig. 30. Simple loop filter for PLL with offset 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 25 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO aaa-020448 108 fo R1 = 3 kΩ (Hz) 107 10 kΩ 106 VCC = 5V 4.5 V 150 kΩ 300 kΩ 6V 5V 4.5 V 3V 105 104 103 5V 4.5 V 3V 5V 4.5 V 3V 102 10 1 10 102 103 104 105 106 107 C1 (pF) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF. Interpolation for various values of R1 can be easily calculated because a constant R1C1 product produces almost the same VCO output frequency. R2 = ∞ Ω; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 °C. Fig. 31. Typical value of VCO center frequency (f0) as a function of C1 aaa-020449 108 foff R2 = 3 kΩ (Hz) 10 kΩ 107 106 VCC = 5V 4.5 V 150 kΩ 300 kΩ 6V 5V 4.5 V 3V 105 104 103 5V 4.5 V 5V 4.5 V 3V 102 10 1 10 102 103 104 105 106 107 C1 (pF) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF. Interpolation for various values of R2 can be easily calculated because a constant R2C1 product produces almost the same VCO output frequency. R1 = ∞ Ω; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 °C. Fig. 32. Typical value of frequency offset as a function of C1 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 26 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO aaa-020450 108 2fL (Hz) 107 106 VCC = 6 V 5V 4.5 V 3V 105 104 103 102 10 10-7 10-6 10-5 10-4 10-3 10-2 10-1 1 R1C1 (pF) VVCO_IN = 0.9 V to (VCC - 0.9) V; R2 = ∞ Ω. VCO gain: Fig. 33. Typical frequency lock range (2fL) as a function of the product R1C1 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 27 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 13.1. PLL design example The frequency synthesizer used in the design example shown in Fig. 34 has the following parameters: • • • • Output frequency: 2 MHz to 3 MHz Frequency steps: 100 kHz Settling time: 1 ms Overshoot: < 20 % The open loop gain is: where: • • • • Kp(s) = phase comparator gain Kf(s) = low-pass filter transfer gain Ko(s) = Kv/s VCO gain 1 Kn = ⁄n divider ratio The programmable counter ratio Kn can be found as follows: The values of R1, R2 and C1; R2 = 10 kΩ (adjustable) set the VCO. The values can be determined using the information in Table 10 and Table 11. With f0 = 2.5 MHz and fL = 500 kHz, the following values (VCC = 5.0 V) are given: • • • R1 = 10 kΩ R2 = 10 kΩ C1 = 500 pF The VCO gain is: The gain of the phase comparator is: The transfer gain of the filter is calculated as follows: Where: The characteristic equation is: It results in: 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 28 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO The natural frequency ωn is defined as: and the damping value (ζ) given as: In Fig. 35, the output frequency response to a step of input frequency is shown. The overshoot and settling time percentages are now used to determine ωn. Fig. 35 shows that the damping ratio ζ = 0.45 produces an overshoot of less than 20 % and settle to within 5 % at ωnt = 5. The required settling time is 1 ms. It results in: Rewriting the equation for natural frequency results in: The maximum overshoot occurs at Nmax: When C2 = 470 nF, then: R3 can be calculated: 74HC4046A; 74HCT4046A OSCILLATOR 74HCU04 Kp 100 kHz DIVIDE - BY 10 74HC191 14 3 PHASE COMPARATOR PC2 Kf 13 R3 9 4 VCO 11 R4 C2 Kn 1 MHz Ko 12 R1 6 7 fout 5 R2 C1 PROGRAMMABLE DIVIDER 4 x 74HC161 aaa-020451 Fig. 34. Frequency synthesizer 1.6 ωe (t) ωe/ωn 1.2 aaa-020452 ζ = 0.3 0.5 0.707 1.0 ζ = 5.0 Θe (t) Θe/ωn -0.2 ζ = 2.0 0.8 0.2 0.4 0 -0.6 0.6 0 2 4 6 ωn (t) 8 1.0 Fig. 35. Type 2, second order frequency step response 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 29 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO aaa-020453 3.1 Frequency(1) (MHz) 3.0 N = 30 N stepped from 29 to 30 2.9 step input 2.1 N stepped from 21 to 20 2.0 1.9 0 0.5 1 1.5 2 2.5 time (ms) The output frequency is proportional to the VCO control voltage. As a result, the PLL frequency response can be observed with an oscilloscope by monitoring pin VCO_IN of the VCO. The average frequency response, as calculated by the Laplace method, is found experimentally by smoothing this voltage at pin VCO_IN using a simple RC filter. The filter has a long time constant when compared with the phase detector sampling rate, but short when compared with the PLL response time. Fig. 36. Frequency compared to the time response 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 30 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 14. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 37. Package outline SOT109-1 (SO16) 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 31 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig. 38. Package outline SOT338-1 (SSOP16) 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 32 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 39. Package outline SOT403-1 (TSSOP16) 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 33 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 15. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductors DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model PLL Phase-Locked Loop VCO Voltage Controlled Oscillator 16. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT4046A v.4 20190806 Product data sheet - 74HC_HCT4046A v.3 Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Typo corrected in Fig. 21 and Fig. 22. 74HC_HCT4046A v.3 20160608 Modifications: • • Product data sheet - 74HC_HCT4046A_CNV v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 74HC_HCT4046A_CNV v.2 19971125 Product specification - 74HC_HCT4046A v.1 74HC_HCT4046A v.1 Objective specification - - 74HC_HCT4046A Product data sheet 19930901 All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 34 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO 17. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 35 / 36 74HC4046A; 74HCT4046A Nexperia Phase-locked loop with VCO Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................2 5. Block diagram...............................................................2 6. Functional diagram.......................................................3 7. Pinning information......................................................4 7.1. Pinning.........................................................................4 7.2. Pin description............................................................. 4 8. Functional description................................................. 5 8.1. VCO............................................................................. 5 8.2. Phase comparators......................................................5 8.2.1. Phase Comparator 1 (PC1)...................................... 5 8.2.2. Phase Comparator 2 (PC2)...................................... 7 8.2.3. Phase Comparator 3 (PC3)...................................... 8 9. Limiting values........................................................... 10 10. Recommended operating conditions......................10 11. Static characteristics................................................11 11.1. Static characteristics 74HC4046A............................11 11.2. Static characteristics 74HCT4046A......................... 13 11.3. Graphs..................................................................... 15 12. Dynamic characteristics.......................................... 16 12.1. Dynamic characteristics 74HC4046A...................... 16 12.2. Dynamic characteristics 74HCT4046A.................... 18 12.3. Waveforms and graphs............................................19 13. Application information........................................... 23 13.1. PLL design example................................................ 28 14. Package outline........................................................ 31 15. Abbreviations............................................................ 34 16. Revision history........................................................34 17. Legal information......................................................35 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 6 August 2019 74HC_HCT4046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 August 2019 © Nexperia B.V. 2019. All rights reserved 36 / 36