SIT2001BI-S2-33E-54.000000G 数据手册
SiT2001B
Single-Chip, SOT23 Oscillator
Features
Applications
Any frequency between 1 MHz and 110 MHz accurate
to 6 decimal places
Operating temperature from -40°C to 85°C.
Refer to SiT2018 for -40°C to 85°C option and
SiT2020 for -55°C to 125°C option
Excellent total frequency stability as low as ±20 ppm
Low power consumption of 3.5 mA typical
Fast start-up time of 5 ms
LVCMOS/HCMOS compatible output
5-pin SOT23-5: 2.9 mm x 2.8mm
Pb-free, RoHS and REACH compliant
For AEC-Q100 SOT23 Oscillators, refer to
SiT2024 and SiT2025
Industrial, medical, automotive, avionics and other
high temperature applications
Industrial sensors, PLC, motor servo, outdoor
networking equipment, medical video cam, asset
tracking systems, etc.
Electrical Specifications
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and nominal supply voltage.
Table 1. Electrical Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Range
Output Frequency Range
f
1
–
110
MHz
Frequency Stability and Aging
Frequency Stability
F_stab
-20
–
+20
ppm
-25
–
+25
ppm
–
+50
ppm
-50
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C,
and variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Operating Temperature Range
Operating Temperature
Range (ambient)
T_use
-20
–
+70
°C
Extended Commercial
-40
–
+85
°C
Industrial
Supply Voltage and Current Consumption
Supply Voltage
Current Consumption
OE Disable Current
Standby Current
Vdd
Idd
I_od
I_std
1.62
1.8
1.98
V
2.25
2.5
2.75
V
2.52
2.8
3.08
V
2.7
3.0
3.3
V
2.97
3.3
3.63
V
2.25
–
3.63
V
–
3.8
4.5
mA
No load condition, f = 20 MHz, Vdd = 2.8V, 3.0V or 3.3V
–
3.7
4.2
mA
No load condition, f = 20 MHz, Vdd = 2.5V
–
3.5
4.1
mA
No load condition, f = 20 MHz, Vdd = 1.8V
–
–
4.3
mA
Vdd = 2.5V to 3.3V, OE = Low, Output in high Z state.
–
–
4.1
mA
Vdd = 1.8V, OE = Low, Output in high Z state.
–
2.6
4.3
A
Vdd = 2.8V to 3.3V, ST = Low, Output is weakly pulled down
–
1.4
2.5
A
Vdd = 2.5V, ST = Low, Output is weakly pulled down
–
0.6
1.3
A
Vdd = 1.8V, ST = Low, Output is weakly pulled down
LVCMOS Output Characteristics
Duty Cycle
Rise/Fall Time
DC
45
–
55
%
Tr, Tf
–
1.0
2.0
ns
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
–
1.3
2.5
ns
Vdd =1.8V, 20% - 80%
Vdd = 2.25V - 3.63V, 20% - 80%
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V or 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V or 2.5V)
IOL = 2 mA (Vdd = 1.8V)
–
–
2.0
ns
Output High Voltage
VOH
90%
–
–
Vdd
Output Low Voltage
VOL
–
–
10%
Vdd
Rev. 1.02
April 19, 2018
All Vdds
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SiT2001B Single-Chip, SOT23 Oscillator
Table 1. Electrical Characteristics (continued)
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Input Characteristics
Input High Voltage
VIH
70%
–
–
Vdd
Pin 3, OE or ST
Input Low Voltage
VIL
–
–
30%
Vdd
Pin 3, OE or ST
Input Pull-up impedance
Z_in
50
87
150
k
Pin 3, OE logic high or logic low, or ST logic high
2
–
–
M
Pin 3, ST logic low
Startup and Resume Timing
Startup Time
Enable/Disable Time
Resume Time
T_start
–
–
5
ms
T_oe
–
–
130
ns
Measured from the time Vdd reaches its rated minimum value
f = 110 MHz.
For other frequencies, T_oe = 100 ns + 3 * clock periods
T_resume
–
–
5
ms
Measured from the time ST pin crosses 50% threshold
Jitter
RMS Period Jitter
T_jitt
Peak-to-peak Period Jitter
T_pk
RMS Phase Jitter (random)
T_phj
–
1.8
3
ps
f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
–
1.8
3
ps
f = 75 MHz, Vdd = 1.8V
–
12
20
ps
f = 75 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
–
14
25
ps
f = 75 MHz, Vdd = 1.8V
–
0.5
0.9
ps
f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
–
1.3
2
ps
f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz
Table 2. Pin Description
Pin
Symbol
1
GND
Power
2
NC
No Connect
Top View
Functionality
OE /
/ NC
NC
GND
Electrical ground
No connect
[1]
Output Enable
H : specified frequency output
L: output is high impedance. Only output driver is disabled.
[1]
H or Open : specified frequency output
3
OE/ ST
̅ ̅ ̅ /NC
Standby
L: output is low (weak pull down). Device goes to sleep mode.
Supply current reduces to I_std.
[1]
No Connect
Any voltage between 0 and Vdd or Open :
Specified frequency output. Pin 3 has no function.
[2]
4
VDD
Power
Power supply voltage
5
OUT
Output
Oscillator output
VDD
OUT
Figure 1. Pin Assignments
Notes:
1. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If pin 3 needs to be left floating, use the NC option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Rev. 1.02
Page 2 of 16
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SiT2001B Single-Chip, SOT23 Oscillator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specificat ions, not at absolute maximum ratings.
Parameter
Min.
Max.
Unit
Storage Temperature
-65
150
°C
Vdd
-0.5
4
V
Electrostatic Discharge
–
2000
V
Soldering Temperature (follow standard Pb free
soldering guidelines)
–
260
°C
–
150
°C
Junction Temperature
[3]
Note:
3. Exceeding this temperature for extended period of time may damage the device.
[4]
Table 4. Thermal Consideration
Package
JA, 4 Layer Board
JC, Bottom
(°C/W)
(°C/W)
SOT23-5
421
175
Note:
4. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table.
[5]
Table 5. Maximum Operating Junction Temperature
Max Operating Temperature (ambient)
Maximum Operating Junction Temperature
70°C
80°C
85°C
95°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Condition/Test Method
Mechanical Shock
MIL-STD-883F, Method 2002
Mechanical Vibration
MIL-STD-883F, Method 2007
Temperature Cycle
JESD22, Method A104
Solderability
MIL-STD-883F, Method 2003
Moisture Sensitivity Level
MSL1 @ 260°C
Rev. 1.02
Page 3 of 16
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SiT2001B Single-Chip, SOT23 Oscillator
Test Circuit and Waveform[6]
Vout
Test
Point
Vdd
tr
15 pF
(including probe
and fixture
capacitance)
80% Vdd
4
5
1
2
tf
0.1µF
3
50%
Power
Supply
20% Vdd
High Pulse
(TH)
Period
Vdd
1kΩ
Low Pulse
(TL)
OE/ST Function
Figure 2. Test Circuit
Figure 3. Output Waveform
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagrams
90% Vdd
Vdd
Vdd
50% Vdd
[7]
T_start
Pin 4 Voltage
No Glitch
during start up
T_resume
ST Voltage
CLK Output
CLK Output
HZ
HZ
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 6. Standby Resume Timing ( ST Mode Only)
Figure 4. Startup Timing (OE/ ST Mode)
Vdd
Vdd
50% Vdd
OE Voltage
50% Vdd
T_oe
OE Voltage
T_oe
CLK Output
CLK Output
HZ
HZ
T_oe: Time to put the output in High Z mode
T_oe: Time to re-enable the clock output
Figure 7. OE Disable Timing (OE Mode Only)
Figure 5. OE Enable Timing (OE Mode Only)
Note:
7. SiT2001 has “no runt” pulses and “no glitch” output during startup or resume.
Rev. 1.02
Page 4 of 16
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SiT2001B Single-Chip, SOT23 Oscillator
Performance Plots[8]
1.8
2.5
2.8
3.0
3.3
6.0
Frequency (ppm)
5.5
Idd (mA)
5.0
4.5
4.0
3.5
3.0
10
20
40
60
70
80
100
110
Frequency (MHz)
Temperature (°C)
Figure 8. Idd vs Frequency
1.8
2.5
2.8
3.0
Figure 9. Frequency vs Temperature
1.8
3.3
2.5
2.8
3.0
3.3
55
RMS period jitter (ps)
54
53
Duty cycle (%)
52
51
50
49
48
47
46
0
10
30
40
70
45
90
0
Frequency (MHz)
20
30
40
50
60
70
80
90
100
110
Frequency (MHz)
Figure 11. Duty Cycle vs Frequency
Fall time (ns)
Rise time (ns)
Figure 10. RMS Period Jitter vs Frequency
Temperature (°C)
Temperature (°C)
Figure 12. 20%-80% Rise Time vs Temperature
Rev. 1.02
10
Figure 13. 20%-80% Fall Time vs Temperature
Page 5 of 16
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SiT2001B Single-Chip, SOT23 Oscillator
IPJ (ps)
IPJ (ps)
Performance Plots[8]
10
30
50
70
90
110
10
30
50
70
90
110
Frequency (MHz)
Frequency (MHz)
Figure 14. RMS Integrated Phase Jitter Random
[9]
(12 kHz to 20 MHz) vs Frequency
Figure 15. RMS Integrated Phase Jitter Random
[9]
(900 kHz to 20 MHz) vs Frequency
Notes:
8. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
9. Phase noise plots are measured with Agilent E5052B signal source analyzer. Integration range is up to 5 MHz for carrier frequ encies below 40 MHz.
Rev. 1.02
Page 6 of 16
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SiT2001B Single-Chip, SOT23 Oscillator
Programmable Drive Strength
The SiT2001 includes a programmable drive strength
feature to provide a simple, flexible tool to optimize the
clock rise/fall time for specific applications. Benefits from
the programmable drive strength feature are:
Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time.
Improves the downstream clock receiver’s (RX) jitter by
decreasing (speeding up) the clock rise/fall time.
Ability to drive large capacitive loads while maintaining
full swing with sharp edge rates.
For more detailed information about rise/fall time control
and drive strength selection, see the SiTime Application
Notes section.
The SiT2001 can support up to 60 pF in maximum capacitive
loads with drive strength settings. Refer to the Rise/Tall
Time Tables (Table 7 to 11) to determine the proper drive
strength for the desired combination of output load vs.
rise/fall time.
SiT2001 Drive Strength Selection
Tables 7 through 11 define the rise/fall time for a given
capacitive load and supply voltage.
1. Select the table that matches the SiT2001 nominal
supply voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V).
2. Select the capacitive load column that matches the
application requirement (5 pF to 60 pF)
3. Under the capacitive load column, select the
desired rise/fall times.
4. The left-most column represents the part number
code for the corresponding drive strength.
5. Add the drive strength code to the part number for
ordering purposes.
EMI Reduction by Slowing Rise/Fall Time
Figure 16 shows the harmonic power reduction as the
rise/fall times are increased (slowed down). The rise/fall
times are expressed as a ratio of the clock period. For the
ratio of 0.05, the signal is very close to a square wave. For
the ratio of 0.45, the rise/fall times are very close to neartriangular waveform. These results, for example, show that
th
the 11 clock harmonic can be reduced by 35 dB if the
rise/fall edge is increased from 5% of the period to 45% of
the period.
trise=0.05
trise=0.1
trise=0.15
trise=0.2
trise=0.25
trise=0.3
trise=0.35
trise=0.4
trise=0.45
10
Harmonic amplitude (dB)
0
-10
-20
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables 7
through 11, the maximum frequency the oscillator can
operate with guaranteed full swing of the output voltage
over temperature can be calculated as the following:
5 x Trf_20/80
where Trf_20/80 is the typical value for 20%-80% rise/fall
time.
-30
Example 1
-40
Calculate fMAX for the following condition:
-50
-60
-70
-80
1
Max Frequency =
1
3
5
7
9
11
Harmonic number
Figure 16. Harmonic EMI reduction as a Function
of Slower Rise/Fall Time
Vdd = 1.8V (Table 7)
Capacitive Load: 30 pF
Desired Tr/f time = 3 ns
(rise/fall time part number code = E)
Part number for the above example:
Jitter Reduction with Faster Rise/Fall Time
SiT2001BIES2-18E-66.666660
Power supply noise can be a source of jitter for the downstream chipset. One way to reduce this jitter is to speed up
the rise/fall time of the input clock. Some chipsets may also
require faster rise/fall time in order to reduce their sensitivity
to this type of jitter. Refer to the Rise/Fall Time Tables
(Table 7 to Table 11) to determine the proper drive strength.
Drive strength code is inserted here. Default setting is “-”
High Output Load Capability
The rise/fall time of the input clock varies as a function of
the actual capacitive load the clock drives. At any given
drive strength, the rise/fall time becomes slower as the
output load increases. As an example, for a 3.3V SiT2001
device with default drive strength setting, the typical
rise/fall time is 1 ns for 15 pF output load. The typical
rise/fall time slows down to 2.6 ns when the output load
increases to 45 pF. One can choose to speed up the
rise/fall time to 1.83 ns by then increasing the drive
strength setting on the SiT2001.
Rev. 1.02
Page 7 of 16
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SiT2001B Single-Chip, SOT23 Oscillator
Rise/Fall Time (20% to 80%) vs CLOAD Tables
Table 8. Vdd = 2.5V Rise/Fall Times
for Specific CLOAD
Table 7. Vdd = 1.8V Rise/Fall Times
for Specific CLOAD
Drive Strength \ CLOAD
L
A
R
B
T
E
U
F or "‐": default
Rise/Fall Time Typ (ns)
5 pF
15 pF
30 pF
45 pF
60 pF
Drive Strength \ CLOAD
6.16
3.19
2.11
1.65
0.93
0.78
0.70
0.65
31.27
16.01
10.77
8.18
4.66
4.09
3.68
3.35
39.91
21.52
14.47
11.08
6.48
5.74
5.09
4.56
L
A
R
B
T
E or "‐": default
U
F
11.61
6.35
4.31
3.23
1.91
1.66
1.48
1.30
22.00
11.00
7.65
5.79
3.32
2.94
2.64
2.40
Table 9. Vdd = 2.8V Rise/Fall Times
for Specific CLOAD
4.13
2.11
1.45
1.09
0.62
0.54
0.43
0.34
8.25
4.27
2.81
2.20
1.28
1.00
0.96
0.88
12.82
7.64
5.16
3.88
2.27
2.01
1.81
1.64
45 pF
60 pF
21.45
11.20
7.65
5.86
3.51
3.10
2.79
2.54
27.79
14.49
9.88
7.57
4.45
4.01
3.65
3.32
Table 10. Vdd = 3.0V Rise/Fall Times
for Specific CLOAD
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
Rise/Fall Time Typ (ns)
5 pF
15 pF
30 pF
Rise/Fall Time Typ (ns)
L
A
R
B
T
5 pF
3.77
1.94
1.29
0.97
0.55
15 pF
7.54
3.90
2.57
2.00
1.12
30 pF
12.28
7.03
4.72
3.54
2.08
45 pF
19.57
10.24
7.01
5.43
3.22
60 pF
25.27
13.34
9.06
6.93
4.08
Drive Strength \ CLOAD
L
A
R
B
T or "‐": default
5 pF
3.60
1.84
1.22
0.89
0.51
15 pF
7.21
3.71
2.46
1.92
1.00
30 pF
11.97
6.72
4.54
3.39
1.97
45 pF
18.74
9.86
6.76
5.20
3.07
60 pF
24.30
12.68
8.62
6.64
3.90
E or "‐": default
U
F
0.44
0.34
0.29
1.00
0.88
0.81
1.83
1.64
1.48
2.82
2.52
2.29
3.67
3.30
2.99
E
U
F
0.38
0.30
0.27
0.92
0.83
0.76
1.72
1.55
1.39
2.71
2.40
2.16
3.51
3.13
2.85
Table 11. Vdd = 3.3V Rise/Fall Times
for Specific CLOAD
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
L
A
R
B
5 pF
3.39
1.74
1.16
0.81
15 pF
6.88
3.50
2.33
1.82
30 pF
11.63
6.38
4.29
3.22
45 pF
17.56
8.98
6.04
4.52
60 pF
23.59
12.19
8.34
6.33
T or "‐": default
E
U
F
0.46
0.33
0.28
0.25
1.00
0.87
0.79
0.72
1.86
1.64
1.46
1.31
2.60
2.30
2.05
1.83
3.84
3.35
2.93
2.61
Rev. 1.02
Page 8 of 16
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SiT2001B Single-Chip, SOT23 Oscillator
Pin 1 Configuration Options (OE, ST
̅ ̅ ̅ , or NC)
Output on Startup and Resume
Pin 3 of the SiT2001 can be factory-programmed to support
three modes: Output Enable (OE), standby ( ST ) or
No Connect (NC).
The SiT2001 comes with gated output. Its clock output is
accurate to the rated frequency stability within the first pulse
from initial device startup or resume from the standby mode.
Output Enable (OE) Mode
In addition, the SiT2001 supports “no runt” pulses, and “no
glitch” output during startup or resume as shown in the
waveform captures in Figure 17 and Figure 18.
In the OE mode, applying logic Low to the OE pin only
disables the output driver and puts it in Hi-Z mode. The core
of the device continues to operate normally. Power
consumption is reduced due to the inactivity of the output.
When the OE pin is pulled High, the output is typically
enabled in