SLG59M1657V

SLG59M1657V An Ultra-small 3 mm2, 8.4 mΩ, 4 A, 125°C-Rated Internally-protected Integrated Power Switch General Description Pin Configuration VDD 1 ON 2 D 3 D 4 Using a proprietary MOSFET design, the SLG59M1657V achieves a stable 8.4 mΩ RDSON across a wide input voltage range. In addition, the SLG59M1657V’s package also exhibits low thermal resistance for high-current operation using Silego’s proprietary CuFET technology. Fully specified over the -40 °C to 125 °C temperature range, the SLG59M1657V is packaged in a space-efficient, low thermal resistance, RoHS-compliant 1.5 mm x 2.0 mm STDFN package. Features • 1.5 x 2.0 mm FC-TDFN 8L package (2 fused pins for drain and 2 fused pins for source) • Logic level ON pin capable of supporting 0.9 V CMOS Logic • User selectable ramp rate with external capacitor • 8.4 mΩ RDSON while supporting 4 A • Two Over Current Protection Modes • Short Circuit Current Limit • Active Current Limit • Over Temperature Protection • Pb-Free / Halogen-Free / RoHS compliant • Operating Temperature: -40 °C to 125°C • Operating Voltage: 2.5 V to 5.5 V SLG59M1657V The SLG59M1657V is a high performance 8.4 mΩ, 4 A single-channel nFET integrated power switch which can operate with a 2.5 V to 5.5 V VDD supply to switch power rails from as low as 0.9 V up to the supply voltage. The SLG59M1657V incorporates two-level overload current protection, thermal shutdown protection, and in-rush current control which can easily be adjusted by a small external capacitor. 8 GND 7 CAP 6 S 5 S 8-pin FC-TDFN (Top View) Applications • Notebook Power Rail Switching • Tablet Power Rail Switching • Smartphone Power Rail Switching Block Diagram 4 A @ 8.4 mΩ D CIN VDD +2.5 V to 5.5 V CAP CSLEW 4 nF S CLOAD Charge Pump Linear Ramp Control Over Current and Over Temperature Protection ON CMOS Input 0.85 to 3.6 V GND Silego Technology, Inc. 000-0059M1657-100 Rev 1.00 Revised February 23, 2017 SLG59M1657V Pin Description Pin # Pin Name Type Pin Description 1 VDD PWR With an internal 1.8 V UVLO threshold, VDD supplies the power for the operation of the power switch and internal control circuitry. Bypass the VDD pin to GND with a 0.1 µF (or larger) capacitor. 2 ON Input A low-to-high transition on this pin initiates the operation of the SLG59M1657V’s state machine. ON is a CMOS input with VIL < 0.25 V and VIH > 0.85 V thresholds. While there is an internal pull-down circuit to GND (~4 MΩ), connect this pin directly to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller. Do not allow this pin to be open-circuited. 3, 4 D MOSFET Drain terminal connection of the n-channel MOSFET (2 pins fused for VD). Connect at least a low-ESR 0.1 µF capacitor from this pin to ground. Capacitors used at VD should be rated at 10 V or higher. 5, 6 S MOSFET Source terminal connection of the n-channel MOSFET (2 pins fused for VS). Connect a low-ESR capacitor from this pin to ground and consult the Electrical Characteristics table for recommended CLOAD range. Capacitors used at VS should be rated at 10 V or higher. 7 CAP Input A low-ESR, stable dielectric, ceramic surface-mount capacitor connected from CAP pin to GND sets the VS slew rate and overall turn-on time of the SLG59M1657V. For best performance CSLEW value should be ≥ 1.5 nF and voltage level should be rated at 10 V or higher. 8 GND GND Ground connection. Connect this pin to system analog or power ground plane. Ordering Information Part Number Type Production Flow SLG59M1657V FC-TDFN 8L Extended Industrial, -40 °C to 125 °C SLG59M1657VTR FC-TDFN 8L (Tape and Reel) Extended Industrial, -40 °C to 125 °C 000-0059M1657-100 Page 2 of 13 SLG59M1657V Absolute Maximum Ratings Parameter VDD Description Conditions Power Supply Min. Typ. Max. Unit -- -- 7 V VD to GND Power Switch Input Voltage to GND -0.3 -- 7 V VS to GND Power Switch Output Voltage to GND -0.3 -- VD V -0.3 -- 7 V ON and CAP to ON and CAP Pin Voltages to GND GND TO Operating Temperature -40 -- 125 °C TS Storage Temperature -65 -- 150 °C TA Rated Operating Temperature -40 -- 125 °C -- V -- V ESDHBM ESDCDM MSL θJA WDIS ESD Protection Human Body Model 2000 -- ESD Protection Charged Device Model 1000 -- Moisture Sensitivity Level Thermal Resistance 1 1.5 x 2 mm, 8L TDFN; Determined using 1 in2, 1 oz. copper pads under each VD and VS terminals and FR4 pcb material Package Power Dissipation MOSFET IDS Max Continuous Switch Current MOSFET IDSPK Peak Current from Drain to Source For no more than 1 ms with 1% duty cycle -- 69 -- °C/W -- -- 1 W -- -- 4 A -- -- 4.5 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics TA = -40 to 125 °C (unless otherwise stated) Parameter VDD VDD_UVLO IDD RDSON VD Description Conditions Min. Typ. Max. Unit Power Supply Voltage -40 to 125°C 2.5 -- 5.5 V VDD Undervoltage Lockout Threshold VDD ↑ -- 1.8 -- V when OFF; TA = 70 °C; VS = 0 V; VD = VDD = 5.5 V -- -- 1 μA when OFF; TA = 85 °C; VS = 0 V; VD = VDD = 5.5 V -- -- 1 μA when OFF; TA = 125 °C; VS = 0 V; VD = VDD = 5.5 V -- -- 1.5 μA when ON, no Load -- 70 120 μA TA 25°C @ 100 mA -- 8.4 10 mΩ TA 85°C @ 100 mA -- 10 12 mΩ TA 125°C @ 100 mA -- 12 14.4 mΩ 0.9 -- VDD V Power Supply Current ON Resistance Drain Voltage 000-0059M1657-100 Page 3 of 13 SLG59M1657V Electrical Characteristics (continued) TA = -40 to 125 °C (unless otherwise stated) Parameter Min. Typ. Max. Unit VD = VDD = 5.5 V; VS = 0 V; ON = 0 V; TA = 70°C -- -- 1 μA VD = VDD = 5.5 V; VS = 0 V; ON = 0 V; TA = 85°C -- -- 1 μA VD = VDD = 5.5 V; VS = 0 V; ON = 0 V; TA = 125°C -- -- 20 μA Slew Rate CSLEW = 4 nF, VDD = VD = 5 V, CLOAD = 10 μF, RLOAD = 20 Ω -- 3 -- V/ms ON pin Delay Time 50% ON to Ramp Begin -- 200 -- μs OFF Delay Time 50% ON to VS Fall Start, VDD = VD = 5 V, no CLOAD, RLOAD = 20 Ω -- 22 -- μs TFALL VS Fall Time 90% VS to 10% VS, VDD = VD = 5 V, no CLOAD, RLOAD = 20 Ω -- 10 -- μs CLOAD Output Capacitive Load to GND -- -- 500 μF IFET_OFF VS(SR) TON_Delay TOFF_Delay Description Conditions MOSFET OFF Leakage Current ON_VIH High Input Voltage on ON pin 0.85 -- VDD V ON_VIL Low Input Voltage on ON pin -0.3 0 0.25 V Active Current Limit (IACL) MOSFET will automatically limit current when VS > 250 mV -- 6.0 -- A Short Circuit Current Limit (ISCL) MOSFET will automatically limit current when VS < 250 mV -- 0.5 -- A Thermal shutoff turn-on temperature -- 150 -- °C THERMOFF Thermal shutoff turn-off temperature -- 130 -- °C THERMTIME Thermal shutoff time -- -- 1 ms ILIMIT THERMON TTotal_ON, TON_Delay and Slew Rate Measurement ON 50% ON 50% ON TOFF_Delay 90% VS VS 90% VS TON_Delay 10% VS 10% VS VS(SR) (V/ms) TFALL TTotal_ON Note: Rise and Fall times of the ON signal are 100 ns 000-0059M1657-100 Page 4 of 13 SLG59M1657V Typical Performance Characteristics RDSON vs. VDD, and Temperature RDSON vs. VD and VDD 000-0059M1657-100 Page 5 of 13 SLG59M1657V VS(SR) vs. Temperature, VD, VDD, and CSLEW TTotal_ON vs. CSLEW, VD, VDD, and Temperature 000-0059M1657-100 Page 6 of 13 SLG59M1657V Typical Operation Waveforms ON VS Figure 1. Typical Turn ON operation waveform for VDD = VD = 5 V, CSLEW = 4 nF, CLOAD = 10 µF, RLOAD = 20 Ω ON VS Figure 2. Typical Turn ON operation waveform for VDD = VD = 5 V, CSLEW = 12 nF, CLOAD = 10 µF, RLOAD = 20 Ω 000-0059M1657-100 Page 7 of 13 SLG59M1657V ON VS Figure 3. Typical Turn OFF operation waveform for VDD = VD = 5 V, CSLEW = 4 nF, no CLOAD, RLOAD = 20 Ω ON VS Figure 4. Typical Turn OFF operation waveform for VDD = VD = 5 V, CSLEW = 4 nF, CLOAD = 10 µF, RLOAD = 20 Ω 000-0059M1657-100 Page 8 of 13 SLG59M1657V SLG59M1657V Power-Up/Power-Down Sequence Considerations A nominal power-up sequence is to apply VDD first, followed by VD only after VDD is > 1 V, and finally toggling the ON pin LOW-to-HIGH after VD is at least 90% of its final value. A nominal power-down sequence is the power-up sequence in reverse order. It is important that the SLG59M1657V’s ON pin is toggled HIGH only after VDD and VD have reached their steady-state values; otherwise, the power switch will spend an undesirable amount of time in high-resistance mode while powering up, heating up, and possibly reaching its thermal shutdown before ever fully turning on. If VDD and VD are applied at the same time, a voltage glitch may appear on the output pin at VS. To prevent glitches at the output, it is recommended to connect a 10 μF capacitor from the VS pin to GND and to keep the VDD & VD ramp times less than 2 ms. The VS output follows a linear ramp when the power switch is turned on, provided that the VS slew time set by CSLEW is less than the RC time constant formed by the RDSON of the power switch and load capacitance CLOAD. SLG59M1657V Current Limiting Operation The SLG59M1657V has two types of current limiting triggered by the output VS pin voltage. 1. Standard Current Limiting Mode (with Thermal Shutdown Protection) When the VS pin voltage > 250 mV, the output current is initially limited to the Active Current Limit (IACL) specification listed in the Electrical Characteristics table. The ACL monitor’s response time is very fast and is triggered within a few microseconds to sudden (transient) changes in load current. When a load current overload is detected, the ACL monitor increases the FET resistance to keep the current from exceeding the power switch’s IACL threshold. However, if a load-current overload condition persists where the die temperature rises because of the increased FET resistance, the power switch’s internal Thermal Shutdown Protection circuit can be activated. If the die temperature exceeds the listed THERMON specification, the FET is shut OFF completely, thereby allowing the die to cool. When the die cools to the listed THERMOFF temperature threshold, the FET is allowed to turn back on. This process may repeat as long as the output current overload condition persists. 2. Short Circuit Current Limiting Mode (with Thermal Shutdown Protection) When the VS pin voltage < 250 mV (which is the case with a hard short, such as a solder bridge on the power rail), the power switch’s internal Short-circuit Current Limit (SCL) monitor limits the FET current to approximately 500 mA (the ISCL threshold). While the internal Thermal Shutdown Protection circuit remains enabled and since the ISCL threshold is much lower than the IACL threshold, thermal shutdown protection may become activated only at higher ambient temperatures. For more information on Silego GreenFET3 integrated power switch features, please visit our Application Notes page at our website and see App Note “AN-1068 GreenFET3 Integrated Power Switch Basics”. 000-0059M1657-100 Page 9 of 13 SLG59M1657V Package Top Marking System Definition Date Code + Revision Pin 1 Identifier XXA DDR LL Part Code + Assembly Site Lot Traceability XX - Part Code Field1 A - Assembly Site Code Field2 DD - Date Code Field1 R - Part Revision Code Field2 LL - Lot Traceability Field1 Note 1: Each character in code field can be alphanumeric A-Z and 0-9 Note 2: Character in code field can be alphabetic A-Z 000-0059M1657-100 Page 10 of 13 SLG59M1657V Package Drawing and Dimensions 8 Lead TDFN Package 1.5 x 2.0 mm (Fused Lead) JEDEC MO-252 Index Area (D/2 x E/2) L A1 1 e 8 b (8X) D S L1 L2 A2 A E Unit: mm Symbol A A1 A2 b D E 000-0059M1657-100 Min 0.70 0.005 0.15 0.15 1.95 1.45 Nom. 0.75 0.20 0.20 2.00 1.50 Max Symbol Min Nom. L 0.80 0.35 0.40 L1 0.060 0.515 0.565 0.135 0.185 L2 0.25 e 0.50 BSC 0.25 0.37 REF S 2.05 1.55 Max 0.45 0.615 0.235 Page 11 of 13 SLG59M1657V Tape and Reel Specifications Max Units Leader (min) Nominal Reel & Package # of Package Size Hub Size Length Type Pins per Reel per Box Pockets [mm] [mm] [mm] TDFN 8L FC Green 8 1.5 x 2.0 x 0.75 3000 3000 178 / 60 100 400 Trailer (min) Pockets Length [mm] Tape Width [mm] 100 400 8 Part Pitch [mm] 4 Carrier Tape Drawing and Dimensions Pocket BTM Pocket BTM Package Length Width Type TDFN 8L FC Green Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole Index Hole to Tape to Pocket Tape Width Edge Center A0 B0 K0 P0 P1 D0 E F W 1.68 2.18 0.9 4 4 1.5 1.75 3.5 8 P0 D0 Y E W F Section Y-Y Y P1 A0 B0 CL K0 Refer to EIA-481 specification Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.25 mm3 (nominal). More information can be found at www.jedec.org. 000-0059M1657-100 Page 12 of 13 SLG59M1657V Revision History Date Version 2/23/2017 1.00 000-0059M1657-100 Change Production Release Page 13 of 13