74HC173DB,112

74HC173; 74HCT173 Quad D-type flip-flop; positive-edge trigger; 3-state Rev. 4 — 25 January 2021 Product data sheet 1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • Complies with JEDEC standard no. 7A Input levels: • For 74HC173: CMOS level • For 74HCT173: TTL level Gated input enable for hold (do nothing) mode Gated output enable control mode Edge-triggered D-type register Asynchronous master reset ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package 74HC173D Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT173D 74HC173PW 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state 4. Functional diagram 7 CP 14 D0 13 D1 12 D2 Q0 3 Q1 4 FF1 to FF4 11 D3 Q2 5 9 Q3 6 10 & C1 7 14 9 E1 10 E2 15 MR 1 OE1 D0 13 12 D1 D2 & 2 15 D3 EN R 9 E1 10 E2 7 CP 1 OE1 13 4 2 OE2 MR Q0 Q1 Q2 Q3 12 5 11 6 2 OE2 14 15 3 4 5 6 3 1D aaa-024784 aaa-024783 Fig. 1. 1 11 Functional diagram Fig. 2. aaa-024785 Logic symbol D0 Fig. 3. D1 IEC logic symbol D2 D3 E1 E2 D CP FF Q 1 D CP Q RD FF Q 2 D CP Q RD FF Q 3 D CP Q RD FF Q 4 CP Q RD MR OE1 OE2 Q0 Q1 Q2 Q3 aaa-024786 Fig. 4. Logic diagram 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 2 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state 5. Pinning information 5.1. Pinning 74HC173 74HCT173 OE1 1 16 VCC OE2 2 15 MR Q0 3 14 D0 Q1 4 13 D1 Q2 5 12 D2 Q3 6 11 D3 CP 7 10 E2 GND 8 9 E1 74HC173 74HCT173 OE1 1 16 VCC 15 MR OE2 2 Q0 3 14 D0 Q1 4 13 D1 Q2 5 12 D2 Q3 6 11 D3 CP 7 10 E2 GND 8 9 E1 aaa-024787 Fig. 5. aaa-024788 Pin configuration for SOT109-1 (SO16) Fig. 6. Pin configuration for SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol Pin Description OE1, OE2 1, 2 output enable input (active LOW) Q0, Q1, Q2, Q3 3, 4, 5, 6 3-state flip-flop output CP 7 clock input (LOW-to-HIGH, edge triggered) GND 8 ground (0 V) E1, E2 9, 10 data enable input (active LOW) D0, D1, D2, D3 14, 13, 12, 11 data input MR 15 asynchronous master reset (active HIGH) VCC 16 supply voltage 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 3 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; qn = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW-to-HIGH CP transition; X = don’t care; ↑ = LOW-to-HIGH clock transition. Register operating mode Outputs Inputs MR CP E1 E2 Dn Qn (register) Reset (clear) H X X X X L Parallel load L ↑ l l I L L ↑ l l h H L X h X X qn L X X h X qn Hold (do nothing) Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state. 3-state buffer operating mode Inputs Read Disabled Outputs Qn (register) OE1 OE2 Q0 Q1 Q2 Q3 L L L L L L L H L L H H H H X H X Z Z Z Z X X H Z Z Z Z 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK Min Max Unit -0.5 +7.0 V VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current -0.5 V < VO < VCC + 0.5 V - ±35 mA ICC supply current - +70 mA IGND ground current -70 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] Conditions [1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 4 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC173 74HCT173 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V 74HC173 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -6.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -7.8 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μA IOZ OFF-state output current VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND - - ±0.5 - ±5.0 - ±10 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8 - 80 - 160 μA 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 5 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state Symbol Parameter CI Conditions 25 °C input capacitance -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT173 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V IO = -6.0 mA 3.98 4.32 - 3.84 - 3.7 - V IO = 20 μA - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 μA IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND - - ±0.5 - ±5.0 - ±10 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A OE1, OE2 - 50 180 - 225 - 245 μA MR - 60 216 - 270 - 294 μA E1, E2 - 40 144 - 180 - 196 μA Dn - 25 90 - 112.5 - 122.5 μA CP - 100 360 - 450 - 490 μA - 3.5 - - - - - pF CI input capacitance 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 6 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 11. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 55 175 - 220 - 265 ns VCC = 4.5 V - 20 35 - 44 - 53 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 30 - 37 - 45 ns - 44 150 - 190 - 225 ns - 16 30 - 38 - 45 ns - 13 - - - - - ns - 13 26 - 33 - 38 ns VCC = 2.0 V - 52 150 - 190 - 225 ns VCC = 4.5 V - 19 30 - 38 - 45 ns VCC = 6.0 V - 15 26 - 33 - 38 ns VCC = 2.0 V - 52 150 - 190 - 225 ns VCC = 4.5 V - 19 30 - 38 - 45 ns VCC = 6.0 V - 15 26 - 33 - 38 ns VCC = 2.0 V - 14 60 - 75 - 90 ns VCC = 4.5 V - 5 12 - 15 - 18 ns VCC = 6.0 V - 4 10 - 13 - 15 ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 60 -8 - 75 - 90 - ns VCC = 4.5 V 12 -3 - 15 - 18 - ns VCC = 6.0 V 10 -2 - 13 - 15 - ns 74HC173 tpd tPHL propagation CP to Qn; see Fig. 7 delay VCC = 2.0 V [1] MR to Qn; see Fig. 8 HIGH to LOW VCC = 2.0 V propagation VCC = 4.5 V delay VCC = 5.0 V; CL = 15 pF VCC = 6.0 V ten tdis tt tW enable time OEn to Qn; see Fig. 9 [2] disable time OEn to Qn; see Fig. 9 transition time pulse width [3] see Fig. 7 [4] CP HIGH or LOW; see Fig. 7 MR HIGH; see Fig. 8 trec recovery time 74HC_HCT173 Product data sheet MR to CP; see Fig. 8 All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 7 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state Symbol Parameter tsu Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 100 33 - 125 - 150 - ns VCC = 4.5 V 20 12 - 25 - 30 - ns VCC = 6.0 V 17 10 - 21 - 26 - ns VCC = 2.0 V 60 17 - 75 - 90 - ns VCC = 4.5 V 12 6 - 15 - 18 - ns VCC = 6.0 V 10 5 - 13 - 15 - ns VCC = 2.0 V 0 -17 - 0 - 0 - ns VCC = 4.5 V 0 -6 - 0 - 0 - ns VCC = 6.0 V 0 -5 - 0 - 0 - ns VCC = 2.0 V 1 -11 - 1 - 1 - ns VCC = 4.5 V 1 -4 - 1 - 1 - ns VCC = 6.0 V 1 -3 - 1 - 1 - ns VCC = 2.0 V 6 26 - 4.8 - 4 - MHz VCC = 4.5 V 30 80 - 24 - 20 - MHz - 88 - - - - - MHz VCC = 6.0 V 35 95 - 28 - 24 - MHz power VI = GND to VCC; VCC = 5 V; [5] dissipation fi = 1 MHz capacitance - 20 - - - - - pF set-up time En to CP; see Fig. 10 Dn to CP; see Fig. 10 th hold time En to CP; see Fig. 10 Dn to CP; see Fig. 10 fmax maximum frequency CP; see Fig. 7 VCC = 5.0 V; CL = 15 pF CPD 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 8 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 20 40 - 50 - 60 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns MR to Qn; see Fig. 8 HIGH to LOW VCC = 4.5 V propagation VCC = 5.0 V; CL = 15 pF delay - 20 37 - 46 - 56 ns - 17 - - - - - ns 74HCT173 propagation CP to Qn; see Fig. 7 delay VCC = 4.5 V tpd tPHL [1] ten enable time OEn to Qn; VCC = 4.5 V; see Fig. 9 [2] - 20 35 - 44 - 53 ns tdis disable time OEn to Qn; VCC = 4.5 V; see Fig. 9 [3] - 19 30 - 38 - 45 ns tt transition time VCC = 4.5 V; see Fig. 7 [4] - 5 12 - 15 - 19 ns tW pulse width CP HIGH or LOW; VCC = 4.5 V; see Fig. 7 16 7 - 20 - 24 - ns MR HIGH; VCC = 4.5 V; see Fig. 8 15 6 - 19 - 22 - ns trec recovery time MR to CP; VCC = 4.5 V; see Fig. 8 12 -2 - 15 - 18 - ns tsu set-up time En to CP; VCC = 4.5 V; see Fig. 10 22 13 - 28 - 33 - ns Dn to CP; VCC = 4.5 V; see Fig. 10 12 7 - 15 - 18 - ns En to CP; VCC = 4.5 V; see Fig. 10 0 -6 - 0 - 0 - ns Dn to CP; VCC = 4.5 V; see Fig. 10 0 -3 - 0 - 0 - ns 30 80 - 24 - 20 - MHz - 88 - - - - - MHz - 20 - - - - - pF th hold time fmax maximum frequency CP; see Fig. 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CPD [1] [2] [3] [4] [5] power VI = GND to VCC - 1.5 V; dissipation VCC = 5 V; fi = 1 MHz capacitance [5] tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD x VCC x fi × N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of outputs. 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 9 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state 10.1. Waveforms and test circuit 1/fmax VI CP input VM GND tW tPHL VOH Qn output tPLH 90 % 90 % VM VOL 10 % 10 % tTHL tTLH aaa-024789 Measurement points are given in Table 9. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. The clock (CP) to outputs (Qn) propagation delays, clock pulse width, output transition times and maximum frequency VI MR input VM GND trec tW VI CP input VM GND tPHL VOH Qn output VM VOL aaa-024790 Measurement points are given in Table 9. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. The master reset (MR) pulse width, master reset to output (Qn) propagation delays, and the master reset to clock (CP) recovery times 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 10 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state VI OEn input VM GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPHZ output HIGH-to-OFF OFF-to-HIGH tPZH VOH VY VM GND outputs enabled outputs disabled outputs enabled aaa-024791 Measurement points are given in Table 9. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 9. 3-state enable and disable times VI En input VM GND VI VM Dn input GND tsu VI CP input tsu th th VM GND aaa-024792 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 9. Fig. 10. The data set-up and hold times from input (En, Dn) to clock (CP) Table 9. Measurement points Input Type Output VM VM VX VY 74HC173 0.5 x VCC 0.5 x VCC 0.1 x VCC 0.9 x VCC 74HCT173 1.3 V 1.3 V 0.1 x VCC 0.9 x VCC 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 11 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VCC VO RT RL S1 open CL 001aad983 Test data is given in Table 10. Test circuit definitions: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistance. S1 = Test selection switch Fig. 11. Test circuit for measuring switching times Table 10. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC173 VCC 6 ns 15 pF, 50 pF 1 kΩ open GND VCC 74HCT173 3V 6 ns 15 pF, 50 pF 1 kΩ open GND VCC 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 12 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 12. Package outline SOT109-1 (SO16) 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 13 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 13. Package outline SOT403-1 (TSSOP16) 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 14 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state 12. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT173 v.4 20210125 Product data sheet - 74HC_HCT173 v.3 Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type numbers 74HC173DB and 74HCT173DB (SOT338-1/SSOP16) removed. Section 7: Derating values for Ptot total power dissipation have been updated. 74HC_HCT173 v.3 20161108 Modifications: • • • 74HC_HCT173 v.2 74HC_HCT173 Product data sheet Product data sheet - 74HC_HCT173 v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Type numbers 74HCT173N and 74HC173N removed. 19901201 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 - © Nexperia B.V. 2021. All rights reserved 15 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state 14. Legal information injury, death or severe property or environmental damage. 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Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC_HCT173 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 16 / 17 74HC173; 74HCT173 Nexperia Quad D-type flip-flop; positive-edge trigger; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit...................................... 10 11. Package outline........................................................ 13 12. Abbreviations............................................................ 15 13. Revision history........................................................15 14. Legal information......................................................16 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 25 January 2021 74HC_HCT173 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 25 January 2021 © Nexperia B.V. 2021. All rights reserved 17 / 17