74HC109DB,112

74HC109; 74HCT109 Dual JK flip-flop with set and reset; positive-edge-trigger Rev. 5 — 5 August 2021 Product data sheet 1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the J and K inputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits • • • • • • • • • • • J and K inputs for easy D-type flip-flop Toggle flip-flop or "do nothing" mode Wide supply voltage range: • For 74HC109: from 2.0 V to 6.0 V • For 74HCT109: from 4.5 V to 5.5 V CMOS low power dissipation High noise immunity Input levels: • For 74HC109: CMOS level • For 74HCT109: TTL level Latch-up performance exceeds 100 mA per JESD 78 Class II Level B 74HC109 complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) 74HCT109 complies with JEDEC standard JESD7A (2.0 V to 6.0 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package 74HC109D Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT109D 74HC109PW 74HCT109PW 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger 4. Functional diagram 5 11 1SD 2SD 2 14 4 12 3 13 SD 1Q 1J Q J 2J 2Q 1CP CP 2CP FF 1Q 1K Q K 2Q 2K RD 5 6 10 2 4 7 9 3 1 1RD 2RD 1 15 Fig. 1. 11 S 1J 6 C1 7 1K 14 12 13 15 R S 1J C1 Logic symbol Fig. 2. 9 1K R (a) mna858 10 (b) mna856 IEC logic symbol Q C K C C C Q J C C C C S R C CP C Fig. 3. aaa-024066 Logic diagram (one flip-flop) 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 2 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger 5. Pinning information 5.1. Pinning 74HC109 74HCT109 1RD 1 16 VCC 1J 2 15 2RD 1K 3 14 2J 1CP 4 13 2K 1SD 5 12 2CP 1Q 6 11 2SD 1Q 7 10 2Q GND 8 9 74HC109 74HCT109 2Q 1RD 1 16 VCC 1J 2 15 2RD 1K 3 14 2J 1CP 4 13 2K 1SD 5 12 2CP 1Q 6 11 2SD 1Q 7 10 2Q GND 8 aaa-024067 Fig. 4. 9 2Q aaa-024068 Pin configuration SOT109-1 (SO16) Fig. 5. Pin configuration SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1RD, 2RD 1, 15 asynchronous reset input (active LOW) 1J, 2J 2, 14 synchronous input 1K, 2K 3, 13 synchronous input 1CP, 2CP 4, 12 clock input (LOW-to-HIGH; edge-triggered) 1SD, 2SD 5, 11 asynchronous set input (active LOW) 1Q, 2Q 6, 10 true flip-flop output 1Q, 2Q 7, 9 complement flip-flop output GND 8 ground (0 V) VCC 16 supply voltage 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 3 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger 6. Functional description Table 3. Function selection H = HIGH voltage level; h = HIGH voltage level one set-up time before the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time before the LOW-to-HIGH CP transition; q = lower case letters indicate the state of the referenced output one set-up time before the LOW-to-HIGH CP transition; X = don’t care; ↑ = LOW-to-HIGH CP transition Operating modes Input Output nSD nRD nCP nJ nK nQ nQ Asynchronous set L H X X X H L Asynchronous reset H L X X X L H Undetermined L L X X X H H Toggle H H ↑ h l q q Load 0 (reset) H H ↑ l l L H Load 1 (set) H H ↑ h h H L Hold no change H H ↑ l h q q 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +7 V VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA ICC supply current - +50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 4 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC109 74HCT109 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V -40 °C to +125 °C Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V 74HC109 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 4.0 - 40 - 80 μA CI input capacitance - 3.5 - - - - - pF 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 5 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Min Typ Max Min Max Min Max Unit 74HCT109 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 5.5 V - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±0.1 - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 35 126 - 157.5 - - 3.5 - - - - nJ, nK, nSD, nRD and nCP inputs CI input capacitance 171.5 μA - pF 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 8. Symbol Parameter Conditions 25 °C -40 °C to +85 °C Min Typ[1] Max -40 °C to +125 °C Unit Min Max Min Max 74HC109 tpd tPLH propagation delay nCP to nQ, nQ; see Fig. 6 VCC = 2.0 V - 50 175 - 220 - 265 ns VCC = 4.5 V - 18 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns VCC = 6.0 V - 14 30 - 37 - 45 ns - 30 120 - 150 - 180 ns - 11 24 - 30 - 36 ns VCC = 5 V; CL = 15 pF - 12 - - - - - ns VCC = 6.0 V - 9 20 - 26 - 31 ns LOW to HIGH nSD to nQ, see Fig. 7 propagation VCC = 2.0 V delay VCC = 4.5 V 74HC_HCT109 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 6 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger Symbol Parameter Conditions 25 °C -40 °C to +85 °C Min Typ[1] Max tPHL tPHL tPLH tt tW HIGH to LOW nSD to nQ; see Fig. 7 propagation VCC = 2.0 V delay VCC = 4.5 V Min Max Min Max - 41 155 - 195 - 235 ns - 15 31 - 39 - 47 ns VCC = 5 V; CL = 15 pF - 12 - - - - - ns VCC = 6.0 V - 12 26 - 33 - 40 ns - 41 185 - 230 - 280 ns - 15 37 - 46 - 56 ns VCC = 5 V; CL = 15 pF - 12 - - - - - ns VCC = 6.0 V - 12 31 - 39 - 48 ns - 39 170 - 215 - 255 ns - 14 34 - 43 - 51 ns VCC = 5 V; CL = 15 pF - 12 - - - - - ns VCC = 6.0 V - 11 29 - 37 - 43 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 70 19 - 90 - 105 - ns VCC = 4.5 V 14 7 - 18 - 21 - ns VCC = 6.0 V 12 6 - 15 - 18 - ns HIGH to LOW nRD to nQ; see Fig. 7 propagation VCC = 2.0 V delay VCC = 4.5 V LOW to HIGH nRD to nQ; see Fig. 7 propagation VCC = 2.0 V delay VCC = 4.5 V transition time nQ, nQ; see Fig. 6 pulse width -40 °C to +125 °C Unit [3] nCP HIGH or LOW; see Fig. 6 nSD, nRD HIGH or LOW; see Fig. 7 trec recovery time nSD, nRD to nCP; see Fig. 7 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 7 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger Symbol Parameter Conditions 25 °C -40 °C to +85 °C Min Typ[1] Max tsu th fmax set-up time hold time maximum frequency Min Max Min Max nJ and nK to nCP; see Fig. 6 VCC = 2.0 V 70 17 - 90 - 105 - ns VCC = 4.5 V 14 6 - 18 - 21 - ns VCC = 6.0 V 12 5 - 15 - 18 - ns VCC = 2.0 V 5 0 - 5 - 5 - ns VCC = 4.5 V 5 0 - 5 - 5 - ns VCC = 6.0 V 5 0 - 5 - 5 - ns VCC = 2.0 V 6 22 - 5 - 4 - MHz VCC = 4.5 V 30 68 - 24 - 20 - MHz nJ and nK to nCP; see Fig. 6 nCP; see Fig. 6 VCC = 5 V; CL = 15 pF - 75 - - - - - MHz 35 81 - 28 - 24 - MHz - 20 - - - - - pF VCC = 4.5 V - 20 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 17 - - - - ns LOW to HIGH nSD to nQ, see Fig. 7 propagation VCC = 4.5 V delay VCC = 5 V; CL = 15 pF - 13 26 - 33 - 39 ns - 14 - - - - - ns HIGH to LOW nSD to nQ; see Fig. 7 propagation VCC = 4.5 V delay VCC = 5 V; CL = 15 pF - 19 35 - 44 - 53 ns - 14 - - - - - ns HIGH to LOW nRD to nQ; see Fig. 7 propagation VCC = 4.5 V delay VCC = 5 V; CL = 15 pF - 19 35 - 44 - 53 ns - 15 - - - - - ns LOW to HIGH nRD to nQ; see Fig. 7 propagation VCC = 4.5 V delay VCC = 5 V; CL = 15 pF - 16 32 - 40 - 48 ns - 15 - - - - - ns - 7 15 - 19 - 22 ns nCP HIGH or LOW; VCC = 4.5 V; see Fig. 6 18 9 - 23 - 27 - ns nSD, nRD HIGH or LOW; VCC = 4.5 V; see Fig. 7 16 8 - 20 - 24 - ns 16 8 - 20 - 24 - ns VCC = 6.0 V CPD -40 °C to +125 °C Unit power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC [4] nCP to nQ, nQ;see Fig. 6 [2] 74HCT109 tpd tPLH tPHL tPHL tPLH propagation delay tt transition time nQ, nQ; VCC = 4.5 V; see Fig. 6 tW pulse width trec recovery time nSD, nRD to nCP; VCC = 4.5 V; see Fig. 7 74HC_HCT109 Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 8 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger Symbol Parameter Conditions 25 °C -40 °C to +85 °C Min Typ[1] Max -40 °C to +125 °C Unit Min Max Min Max tsu set-up time nJ and nK to nCP; VCC = 4.5 V; see Fig. 6 18 8 - 23 - 27 - ns th hold time nJ and nK to nCP; VCC = 4.5 V; see Fig. 6 3 -3 - 3 - 3 - ns fmax maximum frequency nCP; see Fig. 6 27 55 - 22 - 18 - MHz - 61 - - - - - MHz - 22 - - - - - pF VCC = 4.5 V VCC = 5 V; CL = 15 pF CPD [1] [2] [3] [4] power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC - 1.5 V [4] All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of outputs. 10.1. Waveforms and test circuit VI nJ, nK input VM GND tsu th tsu th 1/fmax VI nCP input VM GND tW tPLH tPHL VOH 90 % 90 % VM nQ output 10 % VOL 10 % tTLH tTHL VOH tPHL tPLH 90 % 90 % VM nQ output VOL 10 % 10 % tTLH tTHL aaa-024069 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. Clock propagation delays, output transition time, pulse width, set-up, hold times, and maximum frequency 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 9 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger VI VM nCP input GND trec VI VM nSD input GND tW tW VI VM nRD input GND tPLH tPHL VOH VM nQ output VOL VOH VM nQ output VOL tPHL tPLH aaa-024070 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Set and reset propagation delays, pulse widths and recovery time Table 8. Measurement points Type Input Output VM VM 74HC109 0.5VCC 0.5VCC 74HCT109 1.3 V 1.3 V 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 10 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger VI negative pulse VM VI GND VM 10 % GND positive pulse tW 90 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VO RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. Fig. 8. Test circuit for measuring switching times Table 9. Test data Type Load Input Test VI tr, tf CL 74HC109 VCC 6 ns 15 pF, 50 pF tPLH, tPHL 74HCT109 3V 6 ns 15 pF, 50 pF tPLH, tPHL 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 11 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 12 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 10. Package outline SOT403-1 (TSSOP16) 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 13 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT109 v.5 20210805 Product data sheet - Modifications: • • • 74HC_HCT109 v.4 20200401 Modifications: • • • Type number 74HC109PW (SOT403-1/TSSOP16) added. Type numbers 74HC109DB and 74HCT109DB (SOT338-1/SSOP16) removed. Section 1 and Section 2 updated. 20160801 Modifications: • 74HC_HCT109_CNV v.2 74HC_HCT109 Product data sheet Product data sheet - 74HC_HCT109 v.3 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Table 4: Derating values for Ptot total power dissipation updated. 74HC_HCT109 v.3 • 74HC_HCT109 v.4 Product data sheet - 74HC_HCT109_CNV v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 19971125 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 - © Nexperia B.V. 2021. All rights reserved 14 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC_HCT109 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 15 / 16 74HC109; 74HCT109 Nexperia Dual JK flip-flop with set and reset; positive-edge-trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 9 11. Package outline........................................................ 12 12. Abbreviations............................................................ 14 13. Revision history........................................................14 14. Legal information......................................................15 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 5 August 2021 74HC_HCT109 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 5 August 2021 © Nexperia B.V. 2021. All rights reserved 16 / 16