TF2181M-TAH

Final TF2181M High-Side and Low-Side Gate Driver Features Description  Floating high-side driver in bootstrap operation to 600V  Drives two N-channel MOSFETs or IGBTs in a half bridge configuration  1.9A source / 2.3A sink output current capability  Outputs tolerant to negative transients  Wide low side gate driver supply voltage: 10V to 20V  Logic input (HIN and LIN) 3.3V capability  Schmitt triggered logic inputs with internal pull down  Undervoltage lockout for high and low side drivers  Extended temperature range: -40°C to +125°C The TF2181M is a high voltage, high speed gate driver capable of driving N-channel MOSFETs and IGBTs in a half bridge configuration. TF Semiconductor’s high voltage process enables the TF2181M’s high side to switch to 600V in a bootstrap operation.   The TF2181M logic inputs are compatible with standard TTL and CMOS levels (down to 3.3V) to interface easily with controlling devices. The driver outputs feature high pulse current buffers designed for minimum driver cross conduction. The TF2181M is offered in PDIP-8 and SOIC-8(N) packages and operate over an extended -40 °C to +125 °C temperature range. Applications  DC-DC Converters  AC-DC Inverters  Motor Controls  Class D Power Amplifiers SOIC-8(N) Ordering Information Typical Application Up to 600V VCC VCC HIN HIN LIN LIN R4 COM www.tfsemi.com Jun. 2021 VB HO TF2181M PART NUMBER PACKAGE PACK / Qty TF2181M-3AS PDIP-8 Tube / 50 TF2181M-TAU SOIC-8(N) Tube / 100 TF2181M-TAH SOIC-8(N) T&R / 2500 Year Year Week Week MARK YYWW TF2181M Lot ID YYWW TF2181M Lot ID TO LOAD VS LO Rev 1.2 1 Final TF2181M High-Side and Low-Side Gate Driver Pin Diagrams HIN 1 8 VB LIN 2 7 HO COM 3 6 VS LO 4 5 VCC Top View: SOIC-8 TF2181M Pin Descriptions PIN NAME PIN NUMBER PIN DESCRIPTION HIN 1 Logic input for high-side gate driver output, in phase with HO. LIN 2 Logic input for low-side gate driver output, in phase with LO. COM 3 Low-side and logic return LO 4 Low-side gate drive output VCC 5 Low-side and logic fixed supply VS 6 High-side floating supply return HO 7 High-side gate drive output VB 8 High-side floating supply Functional Block Diagram VCC Vcc HIN TF2181M VB UV Detect UV Detect VSS/COM Level Shift R Pulse Gen HV Level Shift Q HO R S High Voltage Well Vs VCC LIN VSS/COM Level Shift Delay LO COM Jun. 2021 2 Final TF2181M High-Side and Low-Side Gate Driver Absolute Maximum Ratings (NOTE1) A VB - High side floating supply voltage......................-0.3V to +624V VS - High side floating supply offset voltage....VB -24V to VB+0.3V VHO - High side floating output voltage...................VS-0.3V to VB+0.3V dVS / dt - Offset supply voltage transient...................................50 V/ns PD - Package power dissipation at TA ≤ 25 °C SOIC-8.............................................................................................0.625W VCC - Low-side fixed supply voltage...............................-0.3V to +24V VLO - Low-side output voltage....................................-0.3V to VCC +0.3V VIN - Logic input voltage (HIN and LIN)..................-0.3V to VCC +0.3V NOTE1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SOIC-8(N) Thermal Resistance (NOTE2) qJA ...............................................................................................200 °C/W TJ - Junction operating temperature........................................+150 °C TL - Lead Temperature (soldering, 10 seconds).......................+300 °C Tstg - Storage temerature ......................................................-55 to 150 °C NOTE2 Thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Recommended Operating Conditions Symbol Parameter MIN MAX Unit VB High side floating supply absolute voltage VS + 10 VS + 20 V VS High side floating supply offset voltage NOTE3 600 V VHO High side floating output voltage VS VB V VCC Low side fixed supply voltage 10 20 V VLO Low side output voltage 0 VCC V VIN Logic input voltage (HIN and LIN) 0 5 V TA Ambient temperature -40 125 °C NOTE3 Logic operational for VS of -5V to +600V. Jun. 2021 3 Final TF2181M High-Side and Low-Side Gate Driver DC Electrical Characteristics (NOTE4) VBIAS (VCC, VBS ) = 15V, TA = 25 °C , unless otherwise specified. Symbol Parameter VIH Logic “1” input voltage VIL Logic “0” input voltage VCC = 10V to 20V 0.8 VOH High level output voltage, VBIAS - VO IO = 0A 1.4 VOL Low level output voltage, VO IO = 20mA 0.2 ILK Offset supply leakage current VB = VS = 600V 50 IBSQ Quiescent VBS supply current VIN = 0V or 5V 20 60 150 ICCQ Quiescent VCC supply current VIN = 0V or 5V 50 120 240 IIN+ Logic “1” input bias current VIN = 5V 25 60 IIN- Logic “0” input bias current VIN = 0V VBSUV+ VBS supply under-voltage positive going threshold 8.0 8.9 9.8 VBSUV- VBS supply under-voltage negative going threshold 7.4 8.2 9.0 VCCUV+ VCC supply under-voltage positive going threshold 8.0 8.9 9.8 VCCUV- VCC supply under-voltage negative going threshold 7.4 8.2 9.0 IO+ Output high short circuit pulsed current VO = 0V, PW ≤ 10 ms 1.4 1.9 IO- Output low short circuit pulsed current VO = 15V, PW ≤ 10 ms 1.7 2.3 Conditions MIN TYP MAX Unit 2.5 5.0 V mA mA mA V A NOTE4 The VIN, VTH, and IIN parameters are applicable to the two logic input pins: LIN and HIN. The VO and IO parameters are applicable to the respective output pins: HO and LO. NOTE5 For optimal operation, it is highly recommended that the input pulse (to HIN and LIN) should have an amplitude of 2.5V minimum with a pulse width of 360ns minimum. Jun. 2021 4 Final TF2181M High-Side and Low-Side Gate Driver AC Electrical Characteristics VBIAS (VCC, VBS ) = 15V, CL = 1000pF, and TA = 25 °C , unless otherwise specified. Symbol Parameter Conditions ton Turn-on propogation delay toff Turn-off propogation delay tDM Delay matching, HS & LS turn-on/off tr Turn-on rise time tf Turn-off fall time Jun. 2021 MIN TYP MAX VS = 0V 180 270 VS = 0V or 600V 220 330 35 VS = 0V 40 60 20 35 Unit ns 5 Final TF2181M High-Side and Low-Side Gate Driver Timing Waveforms HIN LIN HIN LIN 50% 50% LO HO 10% tDM HO LO tDM 90% LO Figure 1. Input / Output Timing Diagram HIN LIN Figure 2. Delay Matching Waveform Definitions 50% tON HO LO HO 50% tr tOFF 90% 90% 10% tf 10% Figure 3. Switching Time Waveform Definitions Jun. 2021 6 Final TF2181M High-Side and Low-Side Gate Driver Application Information RB1 12V CV1 CV2 400V from PFC DB1 VCC VB HIN HO TF2181M LIN COM CB1 RRG1 CHV1 DRG1 CHV2 Q1 RG1 VS RRG2 DRG2 LO Q2 MCU/ Control RG2 RB2 CV3 DB2 VCC VB HIN HO LIN COM TF2181M VS CB1 RRG3 DRG3 CHV3 Q3 RG3 RRG4 DRG4 LO Q4 RG4 Figure 4. Primary side of Full Bridge converter using TF2181M  RRG1, RRG2, RRG3, and RRG4 values are typically between 0Ω and 10Ω, exact value decided by MOSFET junction capacitance and drive current of gate driver; 10Ω is used in this example.  It is highly recommended that the input pulse (to HIN and LIN) should have an amplitude of 2. 5V minimum (for VDD=15V) with a minimum pulse width of 360ns.  RG1, RG2, RG3, and RG4 values are typically between 20Ω and 100Ω, exact value decided by MOSFET junction capacitance and drive current of gate driver; 50Ω is used in this example.  RB1 and RB2 value is typically between 3Ω and 20Ω, exact value depending on bootstrap capacitor value and amount of current limiting required for bootstrap capacitor charging; 10Ω is used in this example. Also DB1 and DB2 should be an ultra fast diode of 1A rating minimum and voltage rating greater than system operating voltage. Jun. 2021 7 Final TF2181M Package Dimensions (SOIC-8 N) High-Side and Low-Side Gate Driver Please contact support@tfsemi.com for package availability. Jun. 2021 8 Final TF2181M High-Side and Low-Side Gate Driver Revision History Rev. Change Owner Date 1.0 First release, final datasheet Keith Spaulding 8/5/2020 1.1 Changed IO- min. Keith Spaulding 10/15/2020 1.2 Application notes update Raj Selvaraj 06/22/2021 Important Notice TF Semiconductor Solutions (TFSS) PRODUCTS ARE NEITHER DESIGNED NOR INTENDED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS UNLESS THE SPECIFIC TFSS PRODUCTS ARE SPECIFICALLY DESIGNATED BY TFSS FOR SUCH USE. BUYERS ACKNOWLEDGE AND AGREE THAT ANY SUCH USE OF TFSS PRODUCTS WHICH TFSS HAS NOT DESIGNATED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS IS SOLELY AT THE BUYER’S RISK. TFSS assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using TFSS products. Resale of TFSS products or services with statements different from or beyond the parameters stated by TFSS for that product or service voids all express and any implied warranties for the associated TFSS product or service. TFSS is not responsible or liable for any such statements. ©2021 TFSS. All Rights Reserved. Information and data in this document are owned by TFSS wholly and may not be edited , reproduced, or redistributed in any way without the express written consent from TFSS. For additional information please contact support@tfsemi.com or visit www.tfsemi.com. Jun. 2021 9