TF2101M-TAH

TF2101M High-Side and Low-Side Gate Driver Features Description  F  loating high-side driver in bootstrap operation to 600V  Drives two N-channel MOSFETs or IGBTs in high-side/ low-side configuration  Outputs tolerant to negative transients  Wide low-side gate driver and logic supply: 10V to 20V  Logic inputs CMOS and TTL compatible (down to 3.3V)  Schmitt triggered logic inputs with internal pull down  Undervoltage lockout for VCC  Space-saving SOIC-8 package available  Extended temperature range:-40oC to +125oC The TF2101M is a high voltage, high speed gate driver capable of driving N-channel MOSFETs and IGBTs in a high-side/ low-side configuration. TF Semiconductor’s high voltage process enables the TF2101M’s high-side to switch to 600V in a bootstrap operation. The 50ns (max) propagation delay matching between the high and the low side drivers allows high frequency switching. The TF2101M logic inputs are compatible with standard TTL and CMOS levels (down to 3.3V) for easy interfacing with controlling devices. The driver outputs feature high pulse current buffers designed for minimum driver cross conduction. The low-side gate driver and logic share a common ground The TF2101M is available in a space-saving 8-pin SOIC package and an 8-pin PDIP; the operating temperature extends from -40°C to +125°C . Applications  DC-DC Converters  AC-DC Inverters  Motor Controls  Class D Power Amplifiers PDIP-8 SOIC-8(N) Ordering Information Typical Application PART NUMBER PACKAGE PACK / Qty TF2101M-TAU SOIC-8(N) Tube / 100 TF2101M-TAH SOIC-8(N) T & R/ 2500 TF2101M-3AS PDIP-8 Tube / 50 Up to 600V VCC VCC HIN HIN LIN LIN R4 COM www.tfsemi.com July 2019 VB HO TF2101M TO LOAD Year Year Week Week MARK YYWW TF2101M Lot ID YYWW TF2101M Lot ID YYWW TF2101M Lot ID VS LO Rev. 1.1 1 TF2101M High Side and Low Side Gate Driver Pin Diagrams VCC 1 8 VB HIN 2 7 HO LIN 3 6 VS COM 4 5 LO Top View: PDIP-8, SOIC-8 TF2101M Pin Descriptions PIN NAME PIN DESCRIPTION HIN Logic input for high-side gate driver output (HO), in phase LIN Logic input for low-side gate driver output (LO), in phase VB High-side floating supply HO High-side gate drive output VS High-side floating supply return VCC Low-side and logic fixed supply LO Low-side gate drive output COM Low-side return NC “No connect” pin Functional Block Diagram Vcc HIN UV DETECT TF2101M PULSE GEN UV UV Detect Detect HV LEVEL SHIFT/ PULSE FILTER R R VB Q HO S High Voltage Well VS VCC LIN LO COM July 2019 2 TF2101M High Side and Low Side Gate Driver Absolute Maximum Ratings (NOTE1) A VB - High side floating supply voltage...............-0.3V to +624V VS - High side floating supply offset voltage....VB -24V to VB+0.3V VHO - High side floating output voltage...............VS-0.3V to VB+0.3V dVS / dt - Offset supply voltage transient...............................50 V/ns PD - Package power dissipation at TA ≤ 25 °C SOIC-8.............................................................................................0.625W PDIP-8..................................................................................................1.0W VCC - Low side and logic fixed supply voltage..............-0.3V to +24V VLO - Low side output voltage..................................-0.3V to VCC+0.3V VIN - Logic input voltage (HIN and LIN)... -0.3V to VCC+0.3V NOTE1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SOIC-8 Thermal Resistance (NOTE2) qJC..................................................................................................45 °C/W qJA ...............................................................................................200 °C/W PDIP-8 Thermal Resistance (NOTE2) qJC..................................................................................................35 °C/W qJA ................................................................................................125 °C/W TJ - Junction operating temperature .......................................+150 °C TL - Lead temperature (soldering, 10s) .................................. +300 °C Tstg - Storage temperature range ............................-55 °C to +150 °C NOTE2 When mounted on a standard JEDEC 2-layer FR-4 board. Recommended Operating Conditions Symbol Parameter VB High side floating supply absolute voltage VS High side floating supply offset voltage VHO MIN TYP MAX Unit VS + 10 VS + 20 V NOTE3 600 V High side floating output voltage VS VB V VCC Low side and logic fixed supply voltage 10 20 V VLO Low side output voltage 0 VCC V VIN Logic input voltage (HIN and LIN) 0 5 V TA Ambient temperature -40 125 °C NOTE3 Logic operational for VS = -5 to +600V. July 2019 3 TF2101M High Side and Low Side Gate Driver DC Electrical Characteristics (NOTE4) VBIAS (VCC, VBS ) = 15V, TA = 25 °C , unless otherwise specified. Symbol Parameter Conditions MIN VIH Logic “1” input voltage VCC = 10V to 20V 2.5 VIL Logic “0” input voltage VOH High level output voltage, VBIAS - VO IO = 2mA VOL Low level output voltage, VO IO = 2mA ILK Offset supply leakage current VB = VS = 600V IBSQ Quiescent VBS supply current VIN = 0V or 5V ICCQ Quiescent VCC supply current VIN = 0V or 5V IIN+ Logic “1” input bias current VIN = 5V IIN- Logic “0” input bias current VIN = 0V VCCUV+ VCC supply under-voltage positive going threshold 8 VCCUV- VCC supply under-voltage negative going threshold IO+ Output high short circuit pulsed current IO- Output low short circuit pulsed current TYP MAX Unit V NOTE5 0.8 V 0.05 0.2 V 0.02 0.1 V 50 mA 30 55 mA 150 270 mA 3 10 mA 5 mA 8.9 9.8 V 7.4 8.2 9 V VO = 0V, VIN = Logic “1”, PW ≤ 10 ms 130 290 mA VO = 15V, VIN = Logic “0”, PW ≤ 10 ms 270 600 mA MIN TYP MAX Unit AC Electrical Characteristics VBIAS (VCC, VBS ) = 15V, TA = 25 °C, and CL = 1000pF, unless otherwise specified. Symbol Parameter Conditions tON Turn-on propagation delay VS = 0V 160 220 ns tOFF Turn-off propagation delay VS = 600V 150 220 ns tr Turn-on rise time 70 170 ns tf Turn-off fall time 35 90 ns tDM Delay matching 50 ns NOTE4 The VIN, VTH, and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output pins: HO and LO. NOTE5 For optimal operation, it is recommended that the input pulse (to HIN and LIN) should have an amplitude of 2.5V minimum with a pulse width of 300ns minimum July 2019 4 TF2101M High Side and Low Side Gate Driver Timing Waveforms HIN LIN HIN LIN 50% tON HO LO HO LO Figure 1. Input / Output Timing Diagram 50% tr tOFF 90% 90% 10% tf 10% Figure 2. Switching Time Waveform Definitions HIN LIN 50% LO 50% HO 10% tDM tDM 90% LO HO Figure 3. Delay Matching Waveform Definitions July 2019 5 TF2101M High Side and Low Side Gate Driver Typical Characteristics 150 140 Turn On Propagation Delay (ns) Turn On Propagation Delay (ns) 150 ton High Side 130 ton Low Side 120 110 100 90 80 70 140 ton High Side 130 ton Low Side 120 110 100 90 80 70 10 12 14 16 18 20 -40 -20 0 Supply Voltage (V) Figure 4. Turn-on Propagation Delay vs. Supply Voltage 140 Turn Off Propagation Delay (ns) Turn Off Propagation Delay (ns) 60 80 100 120 150 toff High Side 130 toff Low Side 120 110 100 90 80 140 toff High Side 130 toff Low Side 120 110 100 90 80 70 70 10 12 14 18 16 -40 20 -20 0 20 40 60 80 100 120 Temperature (°C) Supply Voltage (V) Figure 6. Turn-off Propagation Delay vs. Supply Voltage Figure 7. Turn-off Propagation Delay vs. Temperature 120 120 110 100 tr High Side 100 tr Low Side 90 Rise Time (ns) 110 Rise Time (ns) 40 Figure 5. Turn-on Propagation Delay vs. Temperature 150 90 80 70 tr High Side tr Low Side 80 70 60 50 40 60 30 20 50 10 12 14 16 Supply Voltage (V) Figure 8. Rise Time vs. Supply Voltage July 2019 20 Temperature (°C) 18 20 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 9. Rise Time vs. Temperature 6 TF2101M High Side and Low Side Gate Driver Typical Characteristics, cont’d 60 50 55 Fall Time (ns) 40 tf High Side 50 tf High Side tf Low Side 45 tf Low Side Fall Time (ns) 45 35 30 25 20 40 35 30 25 20 15 15 10 10 10 12 14 16 18 -40 20 -20 0 20 160 140 140 Quiescent Current (µ µA) Quiescent Current (µ µA) 160 120 100 80 100 120 80 IBSq 60 ICCq 40 20 100 120 120 100 80 IBSq 60 ICCq 40 20 0 10 12 14 16 18 0 20 -40 -20 0 Supply Voltage (V) 20 40 60 Figure 13. Quiescent Current vs. Temperature 20 18 18 16 16 tdmon 14 tdmoff Delay Matching (ns) 20 14 12 10 8 tdmon 6 tdmoff 4 80 Temperature (°C) Figure 12. Quiescent Current vs. Supply Voltage Delay Matching (ns) 60 Figure 11. Fall Time vs. Temperature Figure 10. Fall Time vs. Supply Voltage 12 10 8 6 4 2 2 0 0 10 12 14 16 18 Supply Voltage (V) Figure 14. Delay Matching vs. Supply Voltage July 2019 40 Temperature (°C) Supply Voltage (V) 20 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 15. Delay Matching vs. Temperature 7 TF2101M High Side and Low Side Gate Driver Typical Characteristics, cont’d 800.0 800.0 Output Source Current (mA) Output Source Current (mA) 700.0 IO+ High Side 600.0 IO+ Low Side 500.0 400.0 300.0 200.0 100.0 10 12 14 16 18 700.0 IO+ High Side 600.0 IO+ Low Side 500.0 400.0 300.0 200.0 100.0 20 -40 -20 0 Supply Voltage (V) 800.0 800.0 700.0 700.0 600.0 IO- High Side 400.0 IO- Low Side 300.0 200.0 100.0 10 12 14 16 18 80 100 120 500.0 400.0 IO- High Side 300.0 IO- Low Side 200.0 100.0 20 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 18. Output Sink Current vs. Supply Voltage Figure 19. Output Sink Current vs. Temperature 3.0 3.0 2.5 VIH Low Side 2.0 1.5 1.0 0.5 0.0 10 12 14 16 18 VIH High Side 2.5 VIH High Side Logic 1 Input Voltage (V) Logic 1 Input Voltage (V) 60 600.0 Supply Voltage (V) 20 Supply Voltage (V) Figure 20. Logic 1 Input Voltage vs. Supply Voltage July 2019 40 Figure 17. Output Source Current vs. Temperature Output Sink Current (mA) Output Sink Current (mA) Figure 16. Output Source Current vs. Supply Voltage 500.0 20 Temperature (°C) VIH Low Side 2.0 1.5 1.0 0.5 0.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 21. Logic 1 Input Voltage vs. Temperature 8 TF2101M High Side and Low Side Gate Driver Typical Characteristics, cont’d 3.0 3.0 2.5 VIL High Side 2.0 Logic 0 Input Voltage (V) Logic 0 Input Voltage (V) 2.5 VIL Low Side 1.5 1.0 0.5 0.0 10 12 14 16 18 VIL High Side VIL Low Side 2.0 1.5 1.0 0.5 0.0 20 -40 -20 0 20 Supply Voltage (V) Figure 22. Logic 0 Input Voltage vs. Supply Voltage 80 100 120 Offset Supply Leakage Current (µ µA) 4.5 14 13 VCC UVLO (V) 60 Figure 23. Logic 0 Input Voltage vs. Temperature 15 VCCUV+ 12 VCCUV- 11 10 9 8 7 6 5 -40 -20 0 20 40 60 Temperature (°C) Figure 24. VCC UVLO vs. Temperature July 2019 40 Temperature (°C) 80 100 120 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 25. Offset Supply Leakage Current Temperature 9 TF2101M Package Dimensions (SOIC-8 N) High Side and Low Side Gate Driver Please contact support@tfsemi.com for package availability. July 2019 10 TF2101M Package Dimensions (PDIP-8) July 2019 High Side and Low Side Gate Driver 11 TF2101M High Side and Low Side Gate Driver Revision History Rev. Change Owner Date 1.0 First release Keith Spaulding 4/20/2017 1.1 Add Note 5 Duke Walton 7/28/2019 Important Notice TF Semiconductor Solutions (TFSS) PRODUCTS ARE NEITHER DESIGNED NOR INTENDED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS UNLESS THE SPECIFIC TFSS PRODUCTS ARE SPECIFICALLY DESIGNATED BY TFSS FOR SUCH USE. BUYERS ACKNOWLEDGE AND AGREE THAT ANY SUCH USE OF TFSS PRODUCTS WHICH TFSS HAS NOT DESIGNATED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS IS SOLELY AT THE BUYER’S RISK. TFSS assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using TFSS products. Resale of TFSS products or services with statements different from or beyond the parameters stated by TFSS for that product or service voids all express and any implied warranties for the associated TFSS product or service. TFSS is not responsible or liable for any such statements. ©2019 TFSS. All Rights Reserved. Information and data in this document are owned by TFSS wholly and may not be edited , reproduced, or redistributed in any way without the express written consent from TFSS. For additional information please contact support@tfsemi.com or visit www.tfsemi.com July 2019 12