Sep. 2020
S CB13 H 4G xx0AF
4Gbit DDR3L SDRAM
E U R oH S Co mp lia n t Pr odu ct s
Dat a S hee t
Re v . G
Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
Revision History
Date
Revision
Subjects (major changes since last revision)
2017-12
A
Initial Release
2019-04
B
Add the product of 2133 M
2019-10
C
2020-06
D
2020-07
E
Update the pictures for Figure 1 and Figure 2
2020-07
F
Add the product of industrial grade
2020-09
G
Update the picture for Figure 6: Package Outline for 4Gbit Components x8 Configuration
Modify Row Address
Format review (2020-05)
Modify Figure 1 - Ball out for 512 Mb ×8 Components (PG-TFBGA-78)
Modify Figure 2 - Ball out for 256 Mb ×16 Components (PG-TFBGA-96)
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to
continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:
info@unisemicon.com
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
Contents
Contents ........................................................................................................................................................................................ 3
1
Overview ............................................................................................................................................................................... 4
1.1
Features ................................................................................................................................................................... 4
1.2
Product List............................................................................................................................................................... 5
1.3
DDR3L SDRAM Addressing...................................................................................................................................... 6
1.4
Package Ball out ...................................................................................................................................................... 7
1.5
2
3
4
1.4.1
Ball out for 512 Mb × 8 Components ................................................................................................................ 7
1.4.2
Ball out for 256 Mb ×16 Components ................................................................................................................. 8
Input / Output Signal Functional Description ............................................................................................................. 9
Functional Description ......................................................................................................................................................... 11
2.1
Truth Tables ............................................................................................................................................................ 11
2.2
Mode Register 0 (MR0)........................................................................................................................................... 14
2.3
Mode Register 1 (MR1)........................................................................................................................................... 16
2.4
Mode Register 2 (MR2)........................................................................................................................................... 18
2.5
Mode Register 3 (MR3)........................................................................................................................................... 20
2.6
Burst Order ............................................................................................................................................................. 21
Operating Conditions and Interface Specification ................................................................................................................. 22
3.1
Absolute Maximum Ratings .................................................................................................................................... 22
3.2
Operating Conditions .............................................................................................................................................. 23
3.3
Interface Test Conditions ........................................................................................................................................ 24
3.4
Voltage Levels ........................................................................................................................................................ 25
3.4.1
DC and AC Logic Input Levels ........................................................................................................................ 25
3.4.2
DC and AC Output Measurements Levels ...................................................................................................... 27
3.5
Output Slew Rates .................................................................................................................................................. 28
3.6
ODT DC Impedance and Mid-Level Characteristics ................................................................................................ 29
3.7
ODT DC Impedance Sensitivity on Temperature and Voltage Drifts ........................................................................ 29
3.8
Interface Capacitance ............................................................................................................................................. 30
3.9
Overshoot and Undershoot Specification ................................................................................................................ 31
Speed Bins, AC Timing and IDD ........................................................................................................................................... 33
4.1
Speed Bins ............................................................................................................................................................. 33
4.2
AC Timing Characteristics ( VDD = 1.283V to 1.45V; VDDQ =1.283V to 1.45V ) ................................................... 37
4.3
IDD Specification (IDD Maximum Limits Die for 1.35/1.5V Operation) ................................................................... 43
5
Package Outlines................................................................................................................................................................. 45
6
Product Type Nomenclature................................................................................................................................................. 47
List of Figures .............................................................................................................................................................................. 48
List of Tables................................................................................................................................................................................ 49
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
1 Overview
This chapter gives an overview of the 4Gbit DDR3L SDRAM component product and describes its main characteristics.
1.1 Features
The 4Gbit DDR3L SDRAM offers the following key
features:
• VDD,=VDDQ=1.35V(1.283V-1.45V)
。 Backward compatible to VDD=VDDQ=1.5 V ± 0.075V)
-Supports DDR3L devices to be backward compatible in
1.5V applications
。Data rate :1600Mbps/1866Mbps/2133Mbps
Options
• Configuration
– 512 Meg x 8
– 256 Meg x 16
。Differential bidirectional data strobe
• FBGA package (Pb-free) – x16
– 96-ball (13.5mm x 7.5mm)
。 8n-bit prefetcharchitecture
。Differential clock inputs (CK, CKB)
。8 internal banks
。Nominal and dynamic on-die termination (ODT) for data,
strobe, and mask signals
。Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via
the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self-refresh mode
• TC of 0°C to + 95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multi-purpose register
• Output driver calibration
UniIC_Techdoc, Rev. G 2020-09
• FBGA package (Pb-free) – x8
– 78-ball (10.6mm x 7.5mm)
• Timing – cycle time
– 938ps @ CL = 14 (DDR3-2133)
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
• Operating temperature
– Commercial, (0°C ≤TC ≤ +95°C)
– Industrial, (-40°C ≤TC ≤ +95°C)
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
1.2 Product List
Table 1 shows all possible products within the 4Gbit DDR3L SDRAM component generation. Availability depends on
application needs. For UniIC part number nomenclature see Chapter 6.
Table 1 - Ordering Information for4Gbit DDR3L Components
UniIC Part Number
Max. Clock
frequency
Org
CAS-RCD-RP
latencies
Speed Sort
Name
Package
Commercial Temperature Range(0°C ~ +95°C)
SCB13H4G800AF-13K
800 MHz
×8
11-11-11
DDR3L–1600K
PG-TFBGA-78
SCB13H4G800AF-11M
933 MHz
×8
13-13-13
DDR3L–1866M
PG-TFBGA-78
SCB13H4G800AF-09N
1067 MHz
SCB13H4G160AF-13K
800 MHz
SCB13H4G160AF-11M
933 MHz
SCB13H4G160AF-09N
1067 MHz
Industrial Temperature Range(-40°C ~ +95°C)
SCB13H4G800AF-13KI
800 MHz
×8
× 16
× 16
× 16
14-14-14
11-11-11
13-13-13
14-14-14
DDR3L–2133N
DDR3L–1600K
DDR3L–1866M
DDR3L–2133N
PG-TFBGA-78
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
×8
11-11-11
DDR3L–1600K
PG-TFBGA-78
SCB13H4G800AF-11MI
933 MHz
×8
13-13-13
DDR3L–1866M
PG-TFBGA-78
SCB13H4G800AF-09NI
SCB13H4G160AF-13KI
SCB13H4G160AF-11MI
SCB13H4G160AF-09NI
1067 MHz
800 MHz
933 MHz
1067 MHz
×8
× 16
× 16
× 16
14-14-14
11-11-11
13-13-13
14-14-14
DDR3L–2133N
DDR3L–1600K
DDR3L–1866M
DDR3L–2133N
PG-TFBGA-78
PG-TFBGA-96
PG-TFBGA-96
PG-TFBGA-96
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
1.3 DDR3L SDRAM Addressing
Table 2 - 4Gbit DDR3L SDRAM Addressing
Configuration
512Mb × 8
256Mb × 16
Internal Organization
8 banks × 64M words × 8bits
8 banks × 32M words × 16bits
Refresh count
8K
8K
Bank Address
8(BA[2:0])
8(BA[2:0])
Row Address
64K (A[15:0])
32K (A[14:0])
Column Address
1K(A[9:0])
1K(A[9:0])
Page Size
1KB
2KB
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Note
Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
1.4 Package Ball out
Figure 1 show the ball outs for DDR3L SDRAM components. See Chapter 5 for package outlines.
1.4.1 Ball out for 512 Mb × 8 Components
Figure 1 - Ball out for 512 Mb ×8 Components (PG-TFBGA-78)
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
1.4.2
Ball out for 256 Mb × 16 Components
Figure 2 - Ball out for 256 Mb ×16 Components (PG-TFBGA-96)
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
1.5 Input / Output Signal Functional Description
Table 3 - Input / Output Signal Functional Description
Symbol
Type
Function
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK.
CKE
Input
Clock Enable: CKE High activates, and CKE Low deactivates internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self-Refresh operation (all banks idle), or Active Power-Down ( active row in any bank).
CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable
during the power on and initialization sequence, they must be maintained during all operations
(including Self-Refresh). CKE must be maintained High throughout read and write accesses.
Input buffers, excluding CK, /CK, ODT, CKE and /RESET are disabled during Power-down.
Input buffers, excluding CKE and RESET are disabled during self refresh.
/CS
Input
Chip Select: All commands are masked when /CS is registered High. /CS provides for external
Rank selection on systems with multiple ranks. /CS is considered part of the command code.
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
ODT
Input
On-Die Termination: ODT (registered High) enables termination resistance internal to the
DDR3L SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS and DM signal
for×8 configurations. The ODT signal will be ignored if the Mode Register MR1 is programmed
to disable ODT and during Self Refresh.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled High coincident with that input data during a Write access. DM is sampled on both
edges of DQS.
BA0 - BA2
Input
Bank Address Inputs: Define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines which mode register is to be accessed during a
mode register set cycle.
Input
Address Inputs: Provides the row address for Active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
(A10/AP and A12 | /BC have additional functions, see below). The address inputs also provide
the op-code during Mode Register Set commands.
A10 | AP
Input
Auto-Precharge: A10 | AP is sampled during Read/Write commands to determine whether
Auto-Precharge should be performed to the accessed bank after the Read/Write operation.
(High: Auto-Precharge, Low: no Auto-Precharge). A10 | AP is sampled during Precharge
command to determine whether the Precharge applies to one bank (A10 Low) or all banks
(A10 High). If only one bank is to be precharged, the bank is selected by bank addresses.
A12 | /BC
Input
Burst Chop: A12 | /BC is sampled during Read and Write commands to determine if burst
chop (on-the-fly) will be performed. (High: no burst chop, Low: burst chopped). See
“Command Truth Table” on Page 11 for details.
DQ
Input/
Output
Data Input/Output: Bi-directional data bus.
DQS /DQS
Input/
Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered
in write data. The data strobes DQS are paired with differential signals /DQS, to provide
differential pair signaling to the system during both read and write. DDR3L
A0 – A15
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
Symbol
Type
Function
/RESET
CMOS
Input
Active Low Asynchronous Reset: Reset is active when /RESET is Low, and inactive when
/RESET is High. /RESET must be High during normal operation. /RESET is a CMOS rail to rail
signal with DC High and Low are 80% and 20% of VDD, /RESET active is destructive to data
contents.
NC
—
No Connect: no internal electrical connection is present
VDDQ
Supply
DQ Power Supply: 1.283V to 1.45V or 1.5 V ± 0.075V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.283V to 1.45V or 1.5 V ± 0.075V
VSS
Supply
Ground
VREFDQ
Supply
Reference Voltage for DQ
VREFCA
Supply
Reference Voltage for Command and Address inputs
ZQ
Supply
Reference ball for ZQ calibration
Note: Input only pins (BA0-BA2, A0-A15, /RAS, /CAS, /WE, /CS, CKE, ODT, and /RESET) do not supply termination.
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
2 Functional Description
2.1 Truth Tables
The truth tables list the input signal values at a given clock edge which represent a command or state transition expected to be
executed by the DDR3L SDRAM. Table 4 lists all valid commands to the DDR3L SDRAM. For a detailed description of the
various power mode entries and exits please refer to Table 5. In addition, the DM functionality is described in Table 6.
Table 4 - Command Truth Table
Function
Abbr.
CKE
Prev. Curr.
Cycle Cycle
/CS /RAS /CAS /WE BA2 A13- A12| A10| A11,
Note
A15 /BC AP A9-A0
BA0
1)2)3)4)5)
Mode Register Set
MRS
H
H
L
L
L
L
BA
OP Code
Refresh
REF
H
H
L
L
L
H
V
V
V
V
V
1)2)3)4)5)
Self-Refresh Entry
SRE
H
L
L
L
L
H
V
V
V
V
V
1)2)3)4)5)6)7)8)
Self-Refresh Exit
SRX
L
H
H
V
V
V
V
V
V
V
V
1)2)3)4)5)6)7)8)9)
L
H
H
H
Single Bank Precharge
PRE
H
H
L
L
H
L
BA
V
V
L
V
1)2)3)4)5)
Precharge all Banks
PREA
H
H
L
L
H
L
V
V
V
H
V
1)2)3)4)5)
Active
ACT
H
H
L
L
H
H
BA
RA (Row Address)
Write (BL8MRS or
BC4MRS)
WR
H
H
L
H
L
L
BA
V
V
L
CA
1)2)3)4)5)10)
Write (BC4OTF)
WRS4
H
H
L
H
L
L
BA
V
L
L
CA
1)2)3)4)5)10)
Write (BL8OTF)
WRS8
H
H
L
H
L
L
BA
V
H
L
CA
1)2)3)4)5)10)
Write w/AP (BL8MRS or
BC4MRS)
WRA
H
H
L
H
L
L
BA
v
V
H
CA
1)2)3)4)5)10)
Write w/AP (BC4OTF)
WRAS4 H
H
L
H
L
L
BA
V
L
H
CA
1)2)3)4)5)10)
Write w/AP (BL8OTF)
WRAS8 H
H
L
H
L
L
BA
V
H
H
CA
1)2)3)4)5)10)
Read (BL8MRS or
BC4MRS)
RD
H
H
L
H
L
H
BA
V
V
L
CA
1)2)3)4)5)10)
Read (BC4OTF)
RDS4
H
H
L
H
L
H
BA
V
L
L
CA
1)2)3)4)5)10)
Read (BL8OTF)
RDS8
H
H
L
H
L
H
BA
V
H
L
CA
1)2)3)4)5)10)
Read w/AP (BL8MRS or
BC4MRS)
RDA
H
H
L
H
L
H
BA
V
V
H
CA
1)2)3)4)5)10)
Read w/AP (BC4OTF)
RDAS4
H
H
L
H
L
H
BA
V
L
H
CA
1)2)3)4)5)10)
Read w/AP (BL8OTF)
RDAS8
H
H
L
H
L
H
BA
V
H
H
CA
1)2)3)4)5)10)
No Operation
NOP
H
H
L
H
H
H
V
V
V
V
V
1)2)3)4)5)11)
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1)2)3)4)5)
Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
Function
Abbr.
CKE
Prev. Curr.
Cycle Cycle
CS RAS CAS WE BA2 A13 A12| A10/ A11,
Note
A14 /BC AP A9-A0
BA0 A15
Device Deselect
DES
H
H
H
X
X
X
X
X
X
X
X
1)2)3)4)5)12)
Power Down Entry
PDE
H
L
L
H
H
H
V
V
V
V
V
1)2)3)4)5)8)13)
H
V
V
V
Power Down Exit
PDX
L
H
L
H
H
H
V
V
V
V
V
1)2)3)4)5)8)13)
H
V
V
V
ZQ Calibration Short
ZQCS
H
H
L
H
H
L
X
X
X
L
X
1)2)3)4)5)
ZQ Calibration Long
ZQCL
H
H
L
H
H
L
X
X
X
H
X
1)2)3)4)5)
1) BA = Bank Address, RA = Row Address, CA = Column Address, BC = Burst Chop, AP = Auto Precharge, X = Don’t care, V = valid
2) All DDR3L SDRAM commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the clock. The higher
order address bits of BA, RA and CA are device density and IO configuration (×4, ×8, ×16) dependent.
3) /RESET is a low active signal which will be used only for asynchronous reset. It must be maintained High during any function.
4) Bank addresses (BA) determine which bank is to be operated upon. For MRS, BA selects a Mode Register.
5) V means H or L (but a defined logic level) and X means either “defined or undefined (like floating) logic level”.
6) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh
7) VREF (both VREFCA and VREFDQ) must be maintained during Self Refresh operation.
8) Refer to “Clock Enable (CKE) Truth Table for Synchronous Transitions” on Page 13 for more detail with CKE transition.
9) Self refresh exit is asynchronous.
10) Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
11) The No Operation (NOP) command should be used in cases when the DDR3L SDRAM is in an idle or a wait state. The purpose of the
NOP command is to prevent the DDR3L SDRAM from registering any unwanted commands between operations. A NOP command will
not terminate a previous operation that is still executing, such as a read or write burst.
12) The Deselect command (DES) performs the same function as a No Operation command.
13) The Power Down Mode does not perform any refresh operation.
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
Table 5 - Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State 1)
CKE(N-1)2)
CKE(N)2)
Command (N)3)
Action (N)3)
Note
/RAS, /CAS, /WE, /CS
Previous
Cycle
Current
Cycle
L
L
X
Maintain Power Down
4)5)6)7)8)9)
L
H
DES or NOP
Power Down Exit
4)5)6)7)8)10)
L
L
X
Maintain Self Refresh
4)5)6)7)9)11)
L
H
DES or NOP
Self Refresh Exit
4)5)6)7)11)12)13)
Bank(s) Active
H
L
DES or NOP
Active Power Down Entry
4)5)6)7)8)10)14)
Reading
H
L
DES or NOP
Power Down Entry
4)5)6)7)8)10)14)15)
Writing
H
L
DES or NOP
Power Down Entry
4)5)6)7)8)10)14)15)
Precharging
H
L
DES or NOP
Power Down Entry
4)5)6)7)8)10)14)15)
Refreshing
H
L
DES or NOP
Precharge Power Down Entry
4)5)6)7)10)
All Banks Idle
H
L
DES or NOP
Precharge Power Down Entry
4)5)6)7)10)8)14)16)
H
L
REF
Self Refresh Entry
4)5)6)7)14)16)17)
Power Down
Self Refresh
Any other state
Refer to “Command Truth Table” on Page 11 for more detail with all command signals
4)5)6)7)18)
Current state is defined as the state of the DDR3L SDRAM immediately prior to clock edge N.
CKE(N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N),ODT is not included here.
All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
CKE must be registered with the same value on tCKE.MIN consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the tCKE.MIN clocks of registeration. Thus, after any CKE transition, CKE may not transition from its valid level
during the time period of tIS + tCKE.MIN + tIH.
7) DES and NOP are defined in “Command Truth Table” on Page 11.
8) The Power Down does not perform any refresh operations
9) X means Don’t care (including floating around VREFCA) in Self Refresh and Power Down. It also applies to address pins.
10) Valid commands for Power Down Entry and Exit are NOP and DES only
11) VREF (both VREFCA and VREFDQ) must be maintained during Self Refresh operation.
12) On Self Refresh Exit DES or NOP commands must be issued on every clock edge occurring during the tXS period. Read, or ODT
commands may be issued only after tXSDLL is satisfied.
13) Valid commands for Self Refresh Exit are NOP and DES only.
14) Self Refresh can not be entered while Read or Write operations are in progress.
15) If all banks are closed at the conclusion of a read, write or precharge command then Precharge Power-down is entered, otherwise Active
Power-down is entered.
16) ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is High, and all timings from
previous operations are satisfied (tMRD, tMOD, tRFC, tZQ.INIT, tZQ.OPER, tZQCS, etc.) as well as all Self-Refresh exit and Power-Down Exit
parameters are satisfied (tXS, tXP, tXPDLL, etc.).
17) Self Refresh mode can only be entered from the All Banks Idle state.
18) Must be a legal command as defined in “Command Truth Table” on Page 11.
1)
2)
3)
4)
5)
6)
Table 6 - Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Write Enable
L
Valid
Write Inhibit
H
X
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
2.2 Mode Register 0 (MR0)
The mode register MR0 stores the data for controlling various operating modes of DDR3L SDRAM. It controls burst length, read
burst type, CAS latency, test mode, DLL reset, WR (write recovery time for auto-precharge) and DLL control for precharge
Power-Down, which includes various vendor specific options to make DDR3L SDRAM useful for various applications. The
mode register is written by asserting Low on /CS, /RAS, /CAS, /WE, BA0, BA1, and BA2, while controlling the states of address
pins according to Table 7.
BA2
0
BA1 BA0 A15-A13
0
0
01)
A12 A11
PPD
A10
A9
WR
A8
DLL
A7
TM
A6
A5
CL
A4
A3
A2
RBT
CL
A1
A0
BL
Table 7 - MR0 Mode register Definition (BA[2:0]=000B)
Field
Bits1)
Description
BL
A[1:0]
Burst Length (BL) and Control Method
Number of sequential bits per DQ related to one Read/Write command.
00B BL8MRS mode with fixed burst length of 8. A12 | /BC at Read or Write command time is Don’t
care at read or write command time.
01B BLOTF on-the-fly (OTF) enabled using A12 | /BC at Read or Write command time. When A12 |
/BC is High during Read or Write command time a burst length of 8 is selected (BL8OTF mode).
When A12 | /BC is Low, a burst chop of 4 is selected (BC4OTF mode). Auto-Precharge can be
enabled or disabled.
10B BC4MRS mode with fixed burst chop of 4 with tCCD = 4 × nCK. A12 | /BC is Don’t care at Read or
Write command time.
11B TBD Reserved
RBT
A3
Read Burst Type
0B
Nibble Sequential
1B
Interleaved
CL
A[6:4,2]
CAS Latency (CL)
CAS Latency is the delay, in clock cycles, between the internal Read command and the availability of the
first bit of output data.
Note: For more information on the supported CL and AL settings based on the operating clock frequency,
refer to “Speed Bins” on Page 33.
Note: All other bit combinations are reserved.
0000B RESERVED
0010B 5
0100B 6
0110B 7
1000B 8
1010B 9
1100B 10
1110B 11
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
Field
Bits1)
Description
TM
A7
Test Mode
The normal operating mode is selected by MR0(bit A7 = 0) and all other bits set to the desired values
shown in this table. Programming bit A7 to a 1 places the DDR3L SDRAM into a test mode that is only
used by the SDRAM manufacturer and should NOT be used. No operations or functionality is guaranteed
if A7 = 1.
0B
Normal Mode
1B
Vendor specific test mode
DLLres
A8
DLL Reset
The internal DLL Reset bit is self-clearing, meaning it returns back to the value of 0 after the DLL reset
function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any
time the DLL reset function is used, tDLLK must be met before any functions that require the DLL can be
used (i.e. Read commands or synchronous ODT operations).
0B
No DLL Reset
1B
DLL Reset triggered
WR
A[11:9]
Write Recovery for Auto-Precharge
Number of clock cycles for write recovery during Auto-Precharge. WRMIN in clock cycles is calculated by
dividing tWR.MIN (in ns) by the actual tCK.AVG (in ns) and rounding up to the next integer: WR.MIN [nCK] =
Roundup(tWR.MIN[ns] / tCK.AVG[ns]). The WR value in the mode register must be programmed to be equal
or larger than WR.MIN. The resulting WR value is also used with tRP to determine tDAL. Since WR of 9
and 11 is not implemented in DDR3L and the above formula results in these values, higher values have
to be programmed.
000B Reserved
001B 5
010B 6
011B 7
100B 8
101B 10
110B 12
111B Reserved
PPD
A12
Precharge Power-Down DLL Control
Active Power-Down will always be with DLL-on. Bit A12 will have no effect in this case. For Precharge
Power-Down, bit A12 in MR0 is used to select the DLL usage as shown below.
0B
Slow Exit. DLL is frozen during precharge Power-down.Read and synchronous ODT commands
are only allowed after tXPDLL.
1B
Fast Exit. DLL remains on during precharge Power-down.Any command can be applied after tXP,
provided that other timing parameters are satisfied.
1) A13, A14 and A15 - even if not available on a specific device - must be programmed to 0B.
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
2.3 Mode Register 1 (MR1)
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom impedance,
additive latency (AL), Write leveling enable and Qoff (output disable). The Mode Register MR1 is written by asserting Low on
CS, RAS, CAS, WE, High on BA0 and Low on BA1and BA2, while controlling the states of address pins according to Table 8.
BA2
0
BA1 BA0 A15-A13 A12
0
1
01)
Qoff
A11
A10
A9
A8
A7
A6
A5
0
0
RTT_
nom
0
Level
RTT_
nom
DIC
A4
A3
AL
A2
A1
RTT_
nom
DIC
A0
DLL
Table 8 - MR1 Mode Register Definition (BA[2:0]=001B)
Field
Bits1)
Description
DLLdis
A0
DLL Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization,
after reset and upon returning to normal operation after having the DLL disabled. During normal
operation (DLL-on) with MR1(A0 = 0), the DLL is automatically disabled when entering Self-Refresh
operation and is automatically re-enabled and reset upon exit of Self-Refresh operation. Any time the
DLL is enabled, a DLL reset must be issued afterwards. Any time the DLL is reset, tDLLK clock cycles
must occur before a Read or synchronous ODT command can be issued to allow time for the internal
clock to be synchronized with the external clock. Failing to wait for synchronization to occur may
result in a violation of the tDQSCK, tAON, tAOF or tADC parameters. During tDLLK, CKE must continuously
be registered high. DDR3L SDRAM does not require DLL for any Write operation.
0B
DLL is enabled
1B
DLL is disabled
DIC
A[5, 1]
Output Driver Impedance Control
Note: All other bit combinations are reserved.
00:
01B
RTT_NOM
RZQ/6
Nominal Drive Strength RON34 = RQZ/7 (nominal 34.3 Ω, with nominal RZQ = 240 Ω)
A[9, 6, 2] Nominal Termination Resistance of ODT
Notes
1. If RTT_NOM is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
2. In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 1, all RTT_Nom settings are allowed; in
Write Leveling Mode (MR1[bit7] = 1) with MR1[bit12] = 0, only RTT_NOM settings of RZQ/2, RZQ/4
and RZQ/6 are allowed.
3. All other bit combinations are reserved.
000B ODT disabled, RTT_NOM = off, Dynamic ODT mode disabled
001B RTT60 = RZQ / 4 (nominal 60 Ω with nominal RZQ = 240 Ω)
010B RTT120 = RZQ / 2 (nominal 120 Ω with nominal RZQ = 240 Ω
011B RTT40 = RZQ / 6 (nominal 40 Ω with nominal RZQ = 240 Ω)
100B RTT20 = RZQ / 12 (nominal 20 Ω with nominal RZQ = 240 Ω)
101B RTT30 = RZQ / 8 (nominal 30 Ω with nominal RZQ = 240 Ω)
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
Field
Bits1)
Description
AL
A[4, 3]
Additive Latency (AL)
Any read or write command is held for the time of Additive Latency (AL) before it is issued as internal
read or write command.
Notes
1. AL has a value of CL - 1 or CL - 2 as per the CL value programmed in the MR0 register.
00B AL = 0 (AL disabled)
01B AL = CL - 1
10B AL = CL - 2
11B
Reserved
Write
Leveling
enable
A7
Write Leveling Mode
0B
Write Leveling Mode Disabled, Normal operation mode
1B
Write Leveling Mode Enabled
TDQS
enable
A11
0: Disabled
1: Enabled
Qoff
A12
Output Disable
Under normal operation, the SDRAM outputs are enabled during read operation and write leveling
for driving data (Qoff bit in the MR1 is set to 0B). When the Qoff bit is set to 1B, the SDRAM outputs
(DQ, DQS, /DQS) will be disabled - also during write leveling. Disabling the SDRAM outputs allows
users to run write leveling on multiple ranks and to measure IDD currents during Read operations,
without including the output.
oB
Output buffer enabled
1B
Output buffer disabled
1) A13, A14, A15 - even if not available on a specific device - must be programmed to 0B.
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
2.4 Mode Register 2 (MR2)
The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance, and CAS write latency.
The Mode Register MR2 is written by asserting Low on CS, RAS, CAS, WE, High on BA1 and Low on BA0 and BA2, while
controlling the states of address signals according to Table 9.
BA2
0
BA1 BA0 A15-A13 A12
1
0
01)
0
A11
0
A10
A9
Rtt_WR
A8
A7
A6
0
SRT
ASR
A5
A4
CWL
A3
A2
A1
A0
PASR
Table 9 - MR2 Mode Register Definition (BA[2:0]=010B)
Field
Bits1)
Description
PASR
A[2:0]
Partial Array Self Refresh (PASR)
If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the
specified self refresh location may get lost if self refresh is entered. During non-self-refresh operation,
data integrity will be maintained if tREFI conditions are met.
000B Full array (Banks 000B - 111B)
001B Half Array(Banks 000B - 011B)
010B Quarter Array(Banks 000B - 001B)
011B 1/8th array (Banks 000B )
100B 3/4 array(Banks 010B - 111B)
101B Half array(Banks 100B - 111B)
110B Quarter array(Banks 110B - 111B)
111B 1/8th array(Banks 111B )
CWL
A[5:3]
CAS Write Latency (CWL)
Number of clock cycles from internal write command to first write data in.
Note: All other bit combinations are reserved.
000B
001B
010B
011B
Note:
RFU
A6
5 (3.3 ns ≥ tCK.AVG ≥ 2.5 ns)
6 (2.5 ns > tCK.AVG ≥ 1.875 ns)
7 (1.875 ns > tCK.AVG ≥ 1.5 ns)
8 (1.5 ns > tCK.AVG ≥ 1.25 ns)
Besides CWL limitations on tCK.AVG, there are also tAA.MIN/MAX restrictions that need to be
observed. For details, please refer to Chapter 4.1, Speed Bins.
0: Manual SR reference (SRT)
1: ASR enable (Optional).
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
Field
Bits1)
Description
SRT
A7
Self-Refresh Temperature Range (SRT)
The SRT bit must be programmed to indicate TOPER during subsequent self refresh operation.
0B
Normal operating temperature range
1B
Extended operating temperature range
RTT_WR
A[10:9]
Dynamic ODT mode and RTT_WR Pre-selection
Notes
1. All other bit combinations are reserved.
2. The RTT_WR value can be applied during writes even when RTT_NOM is disabled. During write
leveling, Dynamic ODT is not available.
00B Dynamic ODT mode disabled
01B Dynamic ODT mode enabled with RTT_WR = RZQ/4 = 60 Ω
10B Dynamic ODT mode enabled with RTT_WR = RZQ/2 = 120Ω
1) A13, A14, A15 - even if not available on a specific device - must be programmed to 0B.
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
2.5 Mode Register 3 (MR3)
The Mode Register MR3 controls Multi purpose registers and optional On-die thermal sensor (ODTS) feature. The Mode
Register MR3 is written by asserting Low on CS, RAS, CAS, WE, High on BA1 and BA0, and Low on BA2 while controlling the
states of address signals according to Table 10
BA2
0
BA1 BA0
1
A15-A13 A12
1
01)
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
0
0
0
0
0
0
0
0
0
MPR
0
Table 10 - MR3 Mode Register Definition (BA[2:0]=011B)
Field
Bits1)
Description
MPR loc
A[1:0]
Multi Purpose Register Location
00B Pre-defined data pattern for read synchronization
01B RFU
10B RFU
11B
ODTS On-Die Thermal sensor readout (optional)
MPR
A2
Multi Purpose Register Enable
Note: When MPR is disabled, MR3 A[1:0] will be ignored.
0B
1B
MPR disabled, normal memory operation
Dataflow from the Multi Purpose register MPR
1) A13, A14 and A15 - even if not available on a specific device - must be programmed to 0B.
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A1
A0
MPR loc
Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
2.6 Burst Order
Accesses within a given burst may be interleaved or nibble sequential depending on the programmed bit A3 in the mode
register MR0.
Regarding read commands, the lower 3 column address bits CA[2:0] at read command time determine the start address for the
read burst.
Regarding write commands, the burst order is always fixed. For writes with a burst length of 8, the inputs on the lower 3
column address bits CA[2:0] are ignored during the write command. For writes with a burst being chopped to 4, the input on
column address 2 (CA[2]) determines if the lower or upper four burst bits are selected. In this case, the inputs on the lower 2
column address bits CA[1:0] are ignored during the write command.The following table shows burst order versus burst start
address for reads and writes of bursts of 8 as well as of bursts of 4 operation (burst chop).
Table 11 - Bit Order during Burst
Starting
Burst
READ/
Column
Length
WRITE
Address
(A[2,
0 01,0 0])
READ
4 (chop)
WRITE
8 (fixed)
READ
WRITE
Burst Type = Sequential
(Decimal)
Burst Type = Interleaved
(Decimal)
Notes
0, 1, 2, 3, Z, Z, Z, Z
0, 1, 2, 3, Z, Z, Z, Z
1, 2
001
1, 2, 3, 0, Z, Z, Z, Z
1, 0, 3, 2, Z, Z, Z, Z
1, 2
010
2, 3, 0, 1, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
1, 2
011
3, 0, 1, 2, Z, Z, Z, Z
3, 2, 1, 0, Z, Z, Z, Z
1, 2
100
4, 5, 6, 7, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
1, 2
101
5, 6, 7, 4, Z, Z, Z, Z
5, 4, 7, 6, Z, Z, Z, Z
1, 2
110
6, 7, 4, 5, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
1, 2
111
7, 4, 5, 6, Z, Z, Z, Z
7, 6, 5, 4, Z, Z, Z, Z
1, 2
0VV
0, 1, 2, 3, X, X, X, X
0, 1, 2, 3, X, X, X, X
1, 3, 4
1VV
4, 5, 6, 7, X, X, X, X
4, 5, 6, 7, X, X, X, X
1, 3, 4
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
1
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
1
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
1
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
1
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
1
VVV
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1, 3
Notes: 1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8.
2. Z = Data and strobe output drivers are in tri-state.
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins.
4. X = “Don’t Care.”
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
3 Operating Conditions and Interface Specification
3.1 Absolute Maximum Ratings
Table 12 - Absolute Maximum Ratings
Parameter
Symbol
Rating
Min.
Max.
Unit
Note
1)
Voltage on VDD ball relative to VSS
VDD
–0.4
+1.975
V
Voltage on VDDQ ball relative to VSS
VDDQ
–0.4
+1.975
V
Voltage on any ball relative to VSS
VIN, VOUT
–0.4
+1.975
V
Storage Temperature
TSTG
–55
+150
°C
1) VDD and VDDQ must be within 300mV of each other at all times. VREF must not be greater than 0.6 x VDDQ. When VDD and
VDDQ are less than 500 mV, VREF may be equal or less than 300 mV.
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
3.2 Operating Conditions
Table 13 - SDRAM Component Operating Temperature Range
Rating
Parameter
Symbol
Tc
Operating Temperature Range
Unit
Note
85
°C
1)2)3)4)
95
°C
1)2)3)4)
Min.
Max.
0
85
1) MAX operating case temperature TC is measured in the center of the package, as shown below.
2) A thermal solution must be designed to ensure that the device does not exceed the maximum TC during operation.
3) Device functionality is not guaranteed if the device exceeds maximum TC during operation.
4) If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs interval refresh rate. The use of self
refresh temperature (SRT) or automatic self refresh (ASR), must be enabled.
Table 14 - DC Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit Note
Supply Voltage
1.283
1.35
1.45
V
1-7
Supply Voltage for Output
VDD
VDDQ
1.283
1.35
1.45
V
1-7
Reference Voltage for DQ, DM inputs
VREFDQ.DC 0.49 x VDD 0.5 x VDD 0.51 x VDD V
VREFCA.DC 0.49 x VDD 0.5 x VDD 0.51 x VDD V
Ω
External Calibration Resistor connected from ZQ ball to ground RZQ
237.6
240.0
242.4
Reference Voltage for ADD, CMD inputs
8)9)
9)10)
11)
1) VDD and VDDQ must track one another. VDDQ must be ≤ VDD. VSS = VSSQ.
2) VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC (0 Hz to 250 kHz) specifications.
VDD and VDDQ must be at same level for valid AC timing parameters.
3) Maximum DC value may not be greater than 1.425V. The DC value is the linear average of V DD/VDDQ(t) over a very long
period of time (for example, 1 second)
4) Under these supply voltages, the device operates to this DDR3L specification
5) If the maximum limit is exceeded, input levels shall be governed by DDR3specifications.
6) Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifi-cations under the same speed
timings as defined for this device.
7) Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are
changed for DDR3 operation (see VDD Voltage Switch-ing .
8) VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak
noise (non-common mode) on VREFCA may not exceed ±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on
VREFCA should not ex-ceed ±2% of VREFCA(DC).
9) DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifi-cations if the DRAM induces
additionalAC noise greater than 20 MHz in frequency
10) VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak
noise (non-common mode) on VREFDQ maynot exceed ±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on
VREFDQ should not ex-ceed ±2% of VREFDQ(DC).
11) The external calibration resistor RZQ can be time-shared among DRAMs in multi-rank DIMMs.
Table 15 - Input and Output Leakage Currents
Parameter
Symbol
Condition
Rating
Min.
Max.
Unit
Note
Input Leakage Current
IIL
Any input 0 V < VIN < VDD
–2
+2
µA
1)2)
Output Leakage Current
IOL
0V < VOUT < VDDQ
–5
+5
µA
2)3)
1) All other pins not under test = 0 V.
2) Values are shown per ball.
3) DQ’s, DQS, /DQS and ODT are disabled.
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
3.3 Interface Test Conditions
Figure 4 represents the effective reference load of 25 Ω used in defining the relevant timing parameters of the device as well as
for output slew rate measurements. It is not intended as either a precise representation of the typical system environment nor a
depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions,
generally one or more coaxial transmission lines terminated at the tester electronics.
Figure 3 - Reference Load for AC Timings and Output Slew Rates
8)9)
CK, /CK
The Timing Reference Points are the idealized input and output nodes / terminals on the outside of the packaged SDRAM
device as they would appear in a schematic or an IBIS model.
The output timing reference voltage level for single ended signals is the cross point with VTT.
The output timing reference voltage level for differential signals is the cross point of the true (e.g. DQS) and the complement
(e.g. /DQS) signal.
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
3.4 Voltage Levels
3.4.1 DC and AC Logic Input Levels
Single-Ended Signals
Table 16 shows the input levels for single-ended input signals.
Table 16 - DC and AC Input Levels for Single-Ended Command, Address and Control Signals
Parameter
Symbol
DDR3L-1600,-1866,-2133
Max.
VDD
VREF - 0.100
V
1)
V
1)
See 2)
V
1)
VREF - 0.175
V
1)
VIH.CA.DC
DC input logic low
VIL.CA.DC
VREF + 0.100
VSS
AC input logic high
VIH.CA.AC
VREF + 0.175
VIL.CA.AC
Note
Min.
DC input logic high
AC input logic low
Unit
See
2)
1) For input only pins except RESET: VREF = VREF.CA
2) See Chapter 3.9, Overshoot and Undershoot Specification.
Table 17 - DC and AC Input Levels for Single-Ended DQ and DM Signals
Parameter
Symbol
DDR3L-1600,-1866,-2133
Min.
Max.
DC input logic high
VIH.DQ.DC
VREF + 0.100
VDD
DC input logic low
VIL.DQ.DC
VSS
VREF - 0.100
2)
AC input logic high
VIH.DQ.AC
VREF + 0.150
See
AC input logic low
VIL.DQ.AC
See 2)
VREF - 0.150
Unit
Note
V
1)
V
1)
V
1) 3)
V
1) 3)
1) For DQ and DM: VREF = VREFDQ, for input only signals except RESET: VREF = VREFCA
2) See Chapter 3.9, Overshoot and Undershoot Specification.
3) Single ended swing requirement for DQS, /DQS is 350 mV (peak to peak). Differential swing requirement for DQS, /DQS is 700 mV (peak to
peak).
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Data Sheet
SCB13H4Gxx0AF
4-Gbit DDR3L SDRAM
Differential Swing Requirement for Differential Signals
Table 18 shows the input levels for differential input signals.
Table 18 - Differential swing requirement for clock (CK - /CK) and strobe (DQS - /DQS)
Parameter
Symbol
DDR3L-1600,-1866,-2133
Min.
Max.
Unit
Note
Differential input high
VIH.DIFF
+0.18
See 1)
V
2)
Differential input low
VIL.DIFF
See1)
–0.18
V
2)
Differential input high AC
VIH.DIFF.AC
2 x (VIH.AC - VREF)
See 1)
V
4)
Differential input low AC
VIL.DIFF.AC
See 1)
V
4)
3)
2 x (VREF - VIL.AC)
5)
1) These values are not defined, however they single-ended signals CK, /CK, DQS, /DQS need to be within the respective limits ( VIH.DC.MAX ,
VIL.DC.MIN ) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to Chapter 3.9 .
2) Used to define a differential signal slew-rate.
3) Clock: use VIH.CA.AC for VIH.AC. Strobe: use VIH.DQ.AC for VIH.AC.
4) For CK - /CK use VIH /VIL.AC of ADD/CMD and VREFCA; for DQS - /DQS use VIH /VIL.AC of DQs and VREFDQ;
if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
5) Clock: use VIL.CA.AC for VIL.AC. Strobe: use VIL.DQ.AC for VIL.AC.
Table 19 - Allowed Time Before Ringback (tDVAC) for CK - /CK and DQS - /DQS
tDVAC [ps]@ |VIH/IL.DIFF.AC|
tDVAC [ps]@ |VIH/IL.DIFF.AC|
DDR3L-1600
DDR3L-1866
Slew Rate [V/ns]
320mv
270mv
270mv
260mv
250mv
> 4.0
189
201
163
176
168
4.0
189
201
163
176
168
3.0
162
179
140
154
147
2.0
109
134
95
111
105
1.8
91
119
80
97
91
1.6
69
100
62
78
74
1.4
40
76
37
55
52
1.2
Note1
44
5
Note1
—
Note1
24
22
1.0
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