K24C08

Two-wire Serial EEPROM K24C02C / K24C04 / K24C08C / K24C16B Spring 2011 K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Features ?Wide Voltage Operation ?1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility ?Write Protect Pin for Hardware Data Protection ?8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes ?Partial Page Writes Allowed ?Self-timed Write Cycle (5 ms max) ?High-reliability - VCC = 1.8V to 5.5V ?Operating Ambient Temperature: -40• C to +85• C ?Internally Organized: - K24C02C, 256 X 8 (2K bits) - K24C04, 512 X 8 (4K bits) - K24C08C, 1024 X 8 (8K bits) - Endurance: 1 Million Write Cycles - K24C16B, 2048 X 8 (16K bits) - Data Retention: 100 Years ?Two-wire Serial Interface ?Schmitt Trigger, Filtered Inputs for Noise Suppression ?Bidirectional Data Transfer Protocol ?8-lead PDIP/SOP/MSOP/TSSOP, 8-pad DFN, and SOT23-5 packages General Description The K24C02C/K24C04/K24C08C/K24C16B provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The K24C02C/K24C04/K24C08C/K24C16B is available in space-saving 8-lead PDIP , 8-lead SOP, 8-lead MSOP, 8-lead TSSOP, 8-pad DFN, and SOT23-5 packages and is accessed via a two-wire serial interface. Pin Configuration ?Table 1: Pin Configuration Pin Name Founctions A0 - A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect GND Ground VCC Power Supply 8-lead PDIP SOT23-5 8-pad DFN VCC 8 1 A0 1 7 2 6 3 A1 A2 SCL WP SCL SDA GND 2 5 4 GND SDA 3 WP 4 VCC Bottom view 8-lead SOP 8-lead MSOP 8-lead TSSOP A0 1 8 VCC A0 1 8 VCC A0 1 8 VCC A0 A1 2 7 WP A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL A2 3 6 SCL GND 4 5 SDA GND 4 5 SDA GND 4 5 SDA A1 A2 GND Spring 2011 5 1 2 3 4 8 7 6 5 VCC WP SCL SDA V1.3 . 001 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Block Diagram VCC GND WP SCL START STOP LOGIC SDA EN SERIAL CONTROL LOGIC HIGH VOLTAGE PUMP/TIMING LOAD COMP DATA RECOVERY DEVICE ADDRESS COMPARATOR INC A1 DATA WORD ADDRESS COUNTER A2 Y DECODER DIN X DECODER LOAD A0 EEPROM SERIAL MUX DOUT/ACKNOWLEDGE DOUT Spring 2011 V1.3 . 002 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Pin Descriptions DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the K24C02C. Eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The K24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground. The K24C08C only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to ground. The K24C16B does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no connects and can be connected to ground. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The K24C02C/K24C04/K24C08C/K24C16B has a W rite Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to V CC , the write protection feature is enabled and operates as shown in the following ?Table 2: Write Protect Part of the Array Protected WP Pin Status At VCC K24C02C Full (2K) Array At GND K24C04 K24C08C K24C16B Full (4K) Array Full (8K) Array Full (16K) Array Normal Read / Write Operations Memory Organization K24C02C, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. K24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. K24C08C, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. K24C16B, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing. Spring 2011 V1.3 . 003 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see to Figure 2 on page 4). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on page 4). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The K24C02C/K24C04/K24C08C/K24C16B features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. ?Figure 1: Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE ?Figure 2: Start and Stop Definition SDA SCL START Spring 2011 STOP V1.3 . 004 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) ?Figure 3: Output Acknowledge 1 SCL 8 9 DATA IN DATA OUT START ACKNOWLEDGE Device Addressing The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 7). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. Spring 2011 V1.3 . 005 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5 on page 7). PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 6 on page 7). The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7 on page 8). Spring 2011 V1.3 . 006 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Read Operations RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 8). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9 on page 8). ?Figure 4: Device Address 2K 1 0 1 0 A2 A1 A0 MSB R/W LSB 4K 1 0 1 0 A2 A1 P0 R/W 8K 1 0 1 0 A2 P1 P0 R/W 16K 1 0 1 0 P2 P1 P0 R/W ?Figure 5: Byte Write S T A R DEVICE T ADDRESS W R I T E WORD ADDRESS S T O P DATA SDA LINE M S B L R AM S / CS BWK B LA SC BK A C K ?Figure 6: Page Write S W T R A I R DEVICE T ADDRESS T E WORD ADDRESS DATA ( n ) DATA ( n+1 ) S T O P DATA ( n+x ) SDA LINE M S B Spring 2011 L R AM S / CS BWK B LA SC BK A C K A C K A C K V1.3 . 007 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) ?Figure 7: Current Address Read S T A R DEVICE T ADDRESS R E A D S T O P DATA SDA LINE M S B N O L RA S/C BWK A C K ?Figure 8: Random Read S W T R A I DEVICE R T T ADDRESS E WORD ADDRESS S T A R DEVICE T ADDRESS R E A D S T O P DATA SDA LINE L R AM S / CS BWK B M S B LA M SC S BK B N O LRA S /C BWK A C K DUMMY WRITE ?Figure 9: Sequential Read R E DEVICE A ADDRESS D DATA ( n ) DATA ( n+1) DATA ( n+2 ) DATA ( n+x ) S T O P SDA LINE RA /C WK Spring 2011 A C K A C K A C K N O A C K V1.3 . 008 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) Electrical Characteristics ?Absolute Maximum Stress Ratings ?Comments Stresses above those listed under "Absolute Maximum Ratings" DC Supply Voltage . . . . . . . . . . . . . . . . .-0.3V to +6.5V may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any Input / Output Voltage . . . . . . . .GND-0.3V to VCC+0.3V other conditions above those indicated in the operational sections Operating Ambient Temperature . . . . . -40• C to +85• C of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may Storage Temperature . . . . . . . . . . . . -65• C to +150• C affect device reliability. DC Electrical Characteristics ?Applicable over recommended operating range from: T Parameter A = -40 • C to +85 • C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol Min. Typ. Max. Unit Supply Voltage VCC 1.8 - 5.5 V Condition Supply Current VCC = 5.0V ICC1 - 0.4 1.0 mA READ at 100 kHz Supply Current VCC = 5.0V ICC2 - 2.0 3.0 mA WRITE at 100 kHz Standby Current ISB - - 1.0 A VIN = VCC or GND Input Leakage Current ILI - - 3.0 A VIN = VCC or GND Output Leakage Current ILO - 0.05 3.0 A VOUT = VCC or GND -0.3 - VCC x 0.3 V - VCC + 0.3 V Input Low Level VIL Input High Level VIH Output Low Level VCC =5.0V VOL3 - - 0.4 V IOL = 3.0 mA Output Low Level VCC =3.0V VOL2 - - 0.4 V IOL = 2.1 mA Output Low Level VCC =1.8V VOL1 - - 0.2 V IOL = 0.15 mA VCC x 0.7 Pin Capacitance ?Applicable over recommended operating range from T Parameter A = 25 • C, f = 1.0 MHz, VCC = +1.8V Symbol Min. Typ. Input/Output Capacitance (SDA) CI/O - - 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL) CIN - - 6 pF VIN = 0V Spring 2011 Max. Unit Condition V1.3 . 009 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) AC Electrical Characteristics ?Applicable over recommended operating range from T A = -40• C to +85• C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 1.8-volt Parameter Symbol 5.0-volt Min. Typ. Max. Min. Typ. Max. Units Clock Frequency, SCL fSCL - - 400 - - 1000 kHz Clock Pulse Width Low tLOW 1.2 - - 0.6 - - s Clock Pulse Width High tHIGH 0.6 - - 0.4 - - s Noise Suppression Time tI - - 50 - - 40 ns Clock Low to Data Out Valid tAA 0.05 - 0.9 0.05 - 0.55 s Time the bus must be free before a new transmission can start tBUF 1.2 - - 0.5 - - s tHD.STA 0.6 - - 0.25 - - s Start Setup Time tSU.STA 0.6 - - 0.25 - - s Data In Hold Time tHD.DAT 0 - - 0 - - s Data In Setup Time tSU.DAT 100 - - 100 - - ns Inputs Rise Time(1) tR - - 0.3 - - 0.3 s Start Hold Time tF - - 300 - - 100 ns tSU.STO 0.6 - - 0.25 - - s Data Out Hold Time tDH 50 - - 50 - - ns Write Cycle Time(for 04/16B) tWR1 - 3.3 5 - 3.3 5 ms Write Cycle Time(for 02C/08C) tWR2 - 1.5 5 - 1.5 5 ms Endurance 1M - - - - - Write Cycles Inputs Fall Time(1) Stop Setup Time • 5.0V, 25 C, Byte Mode Note 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 ns Input and output timing reference voltages: 0.5 VCC The value of RL should be concerned according to the actual loading on the user's system. Spring 2011 V1.3 . 010 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Bus Timing ÿFigure 10: SCL: Serial Clock, SDA: Serial Data I/O tHIGH tF tLOW tR tLOW SCL tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO SDA_IN tAA tDH tBUF SDA_OUT Write Cycle Timing ÿFigure 11: SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK tWR(1) STOP CONDITION START CONDITION Note 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Spring 2011 V1.3 . 011 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) 8-lead PDIP package diagram D 1 eA E1 eC c eB N End View Top View COMMON DIMENSIONS A3 (Unit of Measure = mm) A2 MIN MAX A 3.60 4.00 A1 0.51 - A2 3.10 3.50 A3 1.50 1.70 b 0.44 0.53 b1 0.43 SYMBOL A1 B b B e B1 L B Side View 0.48 1.52 BSC c 0.25 0.31 c1 0.24 0.26 D 9.05 9.45 E1 6.15 6.55 e 2.54 BSC b eA 7.62 BSC b1 eB 7.62 9.50 eC 0 0.94 3.00 - c1 c Base Metal L With Plating Section B-B Spring 2011 V1.3 . 0012 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) 8-lead SOP package diagram C 1 E E1 N L θ Top View End View COMMON DIMENSIONS (Unit of Measure = mm) e B SYMBOL A A1 MIN A 1.35 1.75 A1 0.10 0.25 b 0.31 0.51 C 0.17 0.25 D 4.70 5.10 E1 3.80 4.00 E 5.79 6.20 e D MAX 1.27 BSC L 0.40 1.27 θ 0° 8° Side View Spring 2011 V1.3 . 0013 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) 8-lead TSSOP package diagram 3 2 1 E E1 L1 N θ Top View L End View COMMON DIMENSIONS (Unit of Measure = mm) A b e D A2 MIN MAX D 2.80 3.20 E 6.20 6.60 E1 4.20 4.60 A – 1.20 A2 0.80 1.15 b 0.19 0.30 SYMBOL e Side View L 0.65 BSC 0.45 L1 θ Spring 2011 0.75 1.00 BSC 0° 8° V1.3 . 0014 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) 8-lead MSOP package diagram C 1 E1 E L N B B L1 θ Top View End View b e COMMON DIMENSIONS A3 (Unit of Measure = mm) A A2 A1 D Side View b b1 SYMBOL MIN A - 1.10 A1 0.05 0.15 A2 0.75 0.95 A3 0.30 0.40 b 0.29 0.38 b1 0.28 0.33 c 0.15 0.20 c1 0.14 0.16 D 2.90 3.10 E 4.70 5.10 E1 2.90 3.10 e c1 c L 0.65 BSC 0.40 L1 θ Base Metal MAX 0.70 0.95 BSC 0° 8° With Plating Section B-B Spring 2011 V1.3 . 0015 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) 8-pad DFN package diagram A E c Side View 1 2 A1 D Top View End View COMMON DIMENSIONS D2 (Unit of Measure = mm) b E2 h SYMBOL MIN MAX A 0.70 0.80 A1 - 0.05 b 0.18 0.30 c 0.18 0.25 D 1.90 1.50 REF e 0.50 BSC Nd h E 1.50 BSC 2.90 3.10 1.60 BSC E2 L 2.10 D2 L 0.30 0.50 h 0.20 0.30 e Nd Bottom View Spring 2011 V1.3 . 0016 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8 ) 5-lead SOT23 package diagram D 4 5 E1 E L B 1 B 3 2 θ End View Top View b A2 COMMON DIMENSIONS A (Unit of Measure = mm) A3 e A1 Side View b b1 SYMBOL MIN A 1.05 1.30 A1 0 0.10 A2 1.00 1.20 A3 0.55 0.75 b 0.30 0.50 b1 0.33 0.38 c 0.10 0.21 c1 0.14 0.16 D 2.72 3.12 E 2.60 3.00 E1 1.40 1.80 0.95 BSC e c1 c Base Metal MAX L 0.30 0.60 θ 0° 8° With Plating Section B-B Spring 2011 V1.3 . 0017 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Ordering Information Code Number Part Number K 24 XXX X 1 2 3 4 2.Series Name 24: Two-wire (I2C) Interface 3.EEPROM Density C02 = 2K bits C04 = 4K bits C08 = 8K bits C16 = 16K bits X X X X X 5 6 7 8 9 6.Temperature Range 4.Design Option 1.Prefix - 8.Plating Technology I = Industry (-40 •C to 85 •C) Version code 5.Package Type Blank = Standard SnPb plating G = RoHS compliant 7.Pack Type D = PDIP T = Tube S = SOP R = Tape & Reel S = Green, level 1 X = Green, level 3 9.Operating Voltage T = TSSOP M = MSOP A = 1.8 to 5.5 V N = DFN O = SOT Available package types PDIP SOP TSSOP MSOP DFN SOT23 K24C02C Model √ √ √ √ √ √ K24C04 √ √ √ √ √ √ K24C08C √ √ √ √ √ √ K24C16B √ √ √ √ √ － Product Datasheet Change Notice Datasheet Revision History Version Content Date 1.0 Initial version Dec., 2006 1.2 1.3 Spring 2011 Package type update Design version & Package type update Dec., 2008 Jan., 2011 V1.3 . 01 018 . K24C02C/K24C04/K24C08C/K24C16B Two-wire Serial EEPROM 2K bits (256 X 8) / 4K bits (512 X 8) / 8K bits (1024 X 8) / 16K bits (2048 X 8) Disclaimers The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. HUAJIE assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. HUAJIE reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of HUAJIE or others. HUAJIE makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does HUAJIE assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. " Typ. " parameters can and do vary in different applications. All operating parameters, including " Typ. " must be validated for each customer application by the customer's technical experts. HUAJIE products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the HUAJIE product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a HUAJIE product for any such unintended or unauthorized application, the Buyer shall indemnify and hold HUAJIE and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that HUAJIE was negligent regarding the design or manufacture of said product. K24C Series (I2C Bus) Serial EEPROM Data Sheet, Revision 1.3 2011 HUAJIE All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of HUAJIE. Spring 2011 V1.3 . 019 .