SiT9365
Standard Frequency Ultra-low Jitter Differential Oscillator
Description
Features
The SiT9365 is a differential MEMS XO supporting
standard frequencies between 25 MHz and 325 MHz,
and engineered for low-jitter applications. Utilizing
SiTime’s unique DualMEMS™ temperature sensing and
TurboCompensation™ technology, the SiT9365 delivers
exceptional dynamic performance by providing
resistance to airflow, thermal gradients, shock and
vibration. This device also integrates multiple on-chip
regulators to filter power supply noise, eliminating the
need for a dedicated external LDO.
32 standard frequencies from 25 MHz to 325 MHz
(For additional frequencies, refer to SiT9366 and
SiT9367 datasheets)
LVPECL, Low-swing LVPECL, LVDS and HCSL output
signaling
0.1 ps RMS phase jitter (random) for Ethernet applications
Frequency stability as low as ±10 ppm
Wide temperature ranges from -40°C to 105°C
The SiT9365 can be factory programmed for specific
combinations of frequency, stability, voltage, and output
signaling. Programmability enables designers to optimize
clock configurations while eliminating long lead times and
customization costs associated with quartz devices
where each frequency is custom built.
2
Industry-standard packages: 3.2 x 2.5 mm , 7.0 x 5.0 mm
2
and 5.0 x 3.2 mm package
2
Applications
10/40/100 Gbps Ethernet, SONET, SATA, SAS,
Fibre Channel
Telecom, networking, instrumentation, storage, servers
Standard frequencies and programmability makes this
device ideal for telecom, networking, and industrial
applications that require a variety of frequencies and
operate in noisy environments.
Refer to Manufacturing Notes for proper reflow profile,
tape and reel dimension, and other manufacturing
related information.
Block Diagram
Package Pinout
1
6
VDD
NC
2
5
OUT-
GND
3
4
OUT+
Figure 2. Pin Assignments (Top view)
(Refer to Table 7 for Pin Descriptions)
Figure 1. SiT9365 Block Diagram
Rev 1.08
OE/NC
August 17, 2019
www.sitime.com
SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Ordering Information
SiT9365AC - 1B2-33E125.000000T
Part Family
Packaging
“SiT9365”
“T”, “Y”, “D” or “E”
Refer to table below for packing method
[1]
Leave Blank for Bulk
Revision Letter
“A” is the revision of Silicon
Frequency
See supported frequency list below
Temperature Range
“C”: Extended Commercial, -20 to 70°C
“I”: Industrial, -40 to 85°C
“B”: -40 to 95 °C
“E”: Extended Industrial, -40 to 105°C
Feature Pin
“N”: No Connect
“E”: Output Enable
Signalling Type
“1”:
“2”:
“4”:
“5”:
Voltage Supply
LVPECL
LVDS
HCSL
Low-swing LVPECL
“25”: 2.5 V ±10%
“28”: 2.8 V ±10%
“30”: 3.0 V ±10%
“33”: 3.3 V ±10%
Package Size
“B”: 3.2 x 2.5 mm
“C”: 5.0 x 3.2 mm with center pad
“E”: 7.0 x 5.0 mm with center pad
Frequency Stability
“F”:
“1”:
“2”:
“3”:
±10 ppm
±20 ppm
±25 ppm
±50 ppm
Notes:
1. Bulk is available for sampling only.
Table 1. Supported Frequencies
25.000000 MHz
30.720000 MHz
50.000000 MHz
53.125000 MHz
61.440000 MHz
62.500000 MHz
74.175824 MHz
74.250000 MHz
75.000000 MHz
77.760000 MHz
98.304000 MHz
100.000000 MHz
106.250000 MHz
122.880000 MHz
125.000000 MHz
133.333333 MHz
148.351648 MHz
150.000000 MHz
153.600000 MHz
155.520000 MHz
156.250000 MHz
159.375000 MHz
160.000000 MHz
161.132813 MHz
166.666666 MHz
168.040678 MHz
200.000000 MHz
212.500000 MHz
250.000000 MHz
300.000000 MHz
322.265625 MHz
325.000000 MHz
Table 2. Ordering Codes for Supported Tape & Reel Packing Method
Device Size
(mm x mm)
8 mm T&R
(3ku)
8 mm T&R
(1ku)
12 mm T&R
(3ku)
12 mm T&R
(1ku)
16 mm T&R
(3ku)
16 mm T&R
(1ku)
7.0 x 5.0
—
—
—
—
T
Y
T
Y
D
E
—
—
5.0 x 3.2
3.2 x 2.5
Rev 1.08
Page 2 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features ....................................................................................................................................................................................... 1
Applications .................................................................................................................................................................................. 1
Block Diagram .............................................................................................................................................................................. 1
Package Pinout ............................................................................................................................................................................ 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics .............................................................................................................................................................. 4
Waveform Diagrams..................................................................................................................................................................... 9
Termination Diagrams ................................................................................................................................................................ 11
LVPECL and Low-swing LVPECL ....................................................................................................................................... 11
LVDS................................................................................................................................................................................... 13
HCSL .................................................................................................................................................................................. 14
2
Dimensions and Patterns ― 3.2 x 2.5 mm ................................................................................................................................ 15
2
Dimensions and Patterns ― 5.0 x 3.2 mm ................................................................................................................................ 15
2
Dimensions and Patterns ― 7.0 x 5.0 mm ................................................................................................................................ 16
Additional Information................................................................................................................................................................. 17
Revision History ......................................................................................................................................................................... 18
Rev 1.08
Page 3 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Electrical Characteristics
All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with
standard output termination shown in the termination diagrams. Typical values are at 25°C and nominal supply voltage.
Table 3. Electrical Characteristics – Common to LVPECL, Low-swing LVPECL, LVDS and HCSL (All
temperature ranges)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Range
Output Frequency Range
f
32 standard frequencies between
25 MHz and 325.000000 MHz
MHz
Frequency Stability
Frequency Stability
F_stab
-10
–
+10
ppm
-20
–
+20
ppm
-25
–
+25
ppm
-50
–
+50
ppm
Inclusive of initial tolerance, operating temperature, rated power
supply voltage and load variations
First Year Aging
F_1y
-0.7
±0.4
+0.7
ppm
At 85°C
5 Year Aging
F_5y
-1.1
±0.7
+1.1
ppm
At 85°C
10 Year Aging
F_10y
-1.3
±0.8
+1.3
ppm
At 85°C
20 Year Aging
F_20y
-1.5
±1.0
+1.5
ppm
At 85°C
Temperature Range
Operating Temperature Range
T_use
-20
–
+70
°C
Extended Commercial
-40
–
+85
°C
Industrial
-40
–
+95
°C
-40
–
+105
°C
Extended Industrial
Supply Voltage
Supply Voltage
Vdd
2.97
3.30
3.63
V
2.70
3.00
3.30
V
2.52
2.80
3.08
V
2.25
2.50
2.75
V
Input Characteristics
–
Vdd
Input Voltage High
VIH
VIL
70%
–
–
Input Voltage Low
–
30%
Vdd
Pin 1, OE
Input Pull-up Impedance
Z_in
–
100
–
kΩ
Pin 1, OE logic high or logic low
Pin 1, OE
Output Characteristics
Duty Cycle
DC
45
–
55
%
Startup and OE Timing
Startup Time
OE Enable/Disable Time
Rev 1.08
T_start
–
–
3.0
ms
Measured from the time Vdd reaches its rated minimum value.
T_oe
–
–
3.8
µs
f = 156.25 MHz. Measured from the time OE pin reaches rated
VIH and VIL to the time clock pins reach 90% of swing and
high-Z. See Figure 8 and Figure 9.
Page 4 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Table 4. Electrical Characteristics – LVPECL, Low-swing LVPECL
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Current Consumption
Idd
–
–
89
mA
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE Disable Supply Current
I_OE
–
–
58
mA
OE = Low
Output Disable Leakage Current
I_leak
–
0.15
–
A
OE = Low
I_driver
–
–
30
mA
Maximum average current drawn from OUT+ or OUT-
Current Consumption
Maximum Output Current
Output High Voltage
VOH
Output Low Voltage
Output Differential Voltage Swing
VOL
Output Characteristics for LVPECL
–
Vdd-1.1
Vdd-0.7
V
See Figure 4
–
Vdd-1.9
Vdd-1.5
V
See Figure 4
V_Swing
1.2
1.6
2.0
V
See Figure 5
Tr, Tf
–
225
290
ps
20% to 80%. See Figure 5
Rise/Fall Time
Output High Voltage
VOH
Output Characteristics for Low-swing LVPECL
–
Vdd-1.2
Vdd-0.75
V
See Figure 4
Output Low Voltage
VOL
Vdd-1.8
–
Vdd-1.25
V
See Figure 4
V_Swing
0.4
1
1.2
V
Output frequency less than or equal to 220 MHz, See Figure 5
0.4
1
1.6
V
Output frequency greater than 220 MHz, See Figure 5
–
225
290
ps
20% to 80%. See Figure 5
Output Differential Voltage Swing
Rise/Fall Time
Tr, Tf
Jitter – 7.0 x 5.0 mm Package
RMS Period Jitter[2]
T_jitt
–
1.0
1.6
ps
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V
RMS Phase Jitter (random)
T_phj
–
0.225
0.270
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC
and -40 to 85ºC
–
0.225
0.300
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC
and -40 to 105ºC
–
0.1
–
ps
f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10GbE jitter
mask integration bandwidth = 1.875 MHz to 20 MHz, includes
spurs, all Vdd levels.
RMS Period Jitter[2]
RMS Phase Jitter (random)
T_jitt
Jitter – 5.0 x 3.2 mm and 3.2 x 2.5 mm Packages
–
1.0
1.6
ps
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V
–
0.225
0.275
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC
and -40 to 85ºC
–
0.225
0.340
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC
and -40 to 105ºC
–
0.1
–
ps
f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10GbE jitter
mask integration bandwidth = 1.875 MHz to 20 MHz, includes
spurs, all Vdd levels.
Notes:
2. Measured according to JESD65B
Rev 1.08
Page 5 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Table 5. Electrical Characteristics – LVDS
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Current Consumption
Idd
–
–
79
mA
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE Disable Supply Current
I_OE
–
–
58
mA
OE = Low
Output Disable Leakage Current
I_leak
–
0.15
–
A
OE = Low
Current Consumption
Output Characteristics
Differential Output Voltage
Delta VOD
Offset Voltage
VOD
300
–
450
mV
See Figure 6
ΔVOD
–
–
50
mV
See Figure 6
VOS
–
1.375
V
See Figure 6
–
50
mV
See Figure 6
400
470
ps
Measured with 2 pF capacitive loading to GND, 20% to 80%.
See Figure 7
Delta VOS
ΔVOS
1.125
–
Rise/Fall Time
Tr, Tf
–
RMS Period Jitter[3]
T_jitt
–
1.0
1.6
ps
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V
RMS Phase Jitter (random)
T_phj
–
0.215
0.265
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC
and -40 to 85ºC
–
0.215
0.300
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC
and -40 to 105ºC
–
0.1
–
ps
f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10GbE jitter
mask integration bandwidth = 1.875 MHz to 20 MHz, includes
spurs, all Vdd levels.
Jitter – 7.0 x 5.0 mm Package
Jitter – 5.0 x 3.2 and 3.2 x 2.5 mm Packages
RMS Period Jitter[1]
T_jitt
–
1.0
1.6
ps
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V
RMS Phase Jitter (random)
T_phj
–
0.235
0.275
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC
and -40 to 85ºC
–
0.235
0.320
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC
and -40 to 105ºC
–
0.1
–
ps
f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10GbE jitter
mask integration bandwidth = 1.875 MHz to 20 MHz, includes
spurs, all Vdd levels.
Notes:
3. Measured according to JESD65B
Rev 1.08
Page 6 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Table 6. Electrical Characteristics – HCSL
Parameter
Symbol
Min.
Typ.
Max.
Unit
Condition
Current Consumption
Idd
–
–
89
mA
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE Disable Supply Current
I_OE
–
–
58
mA
OE = Low
Output Disable Leakage Current
I_leak
–
0.15
–
A
OE = Low
I_driver
–
–
35
mA
Maximum average current drawn from OUT+ or OUT-
Current Consumption
Maximum Output Current
Output Characteristics
Output High Voltage
VOH
0.60
–
0.90
V
See Figure 4
Output Low Voltage
VOL
-0.05
–
0.08
V
See Figure 4
V_Swing
1.2
1.4
1.80
V
See Figure 5
Rise/Fall Time
Tr, Tf
–
360
465
ps
Measured with 2 pF capacitive loading to GND, 20% to 80%.
See Figure 5
RMS Period Jitter[4]
T_jitt
–
1.0
1.6
ps
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V
RMS Phase Jitter (random)
T_phj
–
0.220
0.270
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC
and -40 to 85ºC
–
0.220
0.300
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC
and -40 to 105ºC
–
0.1
–
ps
f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10GbE jitter
mask integration bandwidth = 1.875 MHz to 20 MHz, includes
spurs, all Vdd levels.
Output Differential Voltage Swing
Jitter – 7.0 x 5.0 mm Package
Jitter – 5.0 x 3.2 and 3.2 x 2.5 mm Packages
RMS Period Jitter[4]
T_jitt
–
1.0
1.6
ps
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3V or 2.5V
RMS Phase Jitter (random)
T_phj
–
0.230
0.275
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -20 to 70ºC
and -40 to 85ºC
–
0.230
0.340
ps
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdd levels, includes spurs. Temperature ranges -40 to 95ºC
and -40 to 105ºC
–
0.1
–
ps
f = 156.25 or 322.265625 MHz, IEEE802.3-2005 10GbE jitter
mask integration bandwidth = 1.875 MHz to 20 MHz, includes
spurs, all Vdd levels.
Notes:
4. Measured according to JESD65B
Table 7. Pin Description
Pin
1
Map
Top View
Functionality
[5]
Output Enable
(OE)
H : specified frequency output
L: output is high impedance
Non Connect
(NC)
H or L or Open: No effect on output frequency or other device
functions
OE/NC
OE/NC
1
6
VDD
NC
2
5
OUT-
GND
3
4
OUT+
No Connect; Leave it floating or connect to GND for better
heat dissipation
2
NC
NA
3
GND
Power
VDD Power Supply Ground
4
OUT+
Output
Oscillator output
5
OUT-
Output
Complementary oscillator output
6
VDD
Power
Power supply voltage
[6]
Figure 3. Pin Assignments
Notes:
5. In OE mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven.
6. A capacitor of value 0.1 µF or higher between VDD and GND is required. An additional 10 µF capacitor
between VDD and GND is required for the best phase jitter performance
Rev 1.08
Page 7 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Table 8. Absolute Maximum Ratings
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Min.
Max.
Unit
-0.5
4.0
V
Vdd + 0.3V
V
150
ºC
Maximum Junction Temperature
130
ºC
Soldering Temperature (follow standard Pb-free soldering guidelines)
260
ºC
Vdd
VIH
VIL
-0.3
Storage Temperature
-65
V
Table 9. Thermal Considerations[7]
Package
JA, 4 Layer Board (°C/W)
JC, Bottom (°C/W)
3225, 6-pin
80
30
5032, 6-pin
53
20
7050, 6-pin
52
19
Notes:
7. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table.
Table 10. Maximum Operating Junction Temperature[8]
Max Operating Temperature (ambient)
Maximum Operating Junction Temperature
70°C
95°C
85°C
110°C
95°C
120°C
105°C
130°C
Notes:
8. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 11. Environmental Compliance
Value
Unit
Mechanical Shock Resistance
Parameter
MIL-STD-883F, Method 2002
Test Conditions
10,000
g
Mechanical Vibration Resistance
MIL-STD-883F, Method 2007
70
g
Soldering Temperature (follow standard Pb free soldering guidelines)
MIL-STD-883F, Method 2003
260
°C
Moisture Sensitivity Level
MSL1 @ 260°C
Electrostatic Discharge (HBM)
HBM, JESD22-A114
2,000
V
Charge-Device Model ESD Protection
JESD220C101
750
V
Latch-up Tolerance
Rev 1.08
JESD78 Compliant
Page 8 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Waveform Diagrams
OUT-
VOH
OUT+
VOL
GND
Figure 4. LVPECL, Low-swing LVPECL, and HCSL Voltage Levels per Differential Pin (i.e. OUT+, or OUT-)
V
80%
80%
V_ Swing
0V
t
20%
20%
Tr
Tf
Figure 5. LVPECL, Low-swing LVPECL, and HCSL Voltage Levels Across Differential Pair (i.e. OUT+ minus OUT-)
Rev 1.08
Page 9 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Waveform Diagrams (continued)
OUT-
VOD
OUT+
VOS
GND
Figure 6. LVDS Voltage Levels per Differential Pin (i.e. OUT+, or OUT-)
V
80%
80%
0V
t
20%
20%
Tr
Tf
Figure 7. LVDS Differential Waveform (i.e. OUT+ minus OUT-)
Vdd
OE Voltage
Vdd
VIH
VIL
T_oe_hw
OE Voltage
T_oe_hw
OUT-
OUT-
90%
HZ
HZ
OUT+
OUT+
GND
GND
Figure 8. Hardware OE Enable Timing
Rev 1.08
Figure 9. Hardware OE Disable Timing
Page 10 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Termination Diagrams
LVPECL and Low-swing LVPECL
OUT+
Shunt Bias Termination
network
0.1μF
Zo = 50Ω
D+
OUT-
Zo = 50Ω
D-
LVPECL
0.1μF
RB
RB
VDD
50 Ω
50 Ω
RB
3.3 V 100 Ω
VT
2.5 V 48.7 Ω
Figure 10. LVPECL and Low-swing LVPECL with AC-coupled Termination
VDD
Thevenin-equivalent
Termination network
R1
LVPECL
R1
OUT+
Zo = 50Ω
D+
OUT-
Zo = 50Ω
D-
VDD
R1
R2
R2
3.3 V 127 Ω
82.5 Ω
2.5 V 250 Ω
62.5 Ω
R2
Figure 11. LVPECL and Low-swing LVPECL DC-coupled Load Termination with Thevenin Equivalent Network
Y-Bias Termination
network
LVPECL
OUT+
Zo = 50Ω
D+
OUT-
Zo = 50Ω
D-
R1
VDD
R1
R2
R3
3.3 V
50 Ω
50 Ω
50 Ω
2.5 V
50 Ω
50 Ω
18 Ω
C1
0.1μF
R2
R3
Figure 12. LVPECL and Low-swing LVPECL with Y-Bias Termination
Rev 1.08
Page 11 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Termination Diagrams (continued)
LVPECL and Low-swing LVPECL (continued)
OUT+
Shunt Bias Termination
network
Zo = 50Ω
D+
OUT-
Zo = 50Ω
D-
LVPECL
50 Ω
50 Ω
VT=VDD-2V
Figure 13. LVPECL and Low-swing LVPECL with DC-coupled Parallel Shunt Load Termination
Rev 1.08
Page 12 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Termination Diagrams (continued)
LVDS
LVDS
Zo = 50Ω
OUT+
OUT+
100 Ω
Zo = 50Ω
OUT-
OUT-
Figure 14. LVDS Single DC Termination at the Load
LVDS
0.1μF
Zo = 50Ω
OUT+
100 Ω
OUT+
100 Ω
0.1μF
Zo = 50Ω
OUT-
OUT-
Figure 15. LVDS double AC Termination with Capacitor Close to the Load
LVDS
Zo = 50Ω
OUT+
100 Ω
OUT-
OUT+
100 Ω
Zo = 50Ω
OUT-
Figure 16. LVDS Double DC Termination
Rev 1.08
Page 13 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Termination Diagrams (continued)
HCSL
R1
OUT+
OUT-
Zo = 50Ω
D+
Zo = 50Ω
D-
R2
50Ω
50Ω
R1 = R2 = 33 Ω
Figure 17. HCSL Interface Termination
Rev 1.08
Page 14 of 18
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Dimensions and Patterns ― 3.2 x 2.5 mm2
Package Size – Dimensions (Unit: mm)
[9]
Recommended Land Pattern (Unit: mm)
3.2 x 2.5 x 0.85 mm
[10]
3.2 x 2.5 x 0.85 mm
1.00
1.6
2.25
0.65
1.05
Dimensions and Patterns ― 5.0 x 3.2 mm2
Package Size – Dimensions (Unit: mm)
[9]
Recommended Land Pattern (Unit: mm)
5.0 x 3.2 x 0.85 mm[11]
[10]
5.0 x 3.2 x 0.85 mm[11]
Notes:
9. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the as sembly location of
the device.
10. A capacitor of value 0.1 µF or higher between VDD and GND is required. An additional 10 µF capacitor between VDD and GND is required for the
best phase jitter performance.
11. The center pad has no electrical function. Soldering down the center pad to the GND is recommended for best thermal dissipation, but is optional.
Rev 1.08
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Dimensions and Patterns ― 7.0 x 5.0 mm2
Package Size – Dimensions (Unit: mm)
7.0 x 5.0 x 0.85 mm
[12]
[14]
Recommended Land Pattern (Unit: mm)
7.0 x 5.0 x 0.85 mm
[13]
[14]
Notes:
12. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the as sembly location of
the device.
13. A capacitor of value 0.1 µF or higher between VDD and GND is required. An additional 10 µF capacitor between VDD and GND is required for the
best phase jitter performance.
14. The center pad has no electrical function. Soldering down the center pad to the GND is recommended for best thermal dissipation, but is optional.
Rev 1.08
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Additional Information
Table 12. Additional Information
Document
Description
Download Link
ECCN #: EAR99
Five character designation used on the
commerce Control List (CCL) to identify dual
use items for export control purposes.
—
HTS Classification Code:
8542.39.0000
A Harmonized Tariff Schedule (HTS) code
developed by the World Customs Organization
to classify/define internationally traded goods.
—
Part number Generator
Tool used to create the part number based on
desired features.
—
Manufacturing Notes
Tape & Reel dimension, reflow profile and
other manufacturing related info
http://www.sitime.com/manufacturing-notes
Qualification Reports
RoHS report, reliability reports,
composition reports
http://www.sitime.com/support/quality-and-reliability
Performance Reports
Additional performance data such as phase
noise, current consumption and jitter for
selected frequencies
http://www.sitime.com/support/performance-measurement-report
Termination Techniques
Termination design recommendations
http://www.sitime.com/support/application-notes
Layout Techniques
Layout recommendations
http://www.sitime.com/support/application-notes
Evaluation Boards
SiT6085/6EB rev. 3.0, SiT6085EB rev.3.1 and
SiT6097EB rev. 2.0 Evaluation Boards for
Differential Oscillators User Manual
https://www.sitime.com/support/user-guides
Rev 1.08
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SiT9365 Standard Frequency Ultra-low Jitter Differential Oscillator
Revision History
Table 13. Revision History
Revision
Release Date
1.0
09/06/2017
Change Summary
Final release
1.04
04/17/2018
Added 5032 package
Added -40 to 95C and -40 to 105C temperature ranges
Corrected minor errors|
Added Additional Information Table
1.05
07/03/2018
Performed minor edits and updated Ordering Information.
1.06
10/25/2018
Removed “Contact SiTime” for ±10 ppm
1.07
07/30/2019
Updated package Dimensions Drawings
Updated Table 9 Thermal Considerations for 5032 package
Updated Table 3 specification for First Year Aging
Added 5, 10, and 20 year aging specs
Added Evaluation Boards SiT6085EB reference in Table 12
Rearranged layout, added Description, Block Diagram and TOC
Tightened LVDS minimum VOD specification
Added HTS code
Added low-swing LVPECL package code and specifications
1.08
8/17/2019
Formatting changes
SiTime Corporation, 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA | Phone: +1-408-328-4400 | Fax: +1-408-328-4439
© SiTime Corporation 2017-2019. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage
or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect
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Rev 1.08
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