GT24C512B
Advanced
GT24C512B
2-WIRE
512K Bits
Serial EEPROM
Copyright © 2014 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without
notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment,
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are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
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GT24C512B
Table of Contents
1.
2.
3.
4.
Features ...................................................................................................................................................................... 3
General Description .............................................................................................................................................. 3
Functional Block Diagram ................................................................................................................................. 4
Pin Configuration.................................................................................................................................................... 5
4.1 8-Pin SOIC, TSSOP and MSOP ............................................................................................................. 5
4.2 8-Lead UDFN .......................................................................................................................................... 5
4.3 Pin Definition ........................................................................................................................................... 5
4.4 Pin Descriptions ...................................................................................................................................... 5
5. Device Operation.................................................................................................................................................... 6
5.1 2-WIRE Bus ............................................................................................................................................ 6
5.2 The Bus Protocol .................................................................................................................................... 6
5.3 Start Condition ........................................................................................................................................ 6
5.4 Stop Condition......................................................................................................................................... 6
5.5 Acknowledge ........................................................................................................................................... 6
5.6 Reset ....................................................................................................................................................... 6
5.7 Standby Mode ......................................................................................................................................... 6
5.8 Device Addressing .................................................................................................................................. 6
5.9 Write Operation ....................................................................................................................................... 7
5.10 Read Operation..................................................................................................................................... 8
5.11 ECC (Error Correction Code) and Write cycling ................................................................................... 8
5.12 Diagrams ............................................................................................................................................... 9
5.12 Timing Diagrams ................................................................................................................................. 12
6. Electrical Characteristics ............................................................................................................................... 13
6.1 Absolute Maximum Ratings .................................................................................................................. 13
6.2 Operating Range................................................................................................................................... 13
6.3 Capacitance .......................................................................................................................................... 13
6.4 Reliability ............................................................................................................................................... 13
6.5 DC Electrical Characteristic .................................................................................................................. 14
6.5 AC Electrical Characteristic .................................................................................................................. 15
7. Ordering Information.......................................................................................................................................... 16
8. Top Markings .......................................................................................................................................................... 17
8.1 SOIC Package ...................................................................................................................................... 17
8.2 TSSOP Package ................................................................................................................................... 17
8.3 UDFN Package ..................................................................................................................................... 17
9. Package Information .......................................................................................................................................... 18
9.1 SOIC ..................................................................................................................................................... 18
9.2 TSSOP .................................................................................................................................................. 19
9.3 UDFN .................................................................................................................................................... 20
10. Revision History ................................................................................................................................................. 21
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GT24C512B
1. Features
Two-Wire Serial Interface, I2CTM Compatible
–
Page write mode
–
Bi-directional data transfer protocol
Up to 128 bytes per page write
Wide-voltage Operation
Self timed write cycle with auto clear: 5ms (max.)
–
Filtered inputs for noise suppression
With ECC function
High-reliability
VCC = 1.7V to 5.5V
Speed: 1 MHz (1.7V)
Standby current (max.): 1 A, 1.7V
Operating current (max.): 1.5 mA, 1.7V
Hardware Data Protection
–
Write Protect Pin
–
–
Endurance: 4 million cycles
Data retention: 100 years
Industrial temperature grades
Sequential & Random Read Features
Packages: SOIC, TSSOP and UDFN
Memory organization: 65,536 x 8 bits
Lead-free, RoHS, Halogen free, Green
Page Size: 128 bytes
2. General Description
The GT24C512B are EEPROM devices that use the
Identification Page (128 bytes) which can be written and
industrial standard 2-wire interface for communications. The
(later) permanently locked in Read-only mode. This
GT24C512B contains a memory array of 512K-bits
Identification Page offers flexibility in the application board
(65,536x8), which is organized in 128-byte per page.
production line, as the Identification Page can be used to
The EEPROM can operate in a wide voltage range from
store unique identification parameters and/or parameters
1.7V to 5.5V which fits most application. This product can
specific to the production line.
provide a low-power 2-wire EEPROM solution. The device
Under no circumstance, the device will be hung up. In order
is offered in Lead-free, RoHS, halogen free or Green. The
to refrain the state machine entering into a wrong state
available package types are 8-pin SOIC, TSSOP and
during power-up sequence or a power toggle off-on
UDFN.
condition, a power on reset circuit is embedded. During
The GT24C512B is compatible with the industrial standard
power-up, the device does not respond to any instructions
2-wire bus protocol. If in case the bus is not responded, a
until the supply voltage (VCC) has reached an acceptable
new sent Op-code command will reset the bus and the
stable level above the reset threshold voltage. Once VCC
device will respond correctly. The simple bus consists of the
passes the power on reset threshold, the device is reset
Serial Clock wire (SCL) and the Serial Data wire (SDA).
and enters into the Standby mode. This would also avoid
Utilizing such bus protocol, a Master device, such as a
any inadvertent Write operations during power-up stage.
microcontroller, can usually control one or more Slave
During power-down process, the device will enter into
devices, alike this GT24C512B. The bit stream over the
standby mode, once VCC drops below the power on reset
SDA line includes a series of bytes, which identifies a
threshold voltage. In addition, the device will be in standby
particular Slave device, an instruction, an address within
mode after receiving the Stop command, provided that no
that Slave device, and a series of data, if appropriate. The
internal write operation is in progress. Nevertheless, it is
GT24C512B also has a Write Protect pin (WP) to allow
illegal to send a command unless the VCC is within its
blocking any write operations over specified memory area.
operating level.
The GT24C512B also offers an additional page, named the
s
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GT24C512B
3. Functional Block Diagram
8
SDA
5
SCL
6
WP
7
X DECODER
VCC
HIGH VOLTAGE
GENERATOR
TIMING &
CONTROL
CONTROL LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
1
A1
2
A2
3
WORD ADDRESS
COUNTER
ACK
Y DECODER
CLOCK
DI/O
GND 4
DATA REGISTER
nMOS
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GT24C512B
4. Pin Configuration
4.1 8-Pin SOIC, TSSOP and MSOP
4.2 8-Lead UDFN
Top View
Top View
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
GND
4
5
SDA
GND
4
5
SDA
4.3 Pin Definition
Pin No.
Pin Name
I/O
Definition
1
A0
I
Device Address Input
2
A1
I
Device Address Input
3
A2
I
Device Address Input
4
GND
-
Ground
5
SDA
I/O
6
SCL
I
Serial Clock Input
7
WP
I
Write Protect Input
8
VCC
-
Power Supply
Serial Address and Data input and Data out put
4.4 Pin Descriptions
SCL
single bus system. When A0, A1, and A2 are left floating,
This input clock pin is used to synchronize the data transfer
the inputs are defaulted to zero.
to and from the device.
WP
SDA
WP is the Write Protect pin. While the WP pin is connected
The SDA is a bi-directional pin used to transfer addresses
to the power supply of GT24C512B, the entire array
and data into and out of the device. The SDA pin is an open
becomes Write Protected (i.e. the device becomes Read
drain output and can be wired with other open drain or open
only). When WP is tied to Ground or left floating, the normal
collector outputs. However, the SDA pin requires a pull-up
write operations are allowed.
resistor connected to the power supply.
VCC
A0, A1, A2
Supply voltage
The A0, A1 and A2 are the device address inputs.
GND
Typically, the A0, A1, and A2 pins are for hardware
Ground of supply voltage
addressing and a total of 8 devices can be connected on a
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GT24C512B
5. Device Operation
The GT24C512B serial interface supports communications
2-wire bus transmission on is accidentally interrupted (e.g. a
using industrial standard 2-wire bus protocol, such as I2C.
power loss), or needs to be terminated mid-stream. The
5.1 2-WIRE Bus
reset is initiated when the Master device creates a Start
The two-wire bus is defined as Serial Data (SDA), and
condition. To do this, it may be necessary for the Master
Serial Clock (SCL). The protocol defines any device that
device to monitor the SDA line while cycling the SCL up to
sends data onto the SDA bus as a transmitter, and the
nine times. (For each clock signal transition to High, the
receiving devices as receivers. The bus is controlled by
Master checks for a High level on SDA.)
Master device that generates the SCL, controls the bus
5.7 Standby Mode
access, and generates the Start and Stop conditions. The
While in standby mode, the power consumption is minimal.
GT24C512B is the Slave device.
The GT24C512B enters into standby mode during one of
5.2 The Bus Protocol
the following conditions: a) After Power-up, while no
Data transfer may be initiated only when the bus is not busy.
Op-code is sent; b) After the completion of an operation and
During a data transfer, the SDA line must remain stable
followed by the Stop signal, provided that the previous
whenever the SCL line is high. Any changes in the SDA line
operation is not Write related; or c) After the completion of
while the SCL line is high will be interpreted as a Start or
any internal write operations.
Stop condition.
5.8 Device Addressing
The state of the SDA line represents valid data after a Start
The Master begins a transmission on by sending a Start
condition. The SDA line must be stable for the duration of
condition, then sends the address of the particular Slave
the High period of the clock signal. The data on the SDA line
devices to be communicated. The Slave device address is 8
may be changed during the Low period of the clock signal.
bits format as shown in Figure. 5-5.
There is one clock pulse per bit of data. Each data transfer
The four most significant bits of the Slave address are fixed
is initiated with a Start condition and terminated by a Stop
(1010) for GT24C512B.
condition.
The next three bits, A0, A1 and A2, of the Slave address are
5.3 Start Condition
specifically related to EEPROM. Up to eight GT24C512B
The Start condition precedes all commands to the device
units can be connected to the 2-wire bus.
and is defined as a High to Low transition of SDA when SCL
The last bit of the Slave address specifies whether a Read
is High. The EEPROM monitors the SDA and SCL lines and
or Write operation is to be performed. When this bit is set to
will not respond until the Start condition is met.
1, Read operation is selected. While it is set to 0, Write
5.4 Stop Condition
operation is selected.
The Stop condition is defined as a Low to High transition of
After the Master transmits the Start condition and Slave
SDA when SCL is High. All operations must end with a Stop
address byte appropriately, the associated 2-wire Slave
condition.
device, GT24C512B, will respond with ACK on the SDA line.
5.5 Acknowledge
Then GT24C512B will pull down the SDA on the ninth clock
After a successful data transfer, each receiving device is
cycle, signaling that it received the eight bits of data.
required to generate an ACK. The Acknowledging device
The GT24C512B then prepares for a Read or Write
pulls down the SDA line.
operation by monitoring the bus.
5.6 Reset
The GT24C512B contains a reset function in case the
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GT24C512B
5.9 Write Operation
can be initiated immediately. This involves issuing the Start
5.9.1 Byte Write
condition followed by the Slave address for a Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the GT24C512B. After
operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the GT24C512B has
completed the Write operation, an ACK will be returned and
the host can then proceed with the next Read or Write
operation.
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The GT24C512B acknowledges once
more and the Master generates the Stop condition, at which
time the device begins its internal programming cycle. While
this internal cycle is in progress, the device will not respond
to any request from the Master device.
5.9.2 Page Write
The GT24C512B is capable of 128-byte Page-Write
operation. A Page-Write is initiated in the same manner as a
Byte Write, but instead of terminating the internal Write
cycle after the first data word is transferred, the Master
device can transmit up to 127 more bytes. After the receipt
of each data word, the EEPROM responds immediately with
an ACK on SDA line, and the seven lower order data word
address bits are internally incremented by one, while the
higher order bits of the data word address remain constant.
If a byte address is incremented from the last byte of a page,
it returns to the first byte of that page. If the Master device
should transmit more than 128 bytes prior to issuing the
Stop condition, the address counter will “roll over,” and the
previously written data will be overwritten. Once all 128
bytes are received and the Stop condition has been sent by
the Master, the internal programming cycle begins. At this
point, all received data is written to the GT24C512B in a
single Write cycle. All inputs are disabled until completion of
the internal Write cycle.
5.9.3 Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
GT24C512B initiates the internal Write cycle. ACK polling
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GT24C512B
5.10 Read Operation
device terminates the sequential Read operation by pulling
Read operations are initiated in the same manner as Write
SDA High (no ACK) indicating the last data word to be read,
operations, except that the (R/W) bit of the Slave address is
followed by a Stop condition. The data output is sequential,
set to “1”. There are three Read operation options: current
with the data from address n followed by the data from
address read, random address read and sequential read.
address n+1,n+2 ... etc. The address counter increments by
5.10.1 Current Address Read
one automatically, allowing the entire memory contents to
The GT24C512B contains an internal address counter
which maintains the address of the last byte accessed,
incremented by one. When the EEPROM receives the
Slave Addressing Byte with a Read operation (R/W bit set
to “1”), it will respond an ACK and transmit the 8-bit data
byte stored at address location n+1. The Master should not
acknowledge the transfer but should generate a Stop
condition so the GT24C512B discontinues transmission.
The address “roll over” during read is from the last byte of
the last memory page, to the first byte of the first page. The
address “roll over” during write is from the last byte of the
current page to the first byte of the same page. (Refer to
Figure 5-8. Current Address Read Diagram.)
5.10.2 Random Address Read
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation by
sending the Start condition, Slave address and byte
address of the location it wishes to read. After the
GT24C512B acknowledges the byte address, the Master
device resends the Start condition and the Slave address,
this time with the R/W bit set to one. The EEPROM then
responds with its ACK and sends the data requested. The
Master device does not send an ACK but will generate a
Stop condition. (Refer to Figure 5-9. Random Address Read
Diagram.)
be serially read during sequential Read operation. When
the memory address boundary of the array is reached, the
address counter “rolls over” to address 0, and the device
continues to output data. (Refer to Figure 5-10. Sequential
Read Diagram).
5.11 ECC (Error Correction Code) and Write
cycling
The Error Correction Code (ECC) is an internal logic
function which is transparent for the I2C communication
protocol.
The ECC logic is implemented on each group of four
EEPROM bytes [1]. Inside a group, if a single bit out of the
four bytes happens to be erroneous during a Read
operation, the ECC detects this bit and replaces it with the
correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four
bytes, a single byte can be written independently. In this
case, the ECC function also writes the three other bytes
located in the same group [1]. As a consequence, the
maximum cycling budget is defined at group level and the
cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of
the same group must remain below the maximum value
defined in 6.4 Reliability.
Note: 1. A group of four bytes is located at addresses [4*N,
4*N+1, 4*N+2, 4*N+3], where N is an integer.
5.10.3 Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
GT24C512B sends the initial byte sequence, the Master
device now responds with an ACK indicating it requires
additional data from the GT24C512B. The EEPROM
continues to output data for each ACK received. The Master
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GT24C512B
5.12 Diagrams
Figure 5-1. Typical System Bus Configuration
VCC
SDA
SCL
Master
Transmitter/Receiver
GT24CXX
Figure 5-2. output Acknowledge
SCL from Master
1
8
9
Data Output from
Transmitter
TAA
Data Output from
Receiver
TAA
ACK
SDA
STOP
CONDITION
SCL
START
CONDITION
Figure 5-3. Start and Stop Conditions
s
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GT24C512B
Figure 5-4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 5-5. Slave Address
Bit
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
Device
Address
W
R
I
T
E
Figure 5-6. Byte Write
S
T
A
R
T
SDA
Bus
Activity
Word Address
A
C
K
M
S
B
Word Address
A
C
K
S
T
O
P
Data
A
C
K
A
C
K
L
M
S
S
B
B
R/W
Figure 5-7. Page Write
S
T
A
R
T
Device
Address
SDA
Bus
Activity
M
S
B
W
R
I
T
E Word Address(n) Word Address(n)
A
A
A
C
C
C
K
K
K
Data(n+1)
A
C
K
Data(n+127)
A
C
K
A
C
K
L
M
S
S
B
B
R/W
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S
T
O
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GT24C512B
Figure 5-8. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
S
T
O
P
Data
A
C
K
SDA
Bus
Activity
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 5-9. Random Address Read
S
T
A
R
T
W
R
I
T
E
Device
Address
SDA
Bus
Activity
Word
Address(n)
A
C
K
M
S
B
S
T
A
R
T
Word
Address(n)
A
C
K
Device
Address
R
E
A
D
A
C
K
S
T
O
P
Data n
A
C
K
N
O
L
S
B
R/W
A
C
K
DUMMY WRITE
Figure 5-10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
S
T
O
Data Byte n+x P
Data Byte n+2
A
C
K
A
C
K
N
O
R/W
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GT24C512B
5.12 Timing Diagrams
Figure 5-11. Bus Timing
TR
TF
THIGH
TLOW
TSU:STO
SCL
TSU:STA
THD:STA
TSU:DAT
THD:DAT
TBUF
SDAIN
TAA
TDH
SDAOUT
TSU:WP THD:WP
WP
Figure 5-12. Write Cycle Timing
SCL
SDA
ACK
Word n
TWR
STOP
Condition
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GT24C512B
6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VS
Supply Voltage
-0.5 to VCC + 1
V
VP
Voltage on Any Pin
–0.5 to VCC + 1
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Output Current
5
mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condition outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6.2 Operating Range
Range
Ambient Temperature (TA)
VCC
Industrial
–40°C to +85°C
1.7V to 5.5V
Note: Giantec offers Industrial grade for Commercial applications (0C to +70C).
6.3 Capacitance
Symbol
Parameter[1, 2]
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
CI/O
Input / Output Capacitance
VI/O = 0V
8
pF
Notes:
[1]
Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
[2]
6.4 Reliability
Ambient Temperature
(TA)
Ta=+25°C
Symbol
Parameter
Min.
Unit
End
Endurance
4 million
Program / Erase Cycles
DR
Data Retention
100
Years
[1]
Note: The write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer. The
Write cycle endurance is defined by characterization and qualification.
[2]
A Write cycle is executed when either a Page Write, a Byte write, a Write Identification Page or a Identification Page instruction is
decoded. When using the Byte Write, the Page Write or the Write Identification Page, refer also to 5.11 ECC (Error Correction Code) and Write
cycling
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GT24C512B
6.5 DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
Symbol
Parameter[1]
VCC
Test Conditions
Min.
Typ.
Max.
Unit
1.7
5.5
V
VCC
Supply Voltage
VIH
Input High Voltage
0.7*VCC
VCC+1
V
VIL
Input Low Voltage
-0.5
0.3* VCC
V
ILI
Input Leakage Current
5V
--
2
μA
ILO
Output Leakage Current
5V
--
2
μA
VIN = VCC max
VOL1
Output Low Voltage
1.7V
IOL = 0.15 mA
—
0.2
V
VOL2
Output Low Voltage
3V
IOL = 2.1 mA
—
0.4
V
ISB1
Standby Current
1.7V
VIN = VCC or GND
—
0.2
1
μA
ISB2
Standby Current
5.5V
VIN = VCC or GND
—
0.5
1
μA
ICC1
Read Current
1.7V
Read at 400KHz
—
0.5
mA
5.5V
Read at 1 MHz
1.0
mA
ICC2
Write Current
1.7V
Write at 1 MHz
1.0
mA
5.5V
Write at 1 MHz
1.2
mA
—
Note: The parameters are characterized but not 100% tested.
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GT24C512B
6.5 AC Electrical Characteristic
Industrial: TA = –40°C to +85°C, Supply voltage = 1.7V to 5.5V
Symbol
Parameter
[1] [2]
1.7VVCC
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