SLM8833
Ultracompact, 1.5 A Thermoelectric Cooler (TEC) Controller
GENERAL DESCRIPTION
FEATURES
The SLM8833 is a monolithic TEC controller with an
integrated TEC controller. It has a linear power stage
and a pulse-width modulation (PWM) power stage.
The linear controller works with the PWM driver to
control the internal power MOSFETs in an H-bridge
configuration. Depending on the control voltage at
the CONT input, the SLM8833 drives current
through a TEC to settle the temperature of a laser
diode or a passive component attached to the TEC
module to the programmed target temperature.
The control voltage applied to the CONT input pin is
generated by a digital-to-analog converter (DAC)
closing the digital proportional, integral, derivative
(PID) loop of temperature control system.
The internal 2.50 V reference voltage provides a 1%
accurate output that is used to bias a thermistor
temperature sensing bridge as well as a voltage
divider network to program the maximum TEC
current and voltage limits for both the heating and
cooling modes. It can also be a reference voltage for
the DAC and the temperature sensing circuit,
including a thermistor bridge and an analog-to-digital
converter (ADC).
Integrated super low RDSON MOSFETs for the
TEC controller
High efficiency single inductor architecture
TEC voltage and current operation monitoring
No external sense resistor required
Independent TEC heating and cooling current
limit settings
Programmable maximum TEC voltage
2.0 MHz PWM driver switching frequency
External synchronization
2.50 V reference output with 1% accuracy
Digital thermal control loop compatible
Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP
or in a 24-lead, 4 mm × 4 mm QFN
APPLICATIONS
TEC temperature control
Optical modules
Optical fiber amplifiers
Optical networking systems
Instruments requiring TEC temperature control
SYSTEM BLOCK DIAGRAM
Figure 1. TEC System Block Diagram
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
1
SLM8833
TYPICAL APPLICATION CIRCUIT
Figure 2. Typical Application Circuit with Digital PID Compensation in a Temperature Control Loop
Figure 3. TEC Controller in a Digital Temperature Control Loop (WLCSP)
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
2
SLM8833
PIN CONFIGURATION
Package
25-ball, 2.5 mm × 2.5 mm WLCSP
24-lead, 4 mm × 4 mm QFN
Pin Configuration
(Top View)
PIN DESCRIPTION
Pin No.
WLCSP
QFN
Pin Name
Description
A1, A2
A3 to
A5, B3,
B4
B1, B2
18, 19
PGNDL
Power Ground of the Linear TEC Controller.
1, 20
to 24
DNC
Do Not Connect. Don’t connect to pins.
17
LDR
B5
3
VLIM/SD
C1, C2
N/A1
PVIN
Output of the Linear TEC Controller.
Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage
limits. When this pin is pulled low, the device shuts down.
Power Input for the TEC Controller.
N/A1
16
PVINL
Power Input for the Linear TEC Driver.
N/A1
15
PVINS
Power Input for the PWM TEC Driver.
C3
11
ITEC
TEC Current Output.
C4
2
CONT
C5
4
ILIM
Current Limit. This pin sets the TEC cooling and heating current limits.
D1, D2
14
SW
Switch Node Output of the PWM TEC Controller.
D3
9
VTEC
D4
8
EN/SY
D5
5
VDD
TEC Voltage Output.
Enable/Synchronization. Set this pin high to enable the device. An external
synchronization clock input can be applied to this pin.
Power for the Controller Circuits.
E1, E2
12, 13
PGNDS
Power Ground of the PWM TEC Controller.
E3
10
SFB
Feedback of the PWM TEC Controller Output.
E4
7
AGND
Signal Ground.
E5
6
VREF
2.5 V Reference Output.
N/A1
0
EPAD
Exposed Pad. Solder to the analog ground plane on the board.
N/A1:
Control Input of the TEC Driver. Apply a control signal from the DAC to this
pin to close the thermal loop.
Not Available.
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
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SLM8833
ORDERING INFORMATION
Industrial Range: -40°C to +125°C
Order Part No.
SLM8833FA-7G
SLM8833EC
Package
25-ball, 2.5 mm × 2.5 mm WLCSP
24-lead, 4 mm × 4 mm QFN
QTY
500/Reel
1000/Reel
ABSOLUTE MAXIMUM RATINGS
PVIN to PGNDL / PGNDS (WLCSP)
PVINL to PGNDL; PBINS to PGNDS (QFN)
LDR to PGNDL (WLCSP)
LDR to PGNDL (QFN)
SW to PGNDS
SFB / VLIM/SD / ILIM /CONT/ EN/SY to AGND
AGND to PGNDL / PGNDS
VDD / ITEC / VTEC to AGND
VREF to AGND
Maximum Current
VREF to AGND
ITEC to AGND
VTEC to AGND
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TJ
Package Thermal
Resistance
Junction to Ambient, Rth-JA
Junction to Case, Rth-JC
ESD (HBM)
ESD (MM)
ESD (FICDM)
Latch-up
-0.3 V ~ 6.0 V
-0.3 V ~ 6.0 V
-0.3 V ~ VPVIN
-0.3 V ~ VPVINL
-0.3 V ~ 6.0 V
-0.3 V ~ VVDD
-0.3 V ~ 0.3 V
-0.3 V ~ 6.0 V
-0.3 V ~ 3 V
WLCSP
QFN
WLCSP
QFN
20 mA
50 mA
50 mA
150°C
-65°~+150°C
-40°C~+125°C
48 °C/w
37 °C/w
0.6 °C/w
1.65 °C/w
2000 V
200 V
1500 V
+/- 100 mA
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
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SLM8833
ELECTRICAL CHARACTERISTICS (TBD)
Test condition is VIN = 2.7 V to 5.5 V, TJ = −40°C ~ +125°C for minimum/maximum specifications, and T A = 25°C
for typical specifications, unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Power Supply
VPVIN
Driver Supply Voltage
2.7
5.5
V
VVDD
Controller Supply Voltage
2.7
5.5
V
IVDD
Supply Current
ISD
Shutdown Current
Under Voltage Lockout
Threshold
UVLO
Under Voltage Lockout
Hysteresis
Reference Voltage
VVREF
Reference Voltage
Linear Output
Output Voltage Low
VLDR
Output Voltage High
ILDR_SOURCE
ILDR_SINK
RDSON_PMOS
RDSON_NMOS
Maximum Source Current
Maximum Sink Current
P-MOSFET ON Resistance
(ILDR = 0.6 A)
N-MOSFET ON Resistance
(ILDR = 0.6 A)
PWM switching
EN/SY = AGND
or VLIM/SD = AGND
VVDD Rising
IVREF = 0 mA to 10 mA
12
mA
350
700
μA
2.45
2.55
2.65
V
80
90
100
mV
2.47
5
2.50
2.52
5
V
0
VPVIN
ILDR = 0 A
TJ = -40°C to +105°C
1.5
TJ = -40°C to +125°C
1.2
V
A
TJ = -40°C to +105°C
1.5
TJ = -40°C to +125°C
1.2
WLCSP, VPVIN = 5.0 V
28
35
WLCSP, VPVIN = 3.3 V
31
38
QFN, VPVIN = 5.0 V
50
65
QFN, VPVIN = 3.3 V
53
70
WLCSP, VPVIN = 5.0 V
21
30
WLCSP, VPVIN = 3.3 V
23
35
QFN, VPVIN = 5.0 V
37
55
QFN, VPVIN = 3.3 V
40
65
A
mΩ
mΩ
ILDR_P_LKG
P-MOSFET Leakage Current
0.1
10
μA
ILDR_N_LKG
N-MOSFET Leakage Current
0.1
10
μA
ALDR
Linear Amplifier Gain
ILDR_SH_GNDL
LDR Short-Circuit Threshold
LDR short to PGNDL, enter
hiccup
ILDR_SH_PVIN(L)
LDR Short-Circuit Threshold
LDR short to PVIN, enter hiccup
THICCUP
Hiccup Cycle
40
V/V
2.2
A
-2.2
A
15
ms
0.06 x
VPVIN
0.93 x
VPVIN
V
PWM Output
VSFB
ISW_SOURCE
Output Voltage Low
Output Voltage High
Maximum Source Current
ISFB = 0 A
TJ = -40°C to +105°C
1.5
TJ = -40°C to +125°C
1.2
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
A
5
SLM8833
ISW_SINK
RDSON_PMOS
RDSON_NMOS
Maximum Sink Current
P-MOSFET ON Resistance
(ILDR = 0.6 A)
N-MOSFET ON Resistance
(ILDR = 0.6 A)
TJ = -40°C to +105°C
1.5
TJ = -40°C to +125°C
1.2
WLCSP, VPVIN = 5.0 V
47
65
WLCSP, VPVIN = 3.3 V
60
80
QFN, VPVIN = 5.0 V
60
80
QFN, VPVIN = 3.3 V
70
95
WLCSP, VPVIN = 5.0 V
40
60
WLCSP, VPVIN = 3.3 V
45
65
QFN, VPVIN = 5.0 V
45
75
QFN, VPVIN = 3.3 V
55
85
A
mΩ
mΩ
ILDR_P_LKG
P-MOSFET Leakage Current
0.1
10
μA
ILDR_N_LKG
N-MOSFET Leakage Current
0.1
10
μA
tSW_R
SW Node Rise Time
DSW
PWM Duty Cycle
ISFB
SFB Input Bias Current
1
CSW = 1 nF
6
ns
93
%
1
2
μA
2.0
2.15
MHz
0.8
V
PWM Oscillator
fOSC
Internal Oscillator Frequency
VEN/SY_ILOW
EN/SY Input Voltage Low
VEN/SY_IHIGH
EN/SY Input Voltage High
External Synchronization
Frequency
Synchronization Pulse Duty
Cycle
EN/SY Rising to PWM Rising
Delay
fSYNC
DSYNC
tSYNC_PWM
tSY_LOCK
IEN/SY
IPULL-DOWN
1.85
2.1
V
1.85
3.25
MHz
10
90
%
50
ns
EN/SY Input Current
0.3
0.5
Cycl
es
μA
Pull-Down Current
0.3
0.5
μA
1.3
VVREF
– 0.2
V
0.2
1.2
V
EN/SY to PWM Lock Time
TEC Current Limit
ILIM Input Voltage Range
VILIMC
Cooling
ILIM Input Voltage Range
VILIMH
Heating
Current-Limit Threshold
VILIMC_TH
Cooling
Current-Limit Threshold
VILIMH_TH
Heating
IILIMH
ILIM Input Current Heating
IILIMC
ILIM Input Current Cooling
Cooling to Heating Current
ICOOL_HEAT_TH
Detection Threshold
TEC Voltage Limit
AVLIM
EN/SY high
Voltage Limit Gain
10
Number of SYNC cycles
VITEC = 0.5 V
1.98
2.0
2.02
V
VITEC = 2 V
0.48
0.5
0.52
V
+0.2
μA
42.5
μA
-0.2
Sourcing current
(VDRL - VSFB)/VVLIM
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
37.5
40
40
mA
2
V/V
6
SLM8833
VLIM
VLIM/SD Input Voltage Range
IILIMC
VLIM/SD Input Current Cooling
VOUT2 < VVREF/2
VLIM/SD Input Current Heating
VOUT2 > VVREF/2, sinking
current
IILIMH
0.2
VVDD/2
V
-0.2
+0.2
μA
12
μA
8
10
TEC Current Measurement (WLCSP)
0.52
5
0.52
5
VPVIN = 3.3 V
RCS
Current Sense Gain
VPVIN = 5 V
ILDR_ERROR
Current Measurement
Accuracy
VITEC_@_700m
A
VITEC_@_
-700mA
VITEC_@_800m
ITEC Voltage Accuracy
A
VITEC_@_
-800mA
700mA ≤ ILDR≤ 1 A, VPVIN =
3.3 V
800mA ≤ ILDR≤ 1 A, VPVIN =
5V
VPVIN = 3.3 V, cooling,
VVREF/2 + ILDR × RCS
VPVIN = 3.3 V, heating,
VVREF/2 - ILDR × RCS
VPVIN = 5 V, cooling, VVREF/2
+ ILDR × RCS
VPVIN = 5 V, heating, VVREF/2
- ILDR × RCS
V/A
V/A
-10
+10
%
-10
+10
%
1.59
7
0.84
6
1.65
7
0.78
3
1.61
8
0.88
3
1.67
8
0.82
2
1.64
9
0.89
1
1.71
8
0.83
6
V
V
V
V
TEC Current Measurement (QFN)
0.52
5
0.52
5
VPVIN = 3.3 V
RCS
Current Sense Gain
VPVIN = 5 V
ILDR_ERROR
Current Measurement
Accuracy
VITEC_@_700m
A
VITEC_@_
-700mA
VITEC_@_800m
ITEC Voltage Accuracy
A
VITEC_@_
-800mA
VITEC
VITEC_BIAS
IITEC_Max
700mA ≤ ILDR≤ 1 A, VPVIN =
3.3 V
800mA ≤ ILDR≤ 1 A, VPVIN =
5V
VPVIN = 3.3 V, cooling,
VVREF/2 + ILDR × RCS
VPVIN = 3.3 V, heating,
VVREF/2 - ILDR × RCS
VPVIN = 5 V, cooling, VVREF/2
+ ILDR × RCS
VPVIN = 5 V, heating, VVREF/2
- ILDR × RCS
ITEC Voltage Output Range
ITEC = 0 A
ITEC Bias Voltage
ILDR = 0 A
Maximum ITEC Output Current
V/A
V/A
-15
+15
%
-15
+15
%
1.37
4
0.75
0
1.41
9
0.70
5
1.61
8
0.88
3
1.67
8
0.83
0
1.86
1
1.01
5
1.92
1
0.95
5
VVREF
–
0.05
0
1.21
5
-2
1.25
0
0.24
1.47
5
0.00
5
1.22
5
-2
0.25
1.50
0
1.28
5
+2
V
V
V
V
V
V
mA
TEC Voltage Measurement
AVTEC
VVTEC_@_1_V
VVTEC
VVTEC_B
Voltage Sense Gain
Voltage Measurement
Accuracy
VLDR – VSFB = 1 V, VVREF/2 +
AVTEC × (VLDR – VSFB)
VTEC Output Voltage Range
VTEC Bias Voltage
Maximum VTEC Output
IVTEC_Max
Current
Internal Soft Start
VLDR = VSFB
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
1.25
0
0.26
1.52
5
2.62
5
1.27
5
+2
V/V
V
V
V
mA
7
SLM8833
tSS
Soft Start Time
80
VLIM/SD SHUTDOWN
VVLIM/SD_THL VLIM/SD Low Voltage
Threshold
Thermal SHUTDOWN
ms
0.07
V
TSHDN_TH
Thermal Shutdown Threshold
170
°C
TSHDN_HYS
Thermal Shutdown Hysteresis
17
°C
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
8
SLM8833
TYPICAL OPERATING CHARACTERISTICS
TA = 25°C, unless otherwise specified.
Figure 4. Efficiency vs. ITEC at VIN=3.3V in Cooling Mode
Figure 5. Efficiency vs. ITEC at VIN=3.3V in Heating Mode
Figure 6. Efficiency vs. ITEC at VIN=3.3V and 5.0V with 2Ω Load
in Cooling Mode
Figure 7. Efficiency vs. ITEC at VIN=3.3V and 5.0V with 2Ω Load in
Heating Mode
Figure 8. Soft Start into Cooling Mode (VIN=3.3V with 5Ω load)
Figure 9. Soft Start into Heating Mode (VIN=3.3V with 5Ω load)
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
9
SLM8833
Figure 10. Cooling to Heating Transient (Line 1: LDR (TEC+), Line
Figure 11. Zero Acrossing TEC Current Zoom-in from Heating to
2: SFB (TEC-), Line 4: ITEC)
Cooling (Line 1: LDR (TEC+), Line 2: SFB (TEC-), Line 4: ITEC)
Figure 12. Zero Acrossing TEC Current Zoom-in from Cooling to
Heating (Line 1: LDR (TEC+), Line 2: SFB (TEC-), Line 4: ITEC)
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
10
SLM8833
APPLICATION INFORMATION & WAVEFORMS
The SLM8833 is a single chip TEC controller that
sets and stabilizes a TEC temperature. A control
voltage from a DAC applied to the CONT input pin
of the SLM8833 corresponds to the temperature
setpoint of the target object attached to the TEC. .
The SLM8833 controls an internal FET H-bridge
whereby the direction of the current fed through the
TEC can be either positive (for cooling mode), to
pump heat away from the object attached to the
TEC, or negative (for heating mode), to pump heat
into the object attached to the TEC. Temperature is
measured with a thermal sensor attached to the
target object and the sensed temperature (voltage)
is fed back to an ADC to complete a closed digital
thermal control loop of the TEC. For the best overall
stability, couple the thermal sensor close to the TEC.
In most laser diode modules, a TEC and a NTC
thermistor are already mounted in the same package
to regulate the laser diode temperature.
The TEC is differentially driven in an H-bridge
configuration. The SLM8833 drives its internal
MOSFET transistors to provide the TEC current. To
provide good power efficiency and zero crossing
quality, only one side of the H-bridge uses a PWM
driver. Only one inductor and one capacitor are
required to filter out the switching frequency. The
other side of the H-bridge uses a linear output
without requiring any additional circuitry. This
proprietary configuration allows the SLM8833 to
provide efficiency of >90%. For most applications, a
1 μH inductor, a 10 μF capacitor, and a switching
frequency of 2 MHz maintain less than 1% of the
worst-case output voltage ripple across a TEC.
The maximum voltage across the TEC and the
current flowing through the TEC are set by using the
VLIM/SD and ILIM pins. The maximum cooling and
heating currents can be set independently to allow
asymmetric heating and cooling limits. For additional
details, see the Maximum TEC Voltage Limit section
and the Maximum TEC Current Limit section.
for the driver and internal reference. The PVIN input
power pins are combined for both the linear and the
switching driver. Apply the same input voltage to all
power input pins: VDD and PVIN. In some
circumstances, an RC lowpass filter can be added
optionally between the PVIN for the WLCSP (PVINS
and PVINL for the LFCSP) and VDD pins to prevent
high frequency noise from entering VDD, as shown
in Figure 3. The capacitor and resistor values are
typically 10 Ω and 100 nF, respectively. When
configuring power supply to the SLM8833, keep in
mind that at high current loads, the input voltage
may drop substantially due to a voltage drop on the
wires between the front-end power supply and the
PVIN for the WLCSP (PVINS and PVINL for the
LFCSP) pin. Leave a proper voltage margin when
designing the front-end power supply to maintain the
performance. Minimize the trace length from the
power supply to the PVIN for the WLCSP (PVINS
and PVINL for the LFCSP) pin to help mitigate the
voltage drop. The features internal automatic overvoltage protection, when output voltage is higher
than 115%.
ENABLE AND SHUTDOWN
To enable the SLM8833, apply a logic high voltage
to the EN/SY pin while the voltage at the VLIM/SD
pin is above the maximum shutdown threshold of
0.07 V. If either the EN/SY pin voltage is set to logic
low or the VLIM/SD voltage is below 0.07 V, the
controller goes into an ultralow current state. The
current drawn in shutdown mode is 350 μA typically.
Most of the current is consumed by the VREF circuit
block, which is always on even when the device is
disabled or shut down. The device can also be
enabled when an external synchronization clock
signal is applied to the EN/SY pin, and the voltage at
VLIM/SD input is above 0.07 V. Table 6 shows the
combinations of the two input signals that are
required to enable the SLM8833.
EN/SY Input
>2.1 V
Switching between
high >2.1 V and
low < 0.8 V
0.07 V
>0.07 V
Controller
Enabled
Enabled
No effect1
No effect1
≤0.07 V
Shutdown
Shutdown
Shutdown
1
No effect means this signal has no effect in shutting down or in
enabling the device.
OSCILLATOR CLOCK FREQUENCY
The SLM8834 has an internal oscillator that
generates a 2.0 MHz switching frequency for the
PWM output stage. This oscillator is active when the
enabled voltage at the EN/SY pin is set to a logic
11
SLM8833
level higher than 2.1 V and the VLIM/SD pin voltage
is greater than the shutdown threshold of 0.07 V.
External Clock Operation
The PWM switching frequency of the SLM883 can
be synchronized to an external clock from 1.85 MHz
to 3.25 MHz, applied to the EN/SY input pin as
shown on Figure 13.
Figure 13. Synchronize to an External Clock
Connecting Multiple SLM8833 Devices
Multiple SLM883 devices can be driven from a single
master clock signal by connecting the external clock
source to the EN/SY pin of each slave device. The
input ripple can be greatly reduced by operating the
SLM8834 devices 180° out of phase from each other
by placing an inverter at one of the EN/SY pins as
shown in Figure 14.
generates aramp with a typical 150 ms profile to
minimize inrush current during power-up. The
settling time and the final voltage across the TEC
depends on the TEC voltage required by the control
voltage of voltage loop. The higher the TEC voltage
is, the longer it requires to be built up.
When the SLM8833 is first powered up, the linear
side discharges the output of any prebias voltage.
As soon as the prebias is eliminated, the soft start
cycle begins. During the soft start cycle, both the
PWM and linear outputs track the internal soft start
ramp until they reach midscale, where the control
voltage, VC, is equal to the bias voltage, VB. From
the midscale voltage, the PWM and linear outputs
are then controlled by VC and diverge from each
other until the required differential voltage is
developed across the TEC or the differential voltage
reaches the voltage limit. The voltage developed
across the TEC depends on the control point at that
moment in time. Figure 15 shows an example of the
soft start in cooling mode. Note that, as both the
LDR and SFB voltages increase with the soft start
ramp and approach VB, the ramp slows down to
avoid possible current overshoot at the point where
the TEC voltage starts to build up.
Figure 15. Soft Start Profile in Cooling Mode
TEC VOLTAGE/CURRENT MONITOR
The TEC real-time voltage and current are
detectable at VTEC and ITEC, respectively.
Voltage Monitor
VTEC is an analog voltage output pin with a voltage
proportional to the actual voltage across the TEC. A
center VTEC voltage of 1.25 V corresponds to 0 V
across the TEC. Convert the voltage at VTEC and
the voltage across the TEC using the following
equation:
VVTEC = 1.25 V + 0.25 × (VLDR − VSFB)
Figure 14. Multiple SLM8833 Devices Driven from a Master Clock
SOFT START ON POWER-UP
The SLM8833 has an internal soft start circuit that
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
Current Monitor
ITEC is an analog voltage output pin with a voltage
proportional to the actual current through the TEC. A
center ITEC voltage of 1.25 V corresponds to 0 A
through the TEC. Convert the voltage at ITEC and
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SLM8833
the current through the TEC using the following
equations:
VITEC_COOLING = 1.25 V + ILDR × RCS
where the current sense gain (RCS) is 0.525 V/A.
VITEC_HEATING = 1.25 V − ILDR × RCS
limits in cooling and heating directions are set by
applying a voltage combination at the ILIM pin.
MAXIMUM TEC VOLTAGE LIMIT
The internal current sink circuitry connected to ILIM
draws a 40 μA current when the SLM8833 drives the
TEC in a cooling direction, which allows a high
cooling current. Use the following equations to
calculate the maximum TEC currents:
VILIM_HEATING = VREF × RC2/(RC1 +RC2)
where VREF = 2.5 V.
VILIM_COOLING = VILIM_HEATING + ISINK_ILIM × RC1||RC2
where ISINK_ILIM = 40 μA.
The maximum TEC voltage is set by applying a
voltage divider at the VLIM/SD pin to protect the
TEC. The voltage limiter operates bidirectionally and
allows the cooling limit to be different from the
heating limit.
Using a Resistor Divider to Set the TEC Voltage
Limit
Separate voltage limits are set using a resistor
divider. The internal current sink circuitry connected
to VLIM/SD draws a current when the SLM8833
drives the TEC in a heating direction, which lowers
the voltage at VLIM/SD. The current sink is not
active when the TEC is driven in a cooling direction;
therefore, the TEC heating voltage limit is always
lower than the cooling voltage limit.
Figure 16. Using a Resistor Divider to Set the TEC Voltage Limit
Using a Resistor Divider to Set the TEC Current
Limit
where RCS = 0.525 V/A.
VILIM_HEATING must not exceed 1.2 V and VILIM_COOLING
must be more than 1.3 V to leave proper margins
between the heating and the cooling modes.
Figure 17. Using a Resistor Divider to Set the TEC Current Limit
Calculate the cooling and heating limits using the
following equations:
VVLIM_COOLING = VREF × RV2/(RV1 +RV2)
where VREF = 2.5 V.
VVLIM_HEATING = VVLIM_COOLING − ISINK_VLIM × RV1//RV2
where ISINK_VLIM = 10 μA.
VTEC_MAX_COOLING = VVLIM_COOLING × AVLIM
where AVLIM = 2 V/V.
VTEC_MAX_HEATING = VVLIM_HEATING × AVLIM
MAXIMUM TEC CURRENT LIMIT
To protect the TEC, separate maximum TEC current
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
13
SLM8833
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 18. Classification Profile
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
14
SLM8833
PACKAGE INFORMATION
25-ball, 2.5 mm × 2.5 mm WLCSP
24-lead, 4 mm × 4 mm QFN
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
15
SLM8833
Revision History
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Page or Item
Subjects (major changes since previous revision)
Rev 0.2 datasheet, 2019-9-3
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New company logo released
Remove “Rev0.1 January 2019”
Copyright© 2019, Sillumin® Semiconductor Co., Ltd.
Rev0.2 September 2019
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