XT25Q16DDTIGT

1.8V Quad IO Serial Flash XT25Q16D XT25Q16D Quad IO Serial NOR Flash Datasheet 深圳市芯天下技术有限公司 XTX Technology Limited Tel: (+86) 755 28229862 Fax: (+86) 755 28229847 Web Site: http://www.xtxtech.com/ Technical Contact: fae@xtxtech.com * Information furnished is believed to be accurate and reliable. However, XTX Technology Limited assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of XTX Technology Limited. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. XTX Technology Limited products are not authorized for use as critical components in life support devices or systems without express written approval of XTX Technology Limited. The XTX logo is a registered trademark of XTX Technology Limited. All other names are the property of their respective own. Rev 1.0 Nov 30, 2020 Page 1 XT25Q16D 1.8V Quad IO Serial Flash Serial NOR Flash Memory 1.8V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase     16M-bit Serial Flash   2048K-bytes  256 bytes per programmable page Standard, Dual, Quad SPI, DTR  Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/RESET#  Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/RESET#  Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3  QPI: SCLK, CS#, IO0, IO1, IO2, IO3  SPI/QPI DTR(Double Transfer Rate) Read  Sector of 4K-bytes  Block of 32/64k-bytes    2*1024-Bytes Security Registers With OTP Lock  Support 128 bits Unique ID  Software/Hardware Write Protection  Write protect all/portion of memory via software  Enable/Disable protection with WP# Pin  Top or Bottom, Sector or Block selection  Package Options   See 1.1 Available Ordering OPN  All Pb-free packages are compliant RoHS, Halogen-Free and REACH. Rev 1.0 Industrial Level Temperature. (-40℃ to +85℃), MSL3  Industrial Plus Level Temperature. (-40℃ to +105℃), MSL3 Power Consumption Nov 30, 2020 0.3uA typical Deep Power-Down current Single Power Supply Voltage  Advanced security Features    Flexible Architecture  Temperature Range & Moisture Sensitivity Level 1.65~2.1V Endurance and Data Retention  Minimum 100,000 Program/Erase Cycle  20-year Data Retention typical High Speed Clock Frequency  108MHz for fast read with 30PF load  Dual I/O Data transfer up to 216Mbits/s  Quad I/O Data transfer up to 432Mbits/s  QPI Mode Data transfer up to 432Mbits/s  DTR Quad I/O Data transfer up to 688Mbits/s Program/Erase Speed  Page Program time: 0.35ms typical  Sector Erase time: 40ms typical  Block Erase time: 0.12/0.15s typical  Chip Erase time: 4.5s typical Page 2 1.8V Quad IO Serial Flash XT25Q16D CONTENTS 1. GENERAL DESCRIPTION........................................................................................................ 5 1.1. Available Ordering OPN .............................................................................................................................................. 5 1.2. Connection Diagram ................................................................................................................................................... 5 1.3. Pin Description ............................................................................................................................................................ 6 1.4. Block Diagram ............................................................................................................................................................. 6 1.5. Memory Description ................................................................................................................................................... 7 2. DEVICE OPERATION ............................................................................................................. 8 2.1. SPI Mode ..................................................................................................................................................................... 8 2.2. QPI Mode .................................................................................................................................................................... 8 2.3. DTR Read ..................................................................................................................................................................... 8 2.4. Hold Function .............................................................................................................................................................. 8 2.5. RESET Function............................................................................................................................................................ 9 2.6. The Reset Signaling Protocol (JEDEC 252) ................................................................................................................. 10 3. STATUS REGISTER .............................................................................................................. 11 4. DATA PROTECTION ............................................................................................................ 14 5. COMMANDS DESCRIPTION ................................................................................................ 16 5.1. Basic Setting .............................................................................................................................................................. 20 5.2. Memory Read............................................................................................................................................................ 24 5.3. Read Under DTR ........................................................................................................................................................ 32 5.4. Memory Program ...................................................................................................................................................... 36 5.5. Memory Erase ........................................................................................................................................................... 39 5.6. Security Register ....................................................................................................................................................... 43 5.7. Status Register .......................................................................................................................................................... 45 5.8. Deep Power Down .................................................................................................................................................... 47 5.9. Software Reset .......................................................................................................................................................... 50 5.10. Read ID .................................................................................................................................................................... 51 5.11. Advanced Data Protection ...................................................................................................................................... 56 5.12. Suspend ................................................................................................................................................................... 60 5.13. Wrap ........................................................................................................................................................................ 62 6. ELECTRICAL CHARACTERISTICS ........................................................................................... 70 6.1. Power-on Timing ....................................................................................................................................................... 70 6.2. Initial Delivery State .................................................................................................................................................. 70 6.3. Latch up Characteristics ............................................................................................................................................ 70 6.4. Absolute Maximum Ratings ...................................................................................................................................... 71 6.5. Capacitance Measurement Condition....................................................................................................................... 71 6.6. DC Characteristics ..................................................................................................................................................... 72 6.7. AC Characteristics ..................................................................................................................................................... 74 Rev 1.0 Nov 30, 2020 Page 3 1.8V Quad IO Serial Flash XT25Q16D 7. ORDERING INFORMATION ................................................................................................. 78 8. PACKAGE INFORMATION ................................................................................................... 79 8.1. Package SOP8 150MIL ............................................................................................................................................... 79 8.2. Package DFN8 (2x3x0.4) mm .................................................................................................................................... 80 9. REVISION HISTORY ............................................................................................................ 81 Rev 1.0 Nov 30, 2020 Page 4 XT25Q16D 1.8V Quad IO Serial Flash 1. GENERAL DESCRIPTION The XT25Q16D (16M-bit) Serial flash supports standard Serial Peripheral Interface (SPI), Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#/RESET#). The Dual I/O data is transferred with speed up to 216Mbits/s and the Quad I/O & Quad output data is transferred with speed up to 432Mbits/s. 1.1. Available Ordering OPN OPN Package Type Package Carrier XT25Q16DSOIGU SOP8 150mil Tube XT25Q16DSOIGT SOP8 150mil Tape & Reel XT25Q16DSOHGU SOP8 150mil Tube XT25Q16DDTIGT DFN8 2x3x0.4 mm Tape & Reel 1.2. Connection Diagram CS# 1 8 VCC SO(IO1) 2 7 HOLD#/RESET#(IO3) WP#(IO2) 3 6 SCLK VSS 4 5 SI(IO0) Top View 8-pin SOP CS# 8 VCC 1 SO(IO1) 2 7 HOLD#/RESET#(IO3) Top View 6 SCLK WP#(IO2) 3 5 SI(IO0) VSS 4 8-pin DFN Rev 1.0 Nov 30, 2020 Page 5 XT25Q16D 1.8V Quad IO Serial Flash 1.3. Pin Description Pin Name I/O Description CS# I SO (IO1) I/O Data Output (Data Input Output 1) WP# (IO2) I/O Write Protect Input (Data Input Output 2) Chip Select Input Ground VSS SI (IO0) I/O SCLK I HOLD#/RESET# (IO3) I/O Data Input (Data Input Output 0) Serial Clock Input Hold or Reset Input (Data Input Output 3) Power Supply VCC Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 – IO3 are used for Quad SPI instructions, WP# & HOLD# (or Reset#) functions are only available for Standard/Dual SPI. 1.4. Block Diagram Write Control Logic Status Register RESET#/ HOLD#(IO3) SCLK CS# SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Rev 1.0 Flash Memory Column Decode And 256-Byte Page Buffer SI(IO0) SO(IO1) Write Protect Logic And Row Decode WP#(IO2) Byte Address Latch/Counter Nov 30, 2020 Page 6 XT25Q16D 1.8V Quad IO Serial Flash 1.5. Memory Description Uniform Block/Sector Architecture Block(64K-byte) Block(32K-byte) 63 31 62 61 30 60 …… 3 1 2 1 0 0 Rev 1.0 Sector(4K-byte) Address Range 511 1FF000H 1FFFFFH …… …… …… 504 1F8000H 1F8FFFH 503 1F7000H 1F7FFFH …… …… …… 496 1F0000H 1F0FFFH 495 1EF000H 1EFFFFH …… …… …… 488 1E8000H 1E8FFFH 487 1E7000H 1E7FFFH …… …… …… 480 1E0000H 1E0FFFH …… …… …… …… …… …… …… …… …… 31 01F000H 01FFFFH …… …… …… 24 018000H 018FFFH 23 017000H 017FFFH …… …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… …… 8 008000H 008FFFH 7 007000H 007FFFH …… …… …… 0 000000H 000FFFH Nov 30, 2020 Page 7 1.8V Quad IO Serial Flash XT25Q16D 2. DEVICE OPERATION 2.1. SPI Mode Standard SPI The device features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI The device supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI The device supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”, “Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-volatile Quad Enable bit (QE) in Status Register to be set. 2.2. QPI Mode The device supports Quad Peripheral Interface (QPI) operations only when the device is switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at any given times. “Enable the QPI (38H)” and “Disable the QPI (FFH)” commands are used to switch between these two modes. Upon power-up and after software reset using “Enable Chip Reset (66H)” and “Reset (99H)” command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set. 2.3. DTR Read To effectively improve the read operation throughput without increasing the serial clock frequency, The device introduces multiple DTR (Double Transfer Rate) Read instructions that support Standard/Dual/Quad SPI and QPI modes. The byte-long instruction code is still latched into the device on the rising edge of the serial clock similar to all other SPI/QPI instructions. Once a DTR instruction code is accepted by the device, the address input and data output will be latched on both rising and falling edges of the serial clock. 2.4. Hold Function The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. Rev 1.0 Nov 30, 2020 Page 8 XT25Q16D 1.8V Quad IO Serial Flash Hold Condition CS# SCLK HOLD# HOLD HOLD 2.5. RESET Function The RESET# pin allows the device to be reset by the control. The pin7 can be configured as a RESET# pin depending on the status register setting, which need QE=0 and HOLD/RST=1. The RESET# pin goes low for a period of tRLRH or longer will reset the flash. After reset cycle, the flash is at the following states: - Standby mode. - All the volatile bits will return to the default status as power on. Reset Timing CS# tRB RESET# tRLRH Symbol tRLRH tRHSL tRB Rev 1.0 tRHSL Min 1 200 Parameter Reset Pulse Width Reset High Time Before Read Reset Recovery Time Typ Max 1 Nov 30, 2020 Unit. us us ms Page 9 XT25Q16D 1.8V Quad IO Serial Flash 2.6. The Reset Signaling Protocol (JEDEC 252) The protocol consists of two phases: reset request, and completion (a device internal reset). Reset Request 1. CS# is driven active low to select the SPI slave (Note1) 2. Clock (SCK) remains stable in either a high or low state (Note 2) 3. SI / IO0 is driven low by the bus master, simultaneously with CS# going active low, (Note 3) 4. CS# is driven inactive (Note 4). Repeat the steps 1-4 each time alternating the state of SI (Note 5). NOTE 1 This powers up the SPI slave. NOTE 2 This prevents any confusion with a command, as no command bits are transferred (clocked). NOTE 3 No SPI bus slave drives SI during CS# low before a transition of SCK, i.e., slave streaming output active is not allowed until after the first edge of SCK. NOTE 4 The slave captures the state of SI on the rising edge of CS#. NOTE 5 SI is low on the first CS#, high on the second, low on the third, high on the fourth (This provides a 5h pattern, to differentiate it from random noise). Reset Completion After the fourth CS# pulse, the slave triggers its internal reset. Timing Diagram and Timing Parameters tCSL Figure 1. Reset Signaling Protocol tCSH CS# Mode 3 SCLK Mode 0 SI SO High Z 200us Internal Reset Rev 1.0 Device is Ready Nov 30, 2020 Page 10 XT25Q16D 1.8V Quad IO Serial Flash 3. STATUS REGISTER S23 Hold/RST S22 DRV1 S21 DRV0 S20 Reserved S19 Reserved S18 WPS S17 LC S16 Reserved S15 SUS1 S14 CMP S13 Reserved S12 LB2 S11 LB1 S10 SUS2 S9 QE S8 SRP1 S7 SRP0 S6 BP4 S5 BP3 S4 BP2 S3 BP1 S2 BP0 S1 WEL S0 WIP HOLD/RST The HOLD/RST bit is used to determine whether HOLD# or RESET# function should be implemented on the hardware pin for 8-pin packages. When HOLD/RST=0, the pin acts as HOLD#, When the HOLD/RST=1, the pin acts as RESET#. However, the HOLD# or RESET# function are only available when QE=0, If QE=1, The HOLD# and RESET# functions are disabled, the pin acts as dedicated data I/O pin. DRV1, DRV0 The Output Driver Strength (DRV1 & DRV0) bits are used to determine the output driver strength for the Read operations. DRV1 DRV0 Driver Strength 0 0 25% 0 1 50% 1 0 75% (default) 1 1 100% WPS The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the combination of CMP, BP (4:0) bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon device power on or after reset. Rev 1.0 Nov 30, 2020 Page 11 1.8V Quad IO Serial Flash XT25Q16D LC The Latency Code (LC) selects the mode and number of dummy cycles between the end of address and the start of read data output for command 0DH under QPI mode and command EDH under SPI/QPI modes. Some read commands send mode bits following the address to indicate that the next command will be of the same type with an implied, rather than an explicit instruction. The next command thus does not provide an instruction Byte, only a new address and mode bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of commands. Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before data can be returned to the host system. Some read commands require additional latency cycles as the SCLK frequency is increased. Latency Code and DTR Mode Frequency Table LC Dummy Clock Cycles 0 1 8 (Default) 6 SUS1, SUS2 The SUS1 and SUS2 bits are read only bits in the status register (S15 and S10) that are set to 1 after executing an Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1,and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command, software reset (66H+99H) command as well as a power-down, power-up cycle. CMP The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4BP0 bits to provide more flexibility for the array protection. Please see the Status register Memory Protection table for details. The default setting is CMP=0. LB1, LB2 The LB1, LB12 bits are non-volatile One Time Program (OTP) bits in Status Register (S11-S12) that provide the write protect control and status to the Security Registers. The default state of LB1-LB2 are 0, the security registers are unlocked. The LB1-LB2 bits can be set to 1 individually using the Write Register instruction. The LB1-LB2 bits are One Time Programmable, once its set to 1, the Security Registers will become read-only permanently. QE The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground). Rev 1.0 Nov 30, 2020 Page 12 XT25Q16D 1.8V Quad IO Serial Flash SRP1, SRP0 The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the type of write protection: software protection, hardware protection, power supply lockdown or one-time programmable protection. SRP1 SRP0 WP# Status Register Description 0 0 X Software Protected The Status Register can be written to after a Write Enable command, WEL=1. (Default) 0 1 0 Hardware Protected WP#=0, the Status Register locked and cannot be written to. 0 1 1 Hardware Unprotected WP#=1, the Status Register is unlocked and can be written to after a Write Enable command, WEL=1. 1 0 X Power Supply LockDown Status Register is protected and cannot be written to again Note 1 until the next Power-Down, Power-Up cycle. 1 1 X One-Time Program Note 2 Status Register is protected and cannot be written to. NOTE: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available on special order. Please contact XTX for details. BP4, BP3, BP2, BP1, BP0 The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table 1.0 & 1.1) becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect(BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, BP0) bits are 0 and CMP=0 or the Block Protect (BP2, BP1, BP0) bits are 1 and CMP=1. WEL The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. WIP The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. Rev 1.0 Nov 30, 2020 Page 13 XT25Q16D 1.8V Quad IO Serial Flash 4. DATA PROTECTION The device provide the following data protection methods:  Write Enable (WREN) command: The WREN command sets the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation:   Power-Up / Software reset (66H+99H)  Write Disable (WRDI)  Write Status Register (WRSR)  Page Program (PP)  Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)  Erase Security Register / Program Security Register Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits, WPS bit and CMP bit define the section of the memory array that can be read but cannot be changed.  Hardware Protection Mode: WP# goes low to prevent writing status register.  Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command (ABH) and software reset (66H+99H). Table1.0 XT25Q16D Protected area size (WPS=0, CMP=0) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 31 1F0000H-1FFFFFH 64KB Upper 1/32 0 0 0 1 0 30 to 31 1E0000H-1FFFFFH 128KB Upper 1/16 0 0 0 1 1 28 to 31 1C0000H-1FFFFFH 256KB Upper 1/8 0 0 1 0 0 24 to 31 180000H-1FFFFFH 512KB Upper 1/4 0 0 1 0 1 16 to 31 100000H-1FFFFFH 1M Upper 1/2 0 1 0 0 1 0 000000H-00FFFFH 64KB Lower 1/32 0 1 0 1 0 0 to 1 000000H-01FFFFH 128KB Lower 1/16 0 1 0 1 1 0 to 3 000000H-03FFFFH 256KB Lower 1/8 0 1 1 0 0 0 to 7 000000H-07FFFFH 512KB Lower 1/4 0 1 1 0 1 0 to 15 000000H-0FFFFFH 1M Lower 1/2 X X 1 1 X 0 to 31 000000H-1FFFFFH 2M ALL 1 0 0 0 1 31 1FF000H-1FFFFFH 4KB Top Block 1 0 0 1 0 31 1FE000H-1FFFFFH 8KB Top Block 1 0 0 1 1 31 1FC000H-1FFFFFH 16KB Top Block 1 0 1 0 X 31 1F8000H-1FFFFFH 32KB Top Block 1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block 1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block 1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block 1 1 1 0 X 0 000000H-007FFFH 32KB Bottom Block Rev 1.0 Nov 30, 2020 Page 14 XT25Q16D 1.8V Quad IO Serial Flash Table1.1 XT25Q16D Protected area size (WPS=0, CMP=1) Status Register Content Memory Content BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion X X 0 0 0 0 to 31 000000H-1FFFFFH 2M ALL 0 0 0 0 1 0 to 30 000000H-1EFFFFH 1984KB Lower 31/32 0 0 0 1 0 0 to 29 000000H-1DFFFFH 1920KB Lower 15/16 0 0 0 1 1 0 to 27 000000H-1BFFFFH 1792KB Lower 7/8 0 0 1 0 0 0 to 23 000000H-17FFFFH 1536KB Lower 3/4 0 0 1 0 1 0 to 15 000000H-0FFFFFH 1M Lower 1/2 0 1 0 0 1 1 to 31 010000H-1FFFFFH 1984KB Upper 31/32 0 1 0 1 0 2 to 31 020000H-1FFFFFH 1920KB Upper 15/16 0 1 0 1 1 4 to 31 040000H-1FFFFFH 1792KB Upper 7/8 0 1 1 0 0 8 to 31 080000H-1FFFFFH 1536KB Upper 3/4 0 1 1 0 1 16 to 31 100000H-1FFFFFH 1M Upper 1/2 X X 1 1 X NONE NONE NONE NONE 1 0 0 0 1 0 to 31 000000H-1FEFFFH 2044KB Lower 511/512 1 0 0 1 0 0 to 31 000000H-1FDFFFH 2040KB Lower 255/256 1 0 0 1 1 0 to 31 000000H-1FBFFFH 2032KB Lower 127/128 1 0 1 0 X 0 to 31 000000H-1F7FFFH 2016KB Lower 63/64 1 1 0 0 1 0 to 31 001000H-1FFFFFH 2044KB Upper 511/512 1 1 0 1 0 0 to 31 002000H-1FFFFFH 2040KB Upper 255/256 1 1 0 1 1 0 to 31 004000H-1FFFFFH 2032KB Upper 127/128 1 1 1 0 X 0 to 31 008000H-1FFFFFH 2016KB Upper 63/64 Table1.2 XT25Q16D Individual Block Protection (WPS=1) Block 31 Sector Individual Block Lock Operation Address range 511 1FF000H 1FFFFFH …… …… …… 496 1F0000H 1F0FFFH …… …… 2 1 0 Rev 1.0 15 00F000H 00FFFFH …… …… …… 0 000000H 000FFFH Nov 30, 2020 The Top/Bottom block is protected by sector. Other 30 Blocks are protected by block Block Lock: 36H+Address Block Unlock: 39H+Address Read Block Lock: 3DH+Address Global Block Lock: 7EH Global Block Unlock: 98H Page 15 XT25Q16D 1.8V Quad IO Serial Flash 5. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 2, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable or Write Disable command, CS# must be driven high exactly at the byte boundary, otherwise the command is rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table 2. Commands Command Name SPI QPI Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 n-Bytes 03H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) (continuous) 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous) Basic Setting Enable QPI √ 38H Write Enable √ √ 06H Write Enable For Volatile √ √ 50H Write Disable Continous Read Reset / Disable QPI Memory Read √ √ 04H √ √ FFH Normal Read √ Fast Read √ √ Dual Output Fast Read √ 3BH A23-A16 Dual I/O Fast Read √ BBH A23-A8 Quad Output Fast Read √ 6BH Quad I/O Fast Read √ Quad I/O Word Fast Read √ A23-A16 A23-A0 (4) M7-M0 A23-A0 (4) M7-M0 √ EBH E7H (2) A15-A8 A7-A0 (2) M7-M0 A15-A8 A7-A0 (D7-D0) dummy (D7-D0) (1) (1) A7-A0 (continuous) (continuous) dummy (D7-D0) (3) (continuous) dummy (5) (D7-D0) (3) (continuous) dummy (6) (D7-D0) (3) (continuous) Read Under DTR DTR Fast Read √ √ 0DH DTR Fast Read Dual I/O √ DTR Fast Read Quad I/O √ √ EDH √ √ 02H BDH A23-A16 A15-A8 A7-A0 Dummy (D7-D0) A23-A16 A15-A8 A7-A0 M7-M0 Dummy (D7-D0) A23-A16 A15-A8 A7-A0 M7-M0 Dummy (D7-D0) A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) Memory Program Page Program Quad Page Program √ 32H A23-A16 A15-A8 A7-A0 (D7-D0) (3) Memory Erase Sector Erase √ √ 20H A23-A16 A15-A8 A7-A0 32k Block Erase √ √ 52H A23-A16 A15-A8 A7-A0 64k Block Erase √ √ D8H A23-A16 A15-A8 A7-A0 Rev 1.0 Nov 30, 2020 Page 16 XT25Q16D 1.8V Quad IO Serial Flash Chip Erase √ √ 60H/C7H Security Register Read Security Register (8) Program Security Register Erase Security Register (8) (8) √ 48H A23-A16 A15-A8 A7-A0 dummy (D7-D0) √ 42H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) √ 44H A23-A16 A15-A8 A7-A0 Status Register Read Status Register 1 √ √ 05H (S7-S0) (continuous) Read Status Register 2 √ √ 35H (S15-S8) (continuous) (continuous) Read Status Register 3 √ √ 15H (S23-S16) Write Status Register 1 √ √ 01H (S7-S0) (continuous) Write Status Register 2 √ √ 31H (S15-S8) (continuous) Write Status Register 3 √ √ 11H (S23-S16) (continuous) Deep Power-Down Release From Deep PowerDown Release From Deep PowerDown, And Read Device ID Software Reset √ √ B9H √ √ ABH √ √ ABH Enabale Reset √ √ 66H Reset √ √ 99H Read Manufacture ID Read Manufacture ID Dual I/O Read Manufacture ID Quad I/O Read JEDEC ID √ √ 90H dummy √ 92H A23-A8 √ 94H √ √ Read Unique ID √ Read SFDP Deep Power-Down Read ID dummy A7-A0, M[7:0] 9FH A23-A0, M[7:0] (M7-M0) (D15-D8) 00H (M7-M0) (D7-D0) (M7-M0) (D7-D0) (D7-D0) √ 4BH dummy dummy dummy dummy (D7-D0) (continuous) √ √ 5AH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous) Single Block Lock √ √ 36H A23-A16 A15-A8 A7-A0 Single Block Unlock √ √ 39H A23-A16 A15-A8 A7-A0 Read Block Lock √ √ 3DH A23-A16 A15-A8 A7-A0 Global Block Lock √ √ 7EH Global Block Unlock √ √ 98H Program Erase Suspend √ √ 75H/B0H Program Erase Resume √ √ 7AH/30H 77H dummy dummy dummy W6-W4 A15-A8 A7-A0 dummy dummy (M7-M0) (D7-D0) (continuous) (continuous) (continuous) Advanced Data Protection Suspend Wrap Set Burst With Wrap √ Set Read Parameters √ C0H P7-P0 Burst Read With Wrap √ 0CH A23-A16 Rev 1.0 Nov 30, 2020 (D7-D0) Page 17 1.8V Quad IO Serial Flash XT25Q16D NOTE: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8,A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9,A7, A5, A3, A1, M7, M5, M3, M1 3. Quad Output Data IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3, …..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Quad I/O Fast Read Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Quad I/O Word Fast Read Data IO0 = (x, x, D4, D0,…) IO1 = (x, x, D5, D1,…) IO2 = (x, x, D6, D2,…) IO3 = (x, x, D7, D3,…) 7. Quad I/O Word Fast Read Data: the lowest address bit must be 0. 8. Security Registers Address: Security Register1: A23-A16=00H, A15-A8=10H, A7-A0= Byte Address; Security Register2: A23-A16=00H, A15-A8=20H, A7-A0= Byte Address; 9. QPI Command, Address, Data input/output format: CLK# = 0 1 2 3 4 5 6 7 8 9 10 11 IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0 IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1 IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2 IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D4 10. QPI mode: Release from Deep Power-Down, And Read Device ID (ABH) N dummy cycles should be inserted before ID read cycle, refer to C0H command 11. QPI mode: Manufacturer/Device ID (90H) N dummy cycles should be inserted before ID read cycle, refer to C0H command Rev 1.0 Nov 30, 2020 Page 18 XT25Q16D 1.8V Quad IO Serial Flash Table of ID Definitions: XT25Q16D Operation Code M7-M0 ID15-ID8 9FH 0B 60 90H 0B 15 14 ABH Rev 1.0 ID7-ID0 14 Nov 30, 2020 Page 19 1.8V Quad IO Serial Flash XT25Q16D 5.1. Basic Setting 5.1.1. Enable QPI(38H) The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can switch the device from SPI mode to QPI mode. See the command Table 2a for all support QPI commands. In order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first, and “Enable QPI (38H)” command must be issued. If the QE bit is 0, the “Enable QPI (38H)” command will be ignored and the device will remain in SPI mode. When the device is switched from SPI mode to QPI mode, the existing Write Enable Latch and the Wrap Length setting will remain unchanged. Figure 2. Enable QPI mode command Sequence Diagram CS 0 1 2 3 4 5 6 7 SCLK Command SI 38H SO High-Z 5.1.2. Write Enable(06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Program Security Register, Erase Security Register and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low -> Sending the Write Enable command -> CS# goes high. Figure 3.Write Enable Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 06H High-Z SO Figure 3a. Write Enable Sequence Diagram (QPI) CS# 0 1 SCLK 06H SI(IO0) 0 0 SO(IO1) 0 1 WP#(IO2) 0 1 0 0 HOLD#(IO3) Rev 1.0 Nov 30, 2020 Page 20 1.8V Quad IO Serial Flash XT25Q16D 5.1.3. Write Enable for Volatile Status Register (50H) The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical nonvolatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command and any other commands can't be inserted between them. Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values. Figure 4.Write Enable for Volatile Status Register Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 50H High-Z SO Figure 4a. Write Enable for Volatile Status Register Sequence Diagram (QPI) CS# 0 1 SCLK 50H SI(IO0) 1 0 SO(IO1) 0 0 WP#(IO2) 1 0 0 0 HOLD#(IO3) Rev 1.0 Nov 30, 2020 Page 21 1.8V Quad IO Serial Flash XT25Q16D 5.1.4. Write Disable(04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low ->Sending the Write Disable command ->CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. Figure 5. Write Disable Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 04H High-Z SO Figure 5a. Write Disable Sequence Diagram (QPI) CS# 0 1 SCLK 04H SI(IO0) 0 0 SO(IO1) 0 0 WP#(IO2) 0 1 0 0 HOLD#(IO3) Rev 1.0 Nov 30, 2020 Page 22 1.8V Quad IO Serial Flash XT25Q16D 5.1.5. Continuous Read Mode Reset / Disable QPI (FFH) The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce command overhead. By setting the (M7-0) to “AXH”, the next Dual/Quad I/O Fast Read operations do not require the BBH/EBH/E7H/BDH/EDH command code. Because the device has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the device will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the Continuous Read Mode from the “AXH” state and allow standard SPI command to be recognized. Figure 6. Continuous Read Mode Reset Sequence Diagram Mode Bit Reset for Quad/ Dual I/O CS# 0 1 2 3 4 5 6 7 SCLK SI(IO0) FFH SO(IO1) Don’t care WP#(IO2) Don’t care HOLD#(IO3) Don’t care Disable QPI (FFH) To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must be issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and the Wrap Length setting will remain unchanged. When the device is in QPI mode, the first FFH command will exit continuous read mode and the second FFH command will exit QPI mode. Figure 6a. Disable QPI mode command Sequence Diagram CS# 0 1 SCLK FFH SI(IO0) 1 1 SO(IO1) 1 1 WP#(IO2) 1 1 1 1 HOLD#(IO3) Rev 1.0 Nov 30, 2020 Page 23 XT25Q16D 1.8V Quad IO Serial Flash 5.2. Memory Read 5.2.1. Normal Read (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 7.Read Data Bytes Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SCLK Command SI 24-bit address(A23:A0) 03H 23 22 21 20 19 MSB High-Z SO 7 6 5 4 3 2 1 0 Data Out1 MSB Data Out2 7 6 5 4 3 2 1 0 5.2.2. Fast Read (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. Figure 8. Read Data By test Higher Speed Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 0BH 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 Data Out1 SO Data Out3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB Rev 1.0 Data Out2 Nov 30, 2020 Page 24 XT25Q16D 1.8V Quad IO Serial Flash Fast Read (0BH) in QPI mode The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. Figure 8a. Read Data Bytes at Higher Speed Sequence Diagram (QPI) CS# 0 2 1 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 SCLK 0BH 24-bit address(A23:A0) SI(IO0) 0 1 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 0 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 0 0 6 2 6 2 6 2 6 2 6 2 6 2 0 1 3 7 3 7 3 7 MSB MSB MSB HOLD#(IO3) A23-A16 A15-A8 A7-0 7 Dummy* 3 Byte1 7 MSB 3 Byte2 7 3 Byte3 *Set Read Parameters Command (C0H) can set the number of dummy cycles 5.2.3. Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in the following figure. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. Figure 9. Dual Output Fast Read Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 3BH 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 SO 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 MSB MSB MSB MSB Data Out1 Rev 1.0 Data Out2 Nov 30, 2020 Data Out3 6 Data Out4 7 Page 25 XT25Q16D 1.8V Quad IO Serial Flash 5.2.4. Dual I/O Fast Read(BBH) The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in the following figure. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. Figure 10. Dual I/O Fast Read Sequence Diagram (M5-4≠(1,0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Command SI(IO0) BBH 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 MSB MSB SO(IO1) 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 M7-0 A7-0 A15-8 A23-16 CS# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Byte6 Byte5 Byte4 Byte3 Byte2 Dual I/O Fast Read with “Continuous Read Mode” The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5- 4) =(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command sequence is shown in Figure11. If the “Continuous Read Mode” bits (M5- 4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5- 4) before issuing normal command. Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4=(1,0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI(IO0) 22 20 18 16 14 12 10 SO(IO1) 23 21 19 17 15 13 11 8 6 4 2 0 6 4 2 MSB 0 MSB A23-16 9 7 5 3 1 7 5 3 A7-0 A15-8 1 M7-0 CS# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 Byte1 Rev 1.0 Byte2 Nov 30, 2020 Byte3 Byte4 Page 26 XT25Q16D 1.8V Quad IO Serial Flash 5.2.5. Quad Output Fast Read(6BH) The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. Figure 13. Quad Output Fast Read Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI(IO0) 6BH 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB High-Z SO(IO1) High-Z WP#(IO2) High-Z HOLD#(IO3) CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8 Rev 1.0 Nov 30, 2020 Page 27 XT25Q16D 1.8V Quad IO Serial Flash 5.2.6. Quad I/O Fast Read(EBH) The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4 dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in the figure below. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. Figure 12. Quad I/O Fast Read Sequence Diagram (M5-4≠(1,0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Command SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 3 7 EBH HOLD#(IO3) A23-16 A15-8 A7-0 M7-0 Byte1 Byte2 Dummy Quad I/O Fast Read with “Continuous Read Mode” The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) =(1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The command sequence is shown in Figure12a. If the “Continuous Read Mode” (M5- 4) do not equal (1, 0), the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5- 4) before issuing normal command. Figure 12a. Quad I/O Fast Read Sequence Diagram (M5-4=(1,0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 3 7 HOLD#(IO3) A23-16 A15-8 A7-0 M7-0 Rev 1.0 Nov 30, 2020 Dummy Byte1 Byte2 Page 28 XT25Q16D 1.8V Quad IO Serial Flash Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. Quad I/O Fast Read (EBH) in QPI mode The Quad I/O Fast Read command is also supported in QPI mode. See the figure below. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. In QPI mode, the “Continuous Read Mode” bits M7-M0 are also considered as dummy clocks. “Continuous Read Mode” feature is also available in QPI mode for Quad I/O Fast Read command. “Wrap Around” feature is not available in QPI mode for Quad I/O Fast Read command. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0CH) command must be used. Figure 12b. Quad I/O Fast Read Sequence Diagram (M5-4= (1, 0) QPI) CS# 0 2 1 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 SCLK EBH 24-bit address(A23:A0) SI(IO0) 0 1 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 1 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 1 0 6 2 6 2 6 2 6 2 6 2 6 2 6 2 1 1 7 3 7 3 7 3 7 3 7 3 7 3 7 3 HOLD#(IO3) A23-A16 A15-A8 A7-0 M7-M0* Dummy* Byte1 Byte2 Byte3 *Set Read Parameters Command (C0H) can set the number of dummy cycles Rev 1.0 Nov 30, 2020 Page 29 XT25Q16D 1.8V Quad IO Serial Flash 5.2.7. Quad I/O Word Fast Read(E7H) The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest address bit (A0) must equal 0 and only 2 dummy clock. The command sequence is shown in followed Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast read command. Figure 14. Quad I/O Word Fast Read Sequence Diagram (M5-4≠(1,0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Command SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 E7H A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3 Quad I/O Word Fast Read with “Continuous Read Mode” The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5- 4) = (1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code. The command sequence is shown in Figure14a. If the “Continuous Read Mode” bits (M5- 4) do not equal (1, 0), the next command requires the first E7H command code, thus returning to normal operation. A “Continuous Read Mode Reset” command can be used to reset (M7-0) before issuing normal command. Figure 14a. Quad I/O Word Fast Read Sequence Diagram (M5-4=(1,0)) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte1 Byte2 Rev 1.0 Nov 30, 2020 Page 30 1.8V Quad IO Serial Flash XT25Q16D Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. Rev 1.0 Nov 30, 2020 Page 31 XT25Q16D 1.8V Quad IO Serial Flash 5.3. Read Under DTR 5.3.1. DTR Fast Read (0DH) The DTR Fast Read instruction is similar to the Fast Read instruction except that the 24-bit address input and the data output require DTR (Double Transfer Rate) operation. This is accomplished by adding six dummy clocks after the 24-bit address as shown in Figure 15. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the SO pin is a “don’t care”. Figure 15. DTR Fast Read Instruction(SPI Mode) CS# 0 1 2 3 4 5 6 7 8 9 16 18 17 19 SCLK 24-bit address(A23:A0) Command SI 0DH 7 23 22 21 20 19 6 5 4 3 2 1 0 MSB High-Z SO CS# 27 26 20 21 22 23 24 25 29 28 31 30 33 32 SCLK 6 Dummy Clocks SI Data Out1 SO 7 6 5 4 3 Data Out2 2 1 0 7 6 5 4 3 Data Out3 2 1 0 MSB MSB DTR Fast Read (0DH) in QPI Mode The DTR Fast Read instruction is also supported in QPI mode. The number of dummy clocks for “DTR Fast Read” (0DH) under QPI mode and “DTR Fast Read Quad I/O” (EDH) can be set by the Latency Code (LC) in status register. When the LC bit is set to 0, which is default, the number of dummy clock cycles is 8. When the LC bit is set to 1, the dummy clock cycles is 6. Figure 15a. DTR Fast Read Instruction(QPI Mode) CS# 0 2 1 3 11 12 4 13 14 15 SCLK 0DH 24-bit address(A23:A0) SI(IO0) 0 1 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 0 0 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 0 1 6 2 6 2 6 2 6 2 6 2 6 2 0 1 7 3 7 3 7 3 7 3 7 3 7 3 HOLD#(IO3) A23-16 A15-8 A7-0 Dummy* Byte1 Byte2 Byte3 * The number of dummy clocks can be set by LC bit Rev 1.0 Nov 30, 2020 Page 32 XT25Q16D 1.8V Quad IO Serial Flash 5.3.2. DTR Fast Read Dual I/O (BDH) The DTR Fast Read Dual I/O (BDh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. Six dummy clocks(including M7-0) will follow the 24-bit address. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the SO pin is a “don’t care”. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Figure 16. DTR Fast Read Dual I/O(Initial instruction or previous M5-4≠10，SPI Mode only) CS# 8 0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Command SI(IO0) BDH 22 20 18 16 14 12 10 6 4 2 0 6 4 2 0 MSB MSB SO(IO1) Dummy 8 6 4 2 0 6 4 2 0 23 21 19 17 15 13 11 A23-16 7 5 3 1 7 5 3 1 9 7 5 3 1 7 5 3 1 A15-8 A7-0 Byte1 M7-0 Byte2 DTR Fast Read Dual I/O with “Continuous Read Mode” The DTR Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in “3BH” command description. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next DTR Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BDh instruction code, as shown in Figure 16a. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFFFh/FFFFFh on IO0 (lasting 16 or 20 clocks) for the next instruction to ensure M4 = 1 and return the device to normal operation. Figure 16a. DTR Fast Read Dual I/O (Previous instruction set M5-4=10, SPI Mode only) CS# 0 1 2 3 4 5 7 6 8 9 10 11 12 13 14 15 SCLK SI(IO0) 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 23 21 19 17 15 13 11 A23-16 6 4 2 0 6 4 2 0 MSB MSB SO(IO1) Dummy A15-8 9 7 5 3 1 7 5 3 1 A7-0 M7-0 7 5 3 1 7 5 3 1 Byte1 Byte2 5.3.3. DTR Fast Read Quad I/O (EDH) The DTR Fast Read Quad I/O (EDh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and several Dummy clocks(including M7-M0) are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Rev 1.0 Nov 30, 2020 Page 33 XT25Q16D 1.8V Quad IO Serial Flash Quad Enable bit (QE) of Status Register-2 must be set to enable the DTR Fast Read Quad I/O Instruction. The number of dummy clocks for “DTR Fast Read” (0DH) under QPI mode and “DTR Fast Read Quad I/O” (EDH) can be set by the Latency Code (LC) in status register. When the LC bit is set to 0, which is default, the number of dummy clock cycles is 8. When the LC bit is set to 1, the dummy clock cycles is 6. DTR Fast Read Quad I/O with “Continuous Read Mode” The DTR Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23 -0), as shown in “6BH” command description. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next DTR Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh/3FFh on IO0 for the next instruction (8/10 clocks), to ensure M4 = 1 and return the device to normal operation. Figure 17. DTR Fast Read Quad I/O (Initial instruction or previous M5-4≠10，SPI Mode) CS# 0 1 2 3 4 5 6 7 8 9 10 17 18 11 19 20 21 SCLK Command SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 EDH A23-16 Byte1 Byte2 A15-8 A7-0 M7-0* Dummy* * The number of dummy clocks can be set by LC bit Byte3 Figure 17a. Fast Read Quad I/O (Previous instruction set M5-4=10，SPI Mode) CS# 0 1 2 3 9 10 11 12 13 SCLK SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Byte1 Dummy* A23-16 A15-8 A7-0 M7-0* * The number of dummy clocks can be set by LC bit Rev 1.0 Nov 30, 2020 Byte2 Byte3 Page 34 XT25Q16D 1.8V Quad IO Serial Flash DTR Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The DTR Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) command prior to EDh. The “Set Burst with Wrap” (77h) command can either enable or disable the “Wrap Around” feature for the following EDh commands. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. DTR Fast Read Quad I/O (EDh) in QPI Mode The DTR Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 17b. In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default setting, the data output will follow the Continuous Read Mode bits immediately. “Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please refer to the description on previous pages. “Wrap Around” feature is not available in QPI mode for DTR Fast Read Quad I/O instruction. To perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch) instruction must be used. Please refer to C0H command for details. Figure 17b. DTR Fast Read Quad I/O (Initial instruction or previous M5-4≠10, QPI Mode) CS# 0 2 1 3 4 11 12 5 13 14 15 SCLK EDH 24-bit address(A23:A0) SI(IO0) 0 1 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 1 0 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 1 1 6 2 6 2 6 2 6 2 6 2 6 2 6 2 1 1 7 3 7 3 7 3 7 3 7 3 7 3 7 3 HOLD#(IO3) A23-16 A15-8 A7-0 M7-0 Dummy* Byte1 Byte2 Byte3 * The number of dummy clocks can be set by LC bit Rev 1.0 Nov 30, 2020 Page 35 XT25Q16D 1.8V Quad IO Serial Flash 5.4. Memory Program 5.4.1. Page Program(02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low sending Page Program command 3-byte address on SI at least 1 byte data on SI CS# goes high. The command sequence is shown in Figure18. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) is not executed. Figure 18. Page Program Sequence Diagram CS# 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 0 1 2 3 4 5 6 7 8 9 10 11 SCLK 24-bit address(A23:A0) Command SI 02H 23 22 21 20 19 Data Byte1 7 6 5 4 3 2 1 MSB 0 7 6 5 4 3 2 1 0 MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 2072 2073 2074 2075 2076 2077 2078 2079 CS# SCLK Data Byte2 SI 7 6 5 4 3 2 1 MSB Rev 1.0 Data Byte3 0 7 6 5 4 3 2 1 MSB Data Byte4 0 7 6 5 4 3 2 1 MSB Nov 30, 2020 Data Byte256 0 7 6 5 4 3 2 1 0 MSB Page 36 XT25Q16D 1.8V Quad IO Serial Flash Figure18a. Page Program Sequence Diagram (QPI) CS# 2 1 0 9 8 7 6 5 4 3 10 11 12 13 14 15 SCLK 02H SI(IO0) 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 0 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 0 0 6 2 6 2 6 2 6 2 6 2 6 2 6 2 0 0 7 3 7 3 7 3 7 3 7 3 7 3 7 3 HOLD#(IO3) Rev 1.0 24-bit address(A23:A0) A23-A16 A15-A8 A7-A0 Nov 30, 2020 Byte1 Byte2 Byte3 Byte4 Page 37 XT25Q16D 1.8V Quad IO Serial Flash 5.4.2. Quad Page Program(32H) The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2, and IO3. To use Quad Page Program, the Quad Enable bit in status register Bit9 must be set (QE=1). A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Quad Page Program command is entered by driving CS# Low, followed by the command code (32H), three address bytes and at least one data byte on IO pins. The command sequence is shown in Figure 19. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Quad Page Program command will not be executed. As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While the Quad Page Program cycle is in progress, the Status Register can be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) will not be executed. Figure 19. Quad Page Program Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 24-bit address(A23:A0) Command SI 32H 23 22 21 20 19 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 MSB Byte1 Byte2 Byte3 Byte4 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 536 537 538 539 540 541 542 543 CS# SCLK SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Byte5 Rev 1.0 Byte6 Byte7 Byte8 Byte9 Byte10 Byte11 Byte12 Byte13 Byte14 Byte15 Byte16 Nov 30, 2020 Byte253 Byte254 Byte255 Byte256 Page 38 XT25Q16D 1.8V Quad IO Serial Flash 5.5. Memory Erase 5.5.1. Sector Erase(20H) The Sector Erase (SE) command is for erasing all the data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Sector Erase command. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. The Sector Erase command sequence: CS# goes low sending Sector Erase command 3-byte address on SI CS# goes high. The command sequence is shown in Figure 20. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command will not be executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register can be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bit (see Table 1.0 & 1.1) will not be executed. Note: Power disruption during erase operation will cause incomplete erase, thus it is recommended to perform a re-erase once power resume. Figure 20. Sector Erase Sequence Diagram CS# 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 SCLK Command SI 20H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB Figure 20a. Sector Erase Sequence Diagram (QPI) CS# 2 1 0 3 4 7 6 5 SCLK 20H SI(IO0) 0 0 4 0 4 0 4 0 SO(IO1) 1 0 5 1 5 1 5 1 WP#(IO2) 0 0 6 2 6 2 6 2 0 0 7 3 7 3 7 3 HOLD#(IO3) Rev 1.0 24-bit address(A23:A0) A23-A16 A15-A8 Nov 30, 2020 A7-A0 Page 39 XT25Q16D 1.8V Quad IO Serial Flash 5.5.2. 32k Block Erase(52H) The 32KB Block Erase (BE) command is for erasing all the data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the 32KB Block Erase command. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI, driving CS# high. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. The 32KB Block Erase command sequence: CS# goes low sending 32KB Block Erase command 3-byte address on SICS# goes high. The command sequence is shown in Figure 21. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command will not be executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register can be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 1.0 & 1.1) will not be executed. Note: Power disruption during erase operation will cause incomplete erase, thus it is recommended to perform a re-erase once power resume. Figure 21. 32KB Block Erase Sequence Diagram CS 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 SCLK Command SI 52H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB Figure 21a. 32KB Block Erase Sequence Diagram (QPI) CS# 0 2 1 4 3 6 5 7 SCLK 52H SI(IO0) 1 0 4 0 4 0 4 0 SO(IO1) 0 1 5 1 5 1 5 1 WP#(IO2) 1 0 6 2 6 2 6 2 0 0 7 3 7 3 7 3 HOLD#(IO3) Rev 1.0 24-bit address(A23:A0) A23-A16 A15-A8 Nov 30, 2020 A7-A0 Page 40 XT25Q16D 1.8V Quad IO Serial Flash 5.5.3. 64k Block Erase(D8H) The 64KB Block Erase (BE) command is for erasing all the data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit, before sending the 64KB Block Erase command. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI, driving CS# high. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-byte address on SICS# goes high. The command sequence is shown in Figure 22. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command will not be executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register can be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table 1.0 & 1.1) will not be executed. Note: Power disruption during erase operation will cause incomplete erase, thus it is recommended to perform a re-erase once power resume. Figure 22. 64KB Block Erase Sequence Diagram CS 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI D8H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB Figure 22a. 64KB Block Erase Sequence Diagram (QPI) CS# 0 2 1 3 4 6 5 7 SCLK D8H SI(IO0) 1 0 4 0 4 0 4 0 SO(IO1) 0 0 5 1 5 1 5 1 WP#(IO2) 1 0 6 2 6 2 6 2 1 1 7 3 7 3 7 3 HOLD#(IO3) Rev 1.0 24-bit address(A23:A0) A23-A16 A15-A8 Nov 30, 2020 A7-A0 Page 41 XT25Q16D 1.8V Quad IO Serial Flash 5.5.4. Chip Erase(60H or C7H) The Chip Erase (CE) command is for erasing all the data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit, before sending the Chip Erase command .The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). The Chip Erase command sequence: CS# goes low sending Chip Erase commandCS# goes high. The command sequence is shown in Figure 23. CS# must be driven high after the eighth bit of the command code has been latch in, otherwise the Chip Erase command will not be executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register can be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is ignored if one or more sectors are protected. Note: Power disruption during erase operation will cause incomplete erase, thus it is recommended to perform a re-erase once power resume. Figure 23. Chip Erase Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60H or C7H Figure 23a. Chip Erase Sequence Diagram (QPI) CS# CS# 0 SCLK SCLK C7H 60H SI(IO0) 0 0 SI(IO0) 0 1 SO(IO1) 1 0 SO(IO1) 0 1 WP#(IO2) 1 0 WP#(IO2) 1 1 0 0 1 0 HOLD#(IO3) Rev 1.0 1 0 1 HOLD#(IO3) Nov 30, 2020 Page 42 XT25Q16D 1.8V Quad IO Serial Flash 5.6. Security Register 5.6.1. Read Security Register(48H) The Read Security Registers command is similar to Fast Read command. The command is followed by a 3byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high. ADDRESS Security Register 1 Security Register 2 A23-A16 00h 00h A15-A12 0001b 0010b A11-A10 00 00 A9-A0 Byte Address Byte Address Figure 24. Read Security Registers command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 48H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 SO Data Out3 Data Out2 Data Out1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB Note: The Byte Address A2-A0 must be 000. 5.6.2. Program Security Register(42H) The Program Security Registers command is similar to the Page Program command. It allows from 1 to 256 bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. If the Security Registers Lock Bit (LB1,LB2) is set to 1, the corresponding Security Registers (#1, #2) will be permanently locked. Program Security Registers command will be ignored. ADDRESS Security Register 1 Security Register 2 Rev 1.0 A23-A16 00h 00h A15-A12 0001b 0010b Nov 30, 2020 A11-A10 00 00 A9-A0 Byte Address Byte Address Page 43 XT25Q16D 1.8V Quad IO Serial Flash Figure 25. Program Security Registers command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 24-bit address(A23:A0) Command SI 42H 23 22 21 20 19 Data Byte1 7 6 5 4 3 2 1 MSB 0 7 6 5 4 3 2 1 0 MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 2072 2073 2074 2075 2076 2077 2078 2079 CS# SCLK Data Byte2 SI Data Byte3 7 6 5 4 3 2 1 MSB 0 7 6 5 4 3 2 1 MSB Data Byte4 0 7 6 5 4 3 2 1 Data Byte256 0 MSB 7 6 5 4 3 2 1 0 MSB Note: When performing program security register or erase security register, program erase suspend (op code is 75H/B0H) is not allowed, if issuing suspend op code during program or erase security register, the device may enter into malfunction. 5.6.3. Erase Security Register(44H) The device provides two 1024-byte Security Registers which only erased each 1024-byte at once. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Erase Security Registers command sequence: CS# goes lowsending Erase Security Registers CommandCS# goes high. The command sequence is shown in Figure 26. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB1,LB2) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the corresponding Security Registers (#1, #2) will be permanently locked; the Erase Security Registers command will be ignored. ADDRESS Security Register 1 Security Register 2 A23-A16 00h 00h A15-A12 0001b 0010b A11-A10 00 00 A9-A0 Don’t care Don’t care Figure 26. Erase Security Registers command Sequence Diagram CS# 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 SCLK Command SI 44H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB Note: When performing program security register or erase security register, program erase suspend (op code is 75H/B0H) is not allowed, if issuing suspend op code during program or erase security register, the device may enter into malfunction. Rev 1.0 Nov 30, 2020 Page 44 XT25Q16D 1.8V Quad IO Serial Flash 5.7. Status Register 5.7.1. Read Status Register (05H or 35H or 15H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register can be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits S7~S0. For the command code “35H”, the SO will output Status Register bits S15~S8. For the command code “15H”, the SO will output Status Register bits S23~S16. Figure 27. Read Status Register Sequence Diagram CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Command SI SO 05H or 35H or 15H High-Z Register 1/2/3 Register 1/2/3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 27a. Read Status Register Sequence Diagram (QPI) CS# 0 1 3 2 4 5 SCLK 05H /35H /15H SI(IO0) 0 1 4 0 4 0 SO(IO1) 0 0 5 1 5 1 WP#(IO2) 0 1 6 2 6 2 0 0 7 3 7 3 HOLD#(IO3) Status Status Register Register 1/2/3 1/2/3 Rev 1.0 Nov 30, 2020 Page 45 1.8V Quad IO Serial Flash XT25Q16D 5.7.2. Write Status Register (01H or 31H or 11H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command has no effect on S20, S19, S16, S13, S1 and S0 of the Status Register. CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 1.0 & 1.1 The Write Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered. For command code “01H”, the SI will input Status Register bits S7~S0. For the command code “31H”, the SI will input Status Register bits S15~S8. For the command code “11H”, the SI will input Status Register bits S23~S16. Figure 28. Write Status Register Sequence Diagram CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK SI Command Status Register in 01H/31H/11H 7 6 5 4 3 2 1 0 MSB High-Z SO Figure 28a. Write Status Register Sequence Diagram (QPI) CS# 0 1 2 3 SCLK 01H /31H /11H SI(IO0) 0 1 4 0 SO(IO1) 0 0 5 1 WP#(IO2) 0 0 6 2 0 0 7 3 HOLD#(IO3) Status Register In Note: If issue op code as 06H+50H+01H, this kind of op code combination will write the non-volatile register; We strongly suggest to issue op code separately, either 06H+01H or 50H+01H; Rev 1.0 Nov 30, 2020 Page 46 XT25Q16D 1.8V Quad IO Serial Flash 5.8. Deep Power-Down 5.8.1. Deep Power-Down(B9H) Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest power consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But the Standby Mode is different from the Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once the flash memory has entered the Deep PowerDown Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command (ABH) and Software Reset(66H + 99H). These commands release the flash memory from the Deep Power-Down Mode. The Deep Power-Down Mode automatically stops at Power-Off, and the device always Power-Up in the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI, driving CS# high. The Deep Power-Down command sequence: CS# goes lowsending Deep Power-Down commandCS# goes high. The command sequence is shown in Figure 29. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command will not be executed. As soon as CS# is driven high, it requires a time duration of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any input of Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 29. Deep Power-Down Sequence Diagram CS# tDP 0 1 2 3 4 5 6 7 SCLK Standby mode Command SI Deep Power-Down mode B9H Figure 29a. Deep Power-Down Sequence Diagram (QPI) CS# tDP 0 1 SCLK B9H SI(IO0) 1 1 SO(IO1) 1 0 WP#(IO2) 0 0 1 1 HOLD#(IO3) Standby Mode Rev 1.0 Nov 30, 2020 Deep Power-Down Mode Page 47 XT25Q16D 1.8V Quad IO Serial Flash 5.8.2. Release From Deep Power-Down(ABH) The Release from Deep Power-Down and Read Device ID command is a multi-purpose command. It can be used to release the device from Deep Power-Down Mode or obtain the devices electronic identification (ID) number. To release the device from Deep Power-Down Mode, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure 30. Release from Deep Power-Down Mode will take the time duration of tRES1 (See AC Characteristics) before the device resume to normal state and other command are accepted. The CS# pin must remain high during the tRES1 time duration. When the command is used only to obtain the Device ID while the flash memory is not in Deep PowerDown Mode, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3 dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure30b. The Device ID value is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When the command is used to release the device from Deep Power-Down Mode and obtain the Device ID, the command is the same as previously described, and shown in Figure 30b. , except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume to normal mode and other command will be accepted. If the Release from Deep Power-Down and Read Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command will be ignored and will not affect the current cycle. Figure 30. Release Power-Down Sequence Diagram CS tRES1 0 1 2 3 4 5 6 7 SCLK Command SI ABH Deep Power-Down mode Standby mode Figure 30a. Release Power-Down Sequence Diagram (QPI) CS# tRES1 0 1 SCLK ABH SI(IO0) 0 1 SO(IO1) 1 1 WP#(IO2) 0 0 1 1 HOLD#(IO3) Deep Power-Down Mode Rev 1.0 Nov 30, 2020 Standby Mode Page 48 XT25Q16D 1.8V Quad IO Serial Flash Figure 30b. Release Power-Down/Read Device ID Sequence Diagram CS 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SCLK Command SI SO ABH High-Z tRES2 3 Dummy Bytes 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB Device ID MSB 7 6 5 4 3 2 1 0 Deep Power-Down Mode Standby Mode Figure 30c. Release Power-Down/Read Device ID Sequence Diagram (QPI) CS# tRES2 0 1 2 3 4 5 6 8 7 9 SCLK ABH SI(IO0) 0 1 4 0 SO(IO1) 1 1 5 1 WP#(IO2) 0 0 6 2 1 1 7 3 HOLD#(IO3) Dummy* Rev 1.0 Nov 30, 2020 DID Deep Power-Down Mode Standby Mode Page 49 XT25Q16D 1.8V Quad IO Serial Flash 5.9. Software Reset 5.9.1. Enable Reset (66H) and Reset (99H) If the Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch status (WEL), Read Parameter setting (P7-P0) and Wrap Bit Setting (W6-W4). The “Reset (99H)” command sequence as follow: CS# goes low  Sending Enable Reset command  CS# goes high  CS# goes low  Sending Reset command  CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tRST_R to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. The Enable Reset (66H) command must be issued prior to a Reset(99H) command and any other command s can't be inserted between them. Otherwise, Enable Reset (66H) command will be cleared. Figure 31. Enable Reset and Reset command Sequence Diagram CS# 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCLK Command SI High-Z 66H Command 99H Figure 31a. Enable Reset and Reset command Sequence Diagram (QPI) CS# 0 0 1 1 SCLK 99H 66H SI(IO0) 0 0 1 1 SO(IO1) 1 1 0 0 WP#(IO2) 1 1 0 0 0 0 1 1 HOLD#(IO3) Rev 1.0 Nov 30, 2020 Page 50 XT25Q16D 1.8V Quad IO Serial Flash 5.10. Read ID 5.10.1. Read Manufacture ID/ Device ID (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Deep Power-Down and Read Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first is shown in Figure 32. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 32. Read Manufacture ID/ Device ID Sequence Diagram CS# 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 SCLK Command SI 24-bit address(A23:A0) 90H 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK SI SO Manufacturer ID Device ID Manufacturer ID 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB MSB Figure 32a. Read Manufacture ID/ Device ID Sequence Diagram (QPI) CS# 0 2 1 3 4 6 5 7 8 9 10 11 SCLK 90H SI(IO0) 1 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 0 0 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 0 0 6 2 6 2 6 2 6 2 6 2 1 0 7 3 7 3 7 3 7 3 7 HOLD#(IO3) Rev 1.0 24-bit address(A23:A0) A23-A16 A15-A8 Nov 30, 2020 A7-0 MID 3 DID Page 51 XT25Q16D 1.8V Quad IO Serial Flash 5.10.2. Read Manufacture ID/ Device ID Dual I/O (92H) The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O. The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 33 If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 33. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCLK Command SI(IO0) 92H SO(IO1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 A23-16 A15-8 A7-0 M7-0 CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 MFR ID Device ID MFR ID (Repeat) Device ID (Repeat) MFR ID (Repeat) Device ID (Repeat) 5.10.3. Read Manufacture ID/ Device ID Quad I/O (94H) The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Deep PowerDown and Read Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O. The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first is shown in Figure 34. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Figure 34. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK Command SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 HOLD#(IO3) 94H A23-16 A15-8 A7-0 M7-0 Rev 1.0 Nov 30, 2020 Dummy MID DID MID DID MID DID Page 52 XT25Q16D 1.8V Quad IO Serial Flash 5.10.4. Read Identification (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress will not be decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit manufacture identification and device identification, stored in the memory, being shifted out on Serial Data Output in repeat, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure 35. The Read Identification (RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. Figure 35. Read Identification ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK Command SI SO 9FH Memory Type JDID15-JDID8 0 7 6 5 4 3 2 1 Manufacturer ID High-Z 7 6 5 4 3 2 1 Capacity JDID7-JDID0 0 7 6 5 4 3 2 1 0 High-Z MSB Figure 35a. Read Identification ID Sequence Diagram (QPI) CS# 0 2 1 3 4 5 6 7 SCLK 9FH SI(IO0) 1 1 4 0 4 0 4 0 SO(IO1) 0 1 5 1 5 1 5 1 WP#(IO2) 0 1 6 2 6 2 6 2 1 1 7 3 7 3 7 3 HOLD#(IO3) Rev 1.0 MID Nov 30, 2020 ID15-ID8 ID7-ID0 Page 53 XT25Q16D 1.8V Quad IO Serial Flash 5.10.5. Read Unique ID(4BH) The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID command sequence: CS# goes low → sending Read Unique ID command →4 dummy bytes → 128bit Unique ID Out → CS# goes high. The command sequence is show below. Figure 36. Read Unique ID (RUID) Sequence (Command 4BH) CS# 32 33 34 35 36 37 38 39 0 1 2 3 4 5 6 7 8 9 10 11 SCLK Command SI 4bytes dummy 4BH MSB High-Z SO CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 156 157 158 159 SCLK SI 128 bit unique serial number SO 7 6 5 4 3 2 1 0 127126 125 124 123 122 121 120 MSB Read Unique ID (4BH) in QPI mode The Read Unique ID command is also supported in QPI mode. See Figure 36a. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. Figure 36a. Read Unique ID (RUID) Sequence (Command 4BH) (QPI) CS# 0 1 2 3 4 5 6 7 8 9 10 11 SCLK 4BH SI(IO0) 0 1 4 0 SO(IO1) 0 1 5 1 WP#(IO2) 1 0 6 2 0 1 HOLD#(IO3) 7 Dummy* 3 DID *Set Read Parameters command (C0H) can set the number of dummy cycles Rev 1.0 Nov 30, 2020 Page 54 XT25Q16D 1.8V Quad IO Serial Flash 5.10.6. Read SFDP(5AH) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216. Figure 37. Read Serial Flash Discoverable Parameter command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 24-bit address(A23:A0) 5AH 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 SO Data Out3 Data Out2 Data Out1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB Note: A23-A8 = 0, A7-A0 is the starting byte address for 256-byte SFDP Register. Read Serial Flash Discoverable Parameter (5AH) in QPI mode The Read Serial Flash Discoverable Parameter command is also supported in QPI mode. See Figure 37a. In QPI mode, the number of dummy clocks is configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. Figure 37a. Read Serial Flash Discoverable Parameter command Sequence Diagram (QPI) CS# 0 2 1 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 SCLK 5AH 24-bit address(A23:A0) SI(IO0) 1 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 0 1 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 1 0 6 2 6 2 6 2 6 2 6 2 6 2 0 1 7 3 7 3 7 3 7 3 7 3 7 3 HOLD#(IO3) A23-A16 A15-A8 A7-0 Dummy* Byte1 Byte2 Byte3 *Set Read Parameters Command (C0H) can set the number of dummy cycles Rev 1.0 Nov 30, 2020 Page 55 XT25Q16D 1.8V Quad IO Serial Flash 5.11. Advanced Data Protection 5.11.1. Individual Block/Sector Lock (36H)/Unlock (39H)/Read (3DH) The individual block/sector lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, BP (4:0) bits in the Status Register. The Individual Block/Sector Lock bits are volatile bits, the default values of which after device power up or after a Reset are 1. The individual Block/Sector Lock command (36H) sequence: CS# goes low –> SI: Sending individual Block/Sector Lock command –> SI: Sending 24bits individual Block/Sector Lock Address –> CS# goes high. The command sequence is shown in Figure 38. The individual Block/Sector Unlock command (39H) sequence: CS# goes low –> SI: Sending individual Block/Sector Unlock command –> SI: Sending 24bits individual Block/Sector Lock Address –> CS# goes high. The command sequence is shown in Figure 38a. The Read individual Block/Sector lock command (3DH) sequence: CS# goes low –> SI: Sending Read individual Block/Sector Lock command –> SI: Sending 24bits individual Block/Sector Lock Address –> SO: The Block/Sector Lock Bit will out –> CS# goes high. If the least significant bit (LSB) is1, the corresponding block/sector is locked, if the LSB is 0, the corresponding block/sector is unlocked, Erase/Program operation can be performed. The command sequence is shown in Figure 38c. Figure 38. Individual Block/Sector Lock command Sequence Diagram CS# 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 SCLK Command SI 36H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB Figure 38a. Individual Block/Sector Lock command Sequence Diagram (QPI) CS# 0 1 2 3 4 5 6 7 SCLK 36H SI(IO0) 1 0 4 0 4 0 4 0 SO(IO1) 1 1 5 1 5 1 5 1 WP#(IO2) 0 1 6 2 6 2 6 2 0 0 7 3 7 3 7 3 HOLD#(IO3) Rev 1.0 24-bit address(A23:A0) A23-16 Nov 30, 2020 A15-8 A7-0 Page 56 XT25Q16D 1.8V Quad IO Serial Flash Figure 38b. Individual Block/Sector Unlock command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 39H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB Figure 38c. Individual Block/Sector Unlock command Sequence Diagram (QPI) CS# 0 1 2 3 4 5 6 7 SCLK 39H 24-bit address(A23:A0) SI(IO0) 1 1 4 0 4 0 4 0 SO(IO1) 1 0 5 1 5 1 5 1 WP#(IO2) 0 0 6 2 6 2 6 2 0 1 7 3 7 3 7 3 HOLD#(IO3) A23-16 A15-8 A7-0 Figure 38d. Read Individual Block/Sector lock command Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 SCLK Command SI 3DH 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB SO Lock Value Out High Z X X X X X X X 0 MSB Rev 1.0 Nov 30, 2020 Page 57 XT25Q16D 1.8V Quad IO Serial Flash Figure 38e. Read Individual Block/Sector lock command Sequence Diagram (QPI) CS# 0 1 2 3 4 5 6 7 SCLK 3DH 24-bit address(A23:A0) SI(IO0) 1 1 4 0 4 0 4 0 SO(IO1) 1 0 5 1 5 1 5 1 WP#(IO2) 0 1 6 2 6 2 6 2 0 1 7 3 7 3 7 3 HOLD#(IO3) A15-8 A23-16 A7-0 5.11.2. Global Block/Sector Lock (7EH) or Unlock (98H) All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock command, or can set to 0 by the Global Block/Sector Unlock command. The Global Block/Sector Lock command (7EH) sequence: CS# goes low –> SI: Sending Global Block/Sector Lock command –> CS# goes high. The command sequence is shown in Figure 39. The Global Block/Sector Unlock command (98H) sequence: CS# goes low –> SI: Sending Global Block/Sector Unlock command –> CS# goes high. The command sequence is shown in Figure 39b. Figure 39. The Global Block/Sector Lock Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 7EH High-Z SO Figure 39a. The Global Block/Sector Lock Sequence Diagram (QPI) CS# 0 1 SCLK 7EH SI(IO0) 1 0 SO(IO1) 1 1 WP#(IO2) 1 1 0 1 HOLD#(IO3) Rev 1.0 Nov 30, 2020 Page 58 1.8V Quad IO Serial Flash XT25Q16D Figure 39b. The Global Block/Sector Unlock Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 98H High-Z SO Figure 39c. The Global Block/Sector Unlock Sequence Diagram (QPI) CS# 0 1 SCLK 98H SI(IO0) 1 0 SO(IO1) 0 0 WP#(IO2) 0 0 1 1 HOLD#(IO3) Rev 1.0 Nov 30, 2020 Page 59 XT25Q16D 1.8V Quad IO Serial Flash 5.12. Suspend 5.12.1. Program Erase Suspend(75H/B0H) The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/block erase operation and then read data from any other sector or block. The Write Status Register command (01H/31H/11H) and Erase/Program Security Registers command (44H,42H) and Erase commands (20H, 52H, D8H, C7H, 60H) and Page Program command (02H/32H) are not allowed during Program suspend. The Write Status Register command (01H/31H/11H) and Erase Security Registers command (44H) and Erase commands (20H, 52H, D8H, C7H, 60H) are not allowed during Erase suspend. Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of time of “tSUS” (See AC Characteristics) is required to suspend the program/erase operation. The Program/Erase Suspend command will be accepted by the device only if the SUS bit in the Status Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If the SUS bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit will be cleared form 1 to 0 within “tSUS” and the SUS bit will be set from 0 to 1 immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and release the suspend state. The command sequence is show in Figure 40. Figure 40. Program/Erase Suspend Sequence Diagram CS# tSUS 0 1 2 3 4 5 6 7 SCLK Command SI 75H SO Accept read command Figure 39a. Program/Erase Suspend Sequence Diagram(QPI) CS# tSUS 0 1 SCLK 75H SI(IO0) 1 1 SO(IO1) 1 0 WP#(IO2) 1 1 0 0 HOLD#(IO3) Accept Read Rev 1.0 Nov 30, 2020 Page 60 1.8V Quad IO Serial Flash XT25Q16D 5.12.2. Program Erase Resume (7AH/30H) The Program/Erase Resume command must be written to resume the program or sector/block erase operation after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if the SUS bit equal to 1 and the WIP bit equal to 0. After issued the SUS bit in the status register will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. The Program/Erase Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in Figure 41. Figure 41. Program/Erase Resume Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 7AH SO Resume Erase/Program Figure 40a. Program/Erase Resume Sequence Diagram (QPI) CS# 0 1 SCLK 7AH SI(IO0) 1 0 SO(IO1) 1 1 WP#(IO2) 1 0 0 1 HOLD#(IO3) Resume Earse/Program Rev 1.0 Nov 30, 2020 Page 61 XT25Q16D 1.8V Quad IO Serial Flash 5.13. Wrap 5.13.1. Set Burst With Wrap(77H) The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read (EBH)”, “Quad I/O Word Fast Read (E7H)” and “Quad Read under DTR (EDH)” commands to access a fixed length of 8/16/32/64-byte section within a 256-byte page in standard SPI mode. The Set Burst with Wrap command sequence: CS# goes low Send Set Burst with Wrap command Send 24 dummy bits Send 8 bits “Wrap bits”CS# goes high W4=0 W4=1(default) W6,W5 Wrap Around Wrap Length Wrap Around Wrap Length 0,0 Yes 8-byte No N/A 0,1 Yes 16-byte No N/A 1,0 Yes 32-byte No N/A 1,1 Yes 64-byte No N/A If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read (EBH)” and “Quad I/O Word Fast Read (E7H)” and “Quad Read under DTR (EDH)” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1. In QPI mode, the “Burst Read with Wrap (0CH)” command should be used to perform the Read Operation with “Wrap Around” feature. The Wrap Length set by W5-W6 in Standard SPI mode is still valid in QPI mode and can also be re-configured by “Set Read Parameters (C0H) command. Figure 42. Set Burst with Wrap Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK Command SI(IO0) 77H X X X X X X 4 X SO(IO1) X X X X X X 5 X WP#(IO2) X X X X X X 6 X HOLD#(IO3) X X X X X X X X W6-W4 5.13.2. Set Read Parameters(C0H) In QPI mode, to accommodate a wide range of applications with different needs for either maximum readfrequency or minimum data access latency, “Set Read Parameters (C0H)” instruction can be used to configure the number of dummy clocks for “Fast Read (0BH)”, “Fast Read Quad I/O (EBH)” & “Burst Read with Wrap (0CH)” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0CH)” instruction. In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed and will remain unchanged when the device is switched from Standard SPI mode to QPI mode and requires to be set again, prior to any 0Bh, EBh or 0Ch instructions. When the device is switched from QPI mode to SPI mode, the number of dummy clocks goes back to default. The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of dummy clocks is 8. The “Wrap Length” is set by W6-4 bit in the “Set Burst with Wrap (77h)” instruction in Standard SPI mode and by P1-P0 in the “Set Read Parameters (C0H)” in the QPI mode. The Wrap Length set by P1-P0 in QPI Rev 1.0 Nov 30, 2020 Page 62 XT25Q16D 1.8V Quad IO Serial Flash mode is still valid in SPI mode and can also be re-configured by “Set Burst with Wrap (77h)”. P5-P4 Dummy Clocks Maximum Read Freq. P1-P0 Wrap Length 00 4 80MHz 00 8-byte 01 4 80MHz 01 16-byte 10 6 108MHz 10 32-byte 1 1 ( Default ) 8 108MHz 11 64-byte Figure 43. Set Read Parameters command Sequence Diagram CS# 0 2 1 3 SCLK C0H SI(IO0) 0 0 P4 P0 SO(IO1) 0 0 P5 P1 WP#(IO2) 1 0 P6 P2 1 0 P7 P3 HOLD#(IO3) Read Parameter 5.13.3. Burst Read With Wrap(0CH) The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation with “Wrap Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap Around” once the ending boundary is reached. The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters (C0H)” command. Figure 44. Burst Read with Wrap command Sequence Diagram CS# 0 2 1 3 6 5 4 7 8 9 10 11 12 13 14 15 16 17 SCLK 0CH SI(IO0) 0 0 4 0 4 0 4 0 4 0 4 0 4 0 SO(IO1) 0 0 5 1 5 1 5 1 5 1 5 1 5 1 WP#(IO2) 0 1 6 2 6 2 6 2 6 2 6 2 6 2 0 1 7 3 7 3 7 3 7 3 7 3 7 3 HOLD#(IO3) Rev 1.0 24-bit address(A23:A0) A23-A16 A15-A8 A7-A0 Nov 30, 2020 Dummy* Byte1 Byte2 Byte3 Page 63 XT25Q16D 1.8V Quad IO Serial Flash Table 3. Parameter Table (0): Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed:50444653H Add(H) DW Add Data Data (Byte) (Bit) 00H 07:00 53H 53H 01H 15:08 46H 46H 02H 23:16 44H 44H 03H 31:24 50H 50H SFDP Minor Revision Number Start from 00H 04H 07:00 01H 01H SFDP Major Revision Number Start from 01H 05H 15:08 02H 02H Number of Parameters Headers Start from 00H 06H 23:16 02H 02H Unused Contains 0xFFH and can never be 07H 31:24 FFH FFH 08H 07:00 00H 00H changed ID number (JEDEC) 00H: It indicates a JEDEC specified Parameter Table Minor Revision Start from 0x00H 09H 15:08 01H 01H Start from 0x01H 0AH 23:16 02H 02H Parameter Table Length How many DWORDs in the 0BH 31:24 10H 10H (in double word) Parameter table Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table 0CH 07:00 30H 30H 0DH 15:08 00H 00H 0EH 23:16 00H 00H 0FH 31:24 FFH FFH 10H 07:00 0BH 0BH header Number Parameter Table Major Revision Number Unused Contains 0xFFH and can never be changed ID Number It is indicates XTX (XTX Manufacturer ID) manufacturer ID Parameter Table Minor Revision Start from 0x00H 11H 15:08 01H 01H Start from 0x01H 12H 23:16 01H 01H Parameter Table Length How many DWORDs in the 13H 31:24 03H 03H (in double word) Parameter table Parameter Table Pointer (PTP) First address of XTX Flash Parameter 14H 07:00 90H 90H table 15H 15:08 00H 00H 16H 23:16 00H 00H 17H 31:24 FFH FFH Number Parameter Table Major Revision Number Unused Contains 0xFFH and can never be changed Rev 1.0 Nov 30, 2020 Page 64 XT25Q16D 1.8V Quad IO Serial Flash Parameter Table (1): JEDEC Flash Parameter Tables Description Comment Add(H) DW Add (Byte) (Bit) Data Data 00: Reserved; 01: 4KB erase; Block/Sector Erase Size 10: Reserved; Write Granularity 0: 1Byte, 1: 64Byte or larger Write Enable Instruction Request- 0: Nonvolatile status bit ed for Writing to Volatile 1: Volatile status bit Status Registers (BP status register bit) 01:00 01b 02 1b 03 0b 11: not support 4KB erase 0: Use 50H Opcode, Write Enable Opcode Select for 1: Use 06H Opcode, Writing to Volatile Status Regis- Note: If target flash status register is ters Nonvolatile, then bits 3 and 4 must 30H E5H 04 0b 07:05 111b 15:08 20H 16 1b 18:17 00b 19 1b be set to 00b. Unused Contains 111b and can never be changed 4KB Erase Opcode If not support 4KB, set to FFH (1-1-2) Fast Read 0=Not support, 1=Support Address Bytes Number used in 00: 3Byte only, 01: 3 or 4Byte, addressing flash array 10: 4Byte only, 11: Reserved Double Transfer Rate (DTR) clocking 0=Not support, 1=Support 31H 32H (1-2-2) Fast Read 0=Not support, 1=Support 20 1b (1-4-4) Fast Read 0=Not support, 1=Support 21 1b (1-1-4) Fast Read 0=Not support, 1=Support 22 1b 23 1b 33H 31:24 FFH 37H:34H 31:00 Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (M7-M0 excluded) (1-4-4) Fast Read Number of Mode Bits 39H (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support Mode Bits (1-1-4) Fast Read Opcode Rev 1.0 3BH Nov 30, 2020 FFH 00100b 44H 07:05 010b 15:08 EBH 20:16 01000b 3AH 000b:Mode Bits not support F9H 00FFFFFFH 38H 000b:Mode Bits not support (1-4-4) Fast Read Opcode (1-1-4) Fast Read Number of 04:00 20H EBH 08H 23:21 000b 31:24 6BH 6BH Page 65 XT25Q16D 1.8V Quad IO Serial Flash Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of Mode Bits 0 0000b: Wait states (Dummy of Wait states Clocks) not support (M7-M0 excluded) 04:00 0=not support 0=not support 40H Unused Data 01000b 08H 07:05 000b 15:08 3BH 20:16 00000b 3EH 1=support 1=support Data 3CH 3FH Unused (4-4-4) Fast Read (Bit) 000b: Mode Bits not support (1-2-2) Fast Read Opcode (2-2-2) Fast Read (Byte) 3DH (1-2-2) Fast Read Number of Mode Bits DW Add 000b: Mode Bits not support (1-1-2) Fast Read Opcode (1-2-2) Fast Read Number Add(H) 3BH 40H 23:21 010b 31:24 BBH 00 0b 03:01 111b 04 1b 07:05 111b BBH FEH Unused 43H:41H 31:08 0xFFH 0xFFH Unused 45H:44H 15:00 0xFFH 0xFFH 20:16 00000b (2-2-2) Fast Read Number 0 0000b: Wait states (Dummy of Wait states Clocks) not support (2-2-2) Fast Read Number of Mode Bits 000b: Mode Bits not support (2-2-2) Fast Read Opcode Unused (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (M7-M0 included) (4-4-4) Fast Read Number of Mode Bits Sector/block size=2^N Bytes 0x00b: this sector type don’t exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size=2^N Bytes 0x00b: this sector type don’t exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size=2^N Bytes 0x00b: this sector type don’t exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size=2^N Bytes 0x00b: this sector type don’t exist Sector Type 4 erase Opcode Rev 1.0 Nov 30, 2020 00H 23:21 000b 47H 31:24 FFH FFH 49H:48H 15:00 0xFFH 0xFFH 20:16 01000b 4AH 000b: Mode Bits not support (4-4-4) Fast Read Opcode Sector Type 1 Size 46H 48H 23:21 010b 4BH 31:24 EBH EBH 4CH 07:00 0CH 0CH 4DH 15:08 20H 20H 4EH 23:16 0FH 0FH 4FH 31:24 52H 52H 50H 07:00 10H 10H 51H 15:08 D8H D8H 52H 23:16 00H 00H 53H 31:24 FFH FFH Page 66 XT25Q16D 1.8V Quad IO Serial Flash Description Comment Add(H) DW Add (Byte) (Bit) Multiplier from typical erase time to maximum erase time Erase Type 1 Erase, Typical time 54H Erase time=40ms/48ms 55H Erase Type 2 Erase, Typical time Erase time=120ms/128ms 56H Erase Type 3 Erase, Typical time Erase Type 4 Erase, Typical time Erase time=150ms/160ms 57H Not exist Multiplier from typical time to max time for Page or Byte program 58H Page Size Page size=256Byte Page Program Typical time Page program=350us/384us Byte Program Typical time, first Byte Byte Program Typical time, additional Byte Chip Erase, Typical time 59H First Byte program=25us/24us Additional Byte program=2.5us/3us Chip erase typical time=4.5s/5.12s Reserved 5AH 5BH Prohibited Operations During Program Suspend Erase Suspend Reserved Interval Suspend in-progress program max latency Erase Resume to Suspend Interval Suspend in-progress erase max latency Suspend / Resume supported 3:0 0111b 8:4 00010b 10:9 01b 15:11 00111b 17:16 01b 22:18 01001b 24:23 01b 31:25 1111111b 3:0 0100b 7:4 1000b 13:8 100101b 15:14 00b 18:16 110b 23:19 00010b 30:24 0110011b 31 0b 3:0 1000b 5CH Prohibited Operations During Program Resume to Suspend Data Interval=64us 5DH max latency=20us/20us 5EH Interval=64us max latency=20us/20us 5FH 0=support 1=not support Data FEA5 3A27H 84H 25H 16H 33H A8H 7:4 1010b 8 0b 12:9 0000b 15:13 011b 19:16 0110b 23:20 0000b 30:24 0110011b 31 0b 60H 06H 33H Program Resume Instruction 60H 7:0 7AH 7AH Program Suspend Instruction 61H 15:0 75H 75H Resume Instruction 62H 23:16 7AH 7AH Suspend Instruction 63H 31:24 75H 75H Rev 1.0 Nov 30, 2020 Page 67 XT25Q16D 1.8V Quad IO Serial Flash Description Comment Add(H) DW Add (Byte) (Bit) Reserved Data 1:0 00b 7:2 000001b 14:8 0100011b 15 1b 22:16 1010101b 23 1b 30:24 1011100b 31 0b 3:0 1001b 7:4 0001b 8 0b 9 1b Data Use of legacy polling is supported by Status Register Polling Device reading the Status Register with 05h Busy instruction and checking WIP 64H 04H bit[0] (0=ready; 1=busy). Exit Deep Power-Down to next operation delay Exit Deep Power-Down Instruction Enter Deep Power-Down Delay=3us/3us 65H ABH 66H B9H Instruction 67H Deep Power-Down Supported 0=support 1=not support 4-4-4 mode disable sequences Issue FFH or 66/99H, set 1001b If QPI not supported, set all bit to 0; 4-4-4 mode enable sequences 0-4-4 mode supported 68H Support QE and 38H, set 0 0011b If QPI not supported, set all bit to 0; 69H 1=support 0=not support A3H D5H 5CH 19H 06H 0-4-4 Mode Exit Method M=00H 15:10 000001b 0-4-4 Mode Entry Method M=AXH 19:16 0100b 22:20 100b 23 1b 31:24 00000000b 6:0 0001000b 7 0b 13:8 010000b 15:14 01b 6EH 23:16 10000000b 80H 6FH 31:24 10000000b 80H Quad Enable Requirements (QER) RESET Disable QE is in status register 2, bit 1 6AH 1=support 0=not support Reserved 6BH C4H 00H Volatile or Non-Volatile Register and Write Enable Instruction for 6CH Status Register 1 Reserved Soft Reset and Rescue Sequence Support Exit 4-Byte Addressing Enter 4-Bye Addressing Rev 1.0 66H-99H 6DH Reserved Reserved Nov 30, 2020 08H 50H Page 68 XT25Q16D 1.8V Quad IO Serial Flash Parameter Table (2): XTX Flash Parameter Tables Description Comment Add(H) DW Add (Byte) (Bit) 91H:90H 93H:92H Data Data 15:00 2100H 2100H 31:16 1650H 1650H 2100H=2.100V Vcc Supply Maximum Voltage 2700H=2.700V 3600H=3.600V 1650H=1.650V Vcc Supply Minimum Voltage 2250H=2.250V 2350H=2.350V 2700H=2.700V HW Reset# pin 0=not support 1=support 00 1b HW Hold# pin 0=not support 1=support 01 1b Deep Power-Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 1b SW Reset Opcode Should be issue Reset Enable(66H) before Reset cmd. 95H:94H 11:04 1001 1001b (99H) F99FH Program Suspend/Resume 0=not support 1=support 12 1b Erase Suspend/Resume 0=not support 1=support 13 1b 14 1b 15 1b 96H 23:16 77H 77H 97H 31:24 64H 64H 0=not support 1=support 00 1b 0=Volatile 01 0b 09:02 36H 10 0b Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode 08H:support 8B wrap-around read Wrap-Around Read data length 16H:8B&16B 32H:8B&16B&32B 64H:8B&16B&32B&64B Individual block lock Individual block lock bit (Volatile/Nonvolatile) 1=Nonvolatile Individual block lock Opcode Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect 9BH:98H Secured OTP 0=not support 1=support 11 1b Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 1b Unused 15:14 11b Unused 31:16 FFFFH Rev 1.0 Nov 30, 2020 E8D9H FFFFH Page 69 XT25Q16D 1.8V Quad IO Serial Flash 6. ELECTRICAL CHARACTERISTICS 6.1. Power-on Timing Vcc(max) Chip Selection is not allowed Vcc(min) tVSL Device is fully accessible VWI Time Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min tVSL VCC(min) To CS# Low 200 VWI Write Inhibit Voltage - Max Unit us 1.5 V 6.2. Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH). All Status Register bits except S22 bit are 0, S22 bit is 1. 6.3. Latch up Characteristics Parameter Min Input Voltage Respect To VSS On I/O Pins -1.0V VCC Current Rev 1.0 -100mA Nov 30, 2020 Max VCC+1.0V 100mA Page 70 XT25Q16D 1.8V Quad IO Serial Flash 6.4. Absolute Maximum Ratings Parameter Value Unit Ambient Operating Temperature -40 to 85 -40 to 105 ℃ Storage Temperature -65 to 150 ℃ Output Short Circuit Current 200 mA Applied Input/Output Voltage -0.5 to 4.0 V -0.5 to 4.0 V VCC 6.5. Capacitance Measurement Condition Symbol Parameter Min Typ Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 pF Input Rise And Fall time 5 ns Input Pulse Voltage 0.1VCC to 0.8VCC V Input Timing Reference Voltage 0.2VCC to 0.7VCC V Output Timing Reference Voltage 0.5VCC V Input Test Waveform and Measurement Level Maximum Negative Overshoot Waveform 20ns 20ns VSS VSS-2.0V 20ns Maximum Positive Overshoot Waveform 20ns VCC+2.0V VCC 20ns Rev 1.0 Nov 30, 2020 20ns Page 71 XT25Q16D 1.8V Quad IO Serial Flash 6.6. DC Characteristics (T=-40℃~85℃,VCC=1.65~2.1V) Symbol Parameter Test Condition Min. Typ Max. Unit ILI Input Leakage Current ±2 μA ILO Output Leakage Current ±2 μA ICC1 Standby Current 12 25 μA ICC2 Deep Power-Down Current 0.3 5 μA 10 18 mA 7 14 mA 5 11 mA CS#=VCC VIN=VCC or VSS CS#=VCC VIN=VCC or VSS CLK=0.1VCC/0.9VCC at 108MHz, Q=Open(*1,*2,*4 I/O) ICC3 CLK=0.1VCC/0.9VCC at Operating Current(Read) 80MHz, Q=Open(*1,*2,*4 I/O) CLK=0.1VCC/0.9VCC at 48MHZ, Q=Open(*1,*2,*4 I/O) ICC5 Operating Current(PP) CS#=VCC 15 20 mA ICC6 Operating Current(WRSR) CS#=VCC 10 20 mA ICC7 Operating Current(SE) CS#=VCC 10 20 mA ICC8 Operating Current(BE/CE) CS#=VCC 15 20 mA VIL Input Low Voltage -0.5 0.2VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage IOL=1.6mA 0.4 V VOH Output High Voltage IOH=-100uA VCC-0.2 V Note: 1. Typical values given for TA=25°C, VCC = 1.8V. 2. Value guaranteed by design and/or characterization, not 100% tested in production. Rev 1.0 Nov 30, 2020 Page 72 XT25Q16D 1.8V Quad IO Serial Flash (T=-40℃~105℃,VCC=1.65~2.1V) Symbol Parameter Test Condition Min. Typ Max. Unit ILI Input Leakage Current ±2 μA ILO Output Leakage Current ±2 μA ICC1 Standby Current 12 35 μA ICC2 Deep Power-Down Current 0.3 8 μA 10 23 mA 7 18 mA 5 12 mA CS#=VCC VIN=VCC or VSS CS#=VCC VIN=VCC or VSS CLK=0.1VCC/0.9VCC at 108MHz, Q=Open(*1,*2,*4 I/O) ICC3 CLK=0.1VCC/0.9VCC at Operating Current(Read) 80MHz, Q=Open(*1,*2,*4 I/O) CLK=0.1VCC/0.9VCC at 48MHZ, Q=Open(*1,*2,*4 I/O) ICC5 Operating Current(PP) CS#=VCC 15 30 mA ICC6 Operating Current(WRSR) CS#=VCC 10 30 mA ICC7 Operating Current(SE) CS#=VCC 10 30 mA ICC8 Operating Current(BE/CE) CS#=VCC 15 30 mA VIL Input Low Voltage -0.5 0.2VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage IOL=1.6mA 0.4 V VOH Output High Voltage IOH=-100uA VCC-0.2 V Note: 1. Typical values given for TA=25°C, VCC = 1.8V. 2. Value guaranteed by design and/or characterization, not 100% tested in production. Rev 1.0 Nov 30, 2020 Page 73 XT25Q16D 1.8V Quad IO Serial Flash 6.7. AC Characteristics (T=-40℃~85℃,VCC=1.65~2.1V，CL=30pF) Symbol fC1 Parameter Serial Clock Frequency For: all commands in STR Min. D.C. Typ. Max. 108 Unit MHz except Read (03H) fC2 fR tCLH tCLL (1) (1) Serial Clock Frequency For: DTR instructions D.C. 86 MHz Serial Clock Frequency for Read Data(03H) D.C. 80 MHz Serial Clock High Time 45%PC ns Serial Clock Low Time 45%PC ns tCLCH Serial Clock Rise Time(Slew Rate) 0.2 V/ns tCHCL Serial Clock Fall Time(Slew Rate) 0.2 V/ns tSLCH CS# Active Setup Time 5 ns tCHSH CS# Active Hold Time 5 ns tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time (read/write) 20 ns tSHQZ Output Disable Time tCLQV Clock Low To Output Valid tCLQX Output Hold Time 1.2 ns tDVCH Data In Setup Time 3 ns tCHDX Data In Hold Time 2 ns tHLCH Hold# Low Setup Time(relative to Clock) 5 ns tHHCH Hold# High Setup Time(relative to Clock) 5 ns tCHHL Hold# High Hold Time(relative to Clock) 5 ns tCHHH Hold# Low Hold Time(relative to Clock) 5 ns tHLQZ Hold# Low To High-Z Output 6 ns tHHQX Hold# High To Low-Z Output 6 ns tWHSL Write Protect Setup Time Before CS# Low 20 ns tSHWL Write Protect Hold Time After CS# High 100 ns tDP CS# High To Deep Power-Down Mode 3 us tRES1 CS# High To Standby Mode Without Electronic Signature Read 3 us tRES2 CS# High To Standby Mode With Electronic Signature Read 3 us tRST CS# High To Next Command After Reset 6 us tSUS CS# High To Next Command After Suspend 20 us tRS Latency Between Resume And Next Suspend tWRSR Write Status Register Cycle Time 0.8 10 ms tPP Page Programming Time 0.35 1 ms tBP Byte Programming Time (First Byte) 25 50 us tBP Byte Programming Time (After First Byte) 2.5 5 us tSE Sector Erase Time 40 700 ms tBE1 Block Erase Time(32K Bytes) 0.12 1.6 s Rev 1.0 Nov 30, 2020 8 ns 5.5 ns 120 us Page 74 XT25Q16D 1.8V Quad IO Serial Flash tBE2 Block Erase Time(64K Bytes) 0.15 3.5 s tCE Chip Erase Time 4.5 10 s Note: 1. Clock high or Clock low must be more than or equal to 45%PC. PC=1/fC(MAX). 2. Typical values given for TA=25°C. Value guaranteed by design and/or characterization, not 100% tested in production. Rev 1.0 Nov 30, 2020 Page 75 XT25Q16D 1.8V Quad IO Serial Flash (T=-40℃~105℃,VCC=1.65~2.1V，CL=30pF) Symbol fC1 Parameter Serial Clock Frequency For: all commands in STR Min. D.C. Typ. Max. 104 Unit MHz except Read (03H) fC2 fR tCLH tCLL (1) (1) Serial Clock Frequency For: DTR instructions D.C. 86 MHz Serial Clock Frequency for Read Data(03H) D.C. 80 MHz Serial Clock High Time 45%PC ns Serial Clock Low Time 45%PC ns tCLCH Serial Clock Rise Time(Slew Rate) 0.2 V/ns tCHCL Serial Clock Fall Time(Slew Rate) 0.2 V/ns tSLCH CS# Active Setup Time 5 ns tCHSH CS# Active Hold Time 5 ns tSHCH CS# Not Active Setup Time 5 ns tCHSL CS# Not Active Hold Time 5 ns tSHSL CS# High Time (read/write) 20 ns tSHQZ Output Disable Time tCLQV Clock Low To Output Valid tCLQX Output Hold Time 1.2 ns tDVCH Data In Setup Time 3 ns tCHDX Data In Hold Time 2 ns tHLCH Hold# Low Setup Time(relative to Clock) 5 ns tHHCH Hold# High Setup Time(relative to Clock) 5 ns tCHHL Hold# High Hold Time(relative to Clock) 5 ns tCHHH Hold# Low Hold Time(relative to Clock) 5 ns tHLQZ Hold# Low To High-Z Output 6 ns tHHQX Hold# High To Low-Z Output 6 ns tWHSL Write Protect Setup Time Before CS# Low 20 ns tSHWL Write Protect Hold Time After CS# High 100 ns tDP CS# High To Deep Power-Down Mode 3 us tRES1 CS# High To Standby Mode Without Electronic Signature Read 3 us tRES2 CS# High To Standby Mode With Electronic Signature Read 3 us tRST CS# High To Next Command After Reset 6 us tSUS CS# High To Next Command After Suspend 20 us tRS Latency Between Resume And Next Suspend tWRSR Write Status Register Cycle Time 0.8 10 ms tPP Page Programming Time 0.35 1 ms tBP Byte Programming Time (First Byte) 25 50 us tBP Byte Programming Time (After First Byte) 2.5 5 us tSE Sector Erase Time 40 700 ms tBE1 Block Erase Time(32K Bytes) 0.12 2 s tBE2 Block Erase Time(64K Bytes) 0.15 4.3 s Rev 1.0 Nov 30, 2020 8 ns 5.5 ns 120 us Page 76 XT25Q16D 1.8V Quad IO Serial Flash tCE Chip Erase Time 4.5 10 s Note: 1. Clock high or Clock low must be more than or equal to 45%PC. PC=1/fC(MAX). 2. Typical values given for TA=25°C. Value guaranteed by design and/or characterization, not 100% tested in production. Serial Input Timing tSHSL CS# tCHSL SCLK SI SO tCHSH tSLCH tDVCH MSB tSHCH tCHCL tCLCH tCHDX LSB High-Z Output Timing CS# tCLH SCLK tCLQV tCLQX SO tSHQZ tCLL tCLQV tCLQX LSB SI Least significant address bit (LSB) in Hold Timing CS# tCHHL tHLCH SCLK tCHHH tHLQZ SO tHHCH tHHQX HOLD# SI do not care during HOLD operation Resume to Suspend Timing Diagram CS# Rev 1.0 Resume Command tRS Nov 30, 2020 Suspend Command Page 77 XT25Q16D 1.8V Quad IO Serial Flash 7. ORDERING INFORMATION The ordering part number is formed by a valid combination of the following XT 25Q 16D SO I G U Company Prefix XT = XTX Product Family 25Q = 1.65~2.1V Serial Flash Memory with 4KB Uniform-Sector Product Density 16D = 16Mbit Product Package SO = 8-pin SOP8 (150mil) DT = 8-pad DFN8 (2x3x0.4mm) Temperature & Moisture Sensitivity Level I = Industrial Level Temp. (-40℃ to +85℃), MSL3 H = Industrial Plus Level Temp. (-40℃ to +105℃), MSL3 Green Code G = Green/Reach Package Product Carrier U = Tube; T = Tape & Reel; A = Tray Rev 1.0 Nov 30, 2020 Page 78 XT25Q16D 1.8V Quad IO Serial Flash 8. PACKAGE INFORMATION 8.1. Package SOP8 150MIL e 8 5 12*(2 X) 15*(2 1200 X) Detail “A” Θ0.8 1 b “B” b 4 Base Metal A2 A c 0.813 L L1 Θ E1 E 10° h Detail “B” SEATING PLANE c A1 D “A” Symbol A A1 A2 b c D E1 e E h L L1 θ Min 1.350 0.100 1.300 0.330 0.190 4.700 3.800 ---5.800 0.2500 0.508 0.837 0° Dimensions in Millimeters Norm ---------------4.900 3.900 1.270 6.000 0.350 0.635 1.040 ---- Max 1.750 0.250 1.500 0.510 0.250 5.000 4.000 ---6.200 0.500 0.762 1.243 8° Note: 1. Coplanarity: 0.1mm 2. Max allowable mold flash is 0.15mm at the package ends. 0.25mm between leads. 3. All dimensions follow JEDEC MS-012 standard. Rev 1.0 Nov 30, 2020 Page 79 XT25Q16D 1.8V Quad IO Serial Flash 8.2. Package DFN8 (2x3x0.4) mm D L1 e 2 L 8 b E E2 D2 h h PIN1 Lsser Mark 1 b1 2 TOP VIEW Nd EXPOSED THERMAL PAD ZONE 2 1 SIDE VIEW A1 c A BOTTOM VIEW SYMBOL A A1 b b1 c D D2 e Nd E E2 L L1 h Rev 1.0 MIN 0.36 0 0.20 0.15 1.90 1.5 2.90 0.10 0.40 0.05 0.05 MILLIMETER NOM — 0.02 0.25 0.20 0.127REF 2.00 1.6 0.50BSC 1.50BSC 3.00 0.20 0.45 0.10 0.15 Nov 30, 2020 MAX 0.40 0.05 0.30 0.25 2.10 1.7 3.10 0.30 0.50 0.15 0.25 Page 80 1.8V Quad IO Serial Flash XT25Q16D 9. REVISION HISTORY Revision 1.0 Rev 1.0 Description Initial Version Date Nov 30, 2020 Nov 30, 2020 Page 81