SILICONCONTENT
TECHNOLOGY
SCT2323，SCT2325
3.8V-32V Vin, 1.1MHz, 2A Synchronous Step-down DCDC Converter with EMI Reduction
FEATURES
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DESCRIPTION
EMI Reduction with Switching Node Ringing-free
3.8V-32V Wide Input Voltage Range
Up to 2A Continuous Output Load Current
3.3V ±1% Output Voltage (SCT2323)
5V ±1% Output Voltage (SCT2325)
Fully Integrated 130mΩ Rdson High-side MOSFET
and 70mΩ Rdson Low-side MOSFET
1uA Shut-down Current
20uA Ultra Low Quiescent Current
1.1MHz Switching Frequency with ±6%
Frequency Spread Spectrum FSS Modulation
80ns Minimum On-time
Precision Enable Threshold for Programmable
UVLO Threshold and Hysteresis
Low Drop-Out LDO Operation
Pulse Skipping Modulation PSM in Light Load
4ms Built-in Soft-start Time
Thermal Shutdown Protection at 160°C
Available in TSOT23-6L Package
APPLICATIONS
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White Goods, Air Conditioner, Refrigerator etc.
Home Appliance
Surveillance
Audio, WiFi Speaker
Printer
DTV, STB, Monitor/LCD Display
E-meter
The SCT2323 and SCT2325 are 2A, 1.1MHz,
synchronous buck converters with up to 32V wide
input voltage range, which fully integrates a 130mΩ
high-side MOSFET and a 70mΩ low-side MOSFET to
provide high efficiency step-down DCDC conversion.
The SCT2323 and SCT2325 adopt peak current
mode control with the integrated compensation
network and the output feedback resistors network,
which make the device easily to be used by
minimizing the off-chip component counts. The
SCT2323 and SCT2325 support the Pulse Skipping
Modulation (PSM) with typical 20uA Ultra-Low
Quiescent and achieved 80% efficiency at 1mA and
85% at 5mA light load conditions.
The SCT2323 and SCT2325 are Electromagnetic
Interference (EMI) friendly buck converters. The
SCT2323 and SCT2325 feature Frequency Spread
Spectrum (FSS) with ±6% jittering span of the 1.1MHz
switching frequency and modulation rate 1/512 of
switching frequency to reduce the conducted EMI.
The converter has proprietary designed gate driver
scheme to resist switching node high frequency
ringing without sacrificing MOSFET turn on and turn
off time, which further erases high frequency radiation
EMI noise caused by the MOSFETs hard switching.
When the converter enters PSM mode, the artificial
switching node anti-ringing circuit is specially
designed to address the radiation EMI noise in the
light load condition.
The SCT2323 and SCT2325 offers output overvoltage protection, cycle-by-cycle peak current limit,
and thermal shutdown protection. The device is
available in a low-profile TSOT23-6 package.
ON
OFF
VS
BST
EN
SW
VIN
GND
C2
L1
VOUT
VIN
C1
C3
C0
Efficiency (%)
TYPICAL APPLICATION
100
90
80
70
60
50
40
30
20
10
0
VIN=12V, SCT2323
VIN=12V, SCT2325
1
10
100
1000
Output Current (mA)
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1
SCT2323, SCT2325
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE DISCRIPTION
SCT2323TVB
2323
TSOT23-6L
SCT2325TVB
2325
TSOT23-6L
1）For Tape & Reel, Add Suffix R (e.g. SCT2323TVBR, SCT2325TVBR)
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Over operating free-air temperature unless otherwise noted(1)
DESCRIPTION
(1)
(2)
MIN
MAX
UNIT
BST
-0.3
40
V
VIN, SW, EN
-0.3
34
V
VS, FB
-0.3
6
V
Operating junction temperature(2)
-40
125
C
Storage temperature TSTG
-65
150
C
VS
1
6
BST
EN
2
5
SW
VIN
3
4
GND
Top View: TSOT23-6L, Plastic
Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime
PIN FUNCTIONS
NAME
2
NO.
VS
1
EN
2
VIN
GND
3
4
SW
5
BST
6
PIN FUNCTION
Buck converter output Pin. SCT2323 output voltage is 3.3V and SCT2325 output
voltage is fixed as 5V
Enable logic input. Floating the pin enables the device. This pin supports high
voltage input up to VIN supply so as to be connected VIN directly to enable the
device. The device has precision enable threshold 1.18V/1,1V rise/fall for
programmable UVLO threshold and hysteresis.
Power supply input. Must be locally bypassed.
Power ground. Must be soldered directly to ground planes.
Switching node of the buck converter.
Power supply for the high-side power MOSFET gate driver. Must connect a 0.1uF
or greater ceramic capacitor between BOOT pin and SW node.
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SCT2323, SCT2325
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
VIN
TJ
DEFINITION
Input voltage range
Operating junction temperature
MIN
MAX
UNIT
3.8
-40
32
125
V
°C
MIN
MAX
UNIT
-2
+2
kV
-0.5
+0.5
kV
ESD RATINGS
PARAMETER
VESD
DEFINITION
Human Body Model(HBM), per ANSI-JEDEC-JS-0012014 specification, all pins(1)
Charged Device Model(CDM), per ANSI-JEDEC-JS-0022014specification, all pins(1)
(1) HBM and CDM stressing are done in accordance with the ANSI/ESDA/JEDEC JS-001-2014 specification
THERMAL INFORMATION
PARAMETER
RθJA
RθJC
THERMAL METRIC
TSOT23-6L
Junction to ambient thermal resistance(1)
Junction to case thermal
89
resistance(1)
39
UNIT
°C/W
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT2323 or SCT2325 is mounted, and external environmental factors. The PCB board is a heat sink that is
soldered to the leads and thermal pad of the SCT2323 or SCT2325. Changing the design or configuration of the PCB board changes
the efficiency of the heat sink and therefore the actual RθJA and RθJC.
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3
SCT2323, SCT2325
ELECTRICAL CHARACTERISTICS
VIN=12V, TJ=-40°C~125°C, typical values are tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
Power Supply and Output
VIN
Operating input voltage
ISD
Input UVLO
Hysteresis
Shutdown current
IQ
Quiescent current
VIN_UVLO
MIN
TYP
MAX
32
V
3.5
420
1
3.7
V
mV
uA
3.8
VIN rising
EN=0, No load, VIN=12V
EN=floating, No load, No
switching. VIN=12V.
20
Enable, Soft Start and Working Modes
VEN_H
Enable high threshold
1.18
VEN_L
Enable low threshold
IEN
Enable pin input current
EN=1V
IEN_HYS
Enable pin hysteresis current
EN=1.5V
3
1.03
1.1
1
1.5
UNIT
uA
1.25
V
V
2
uA
4
uA
Power MOSFETs
RDSON_H
High side FET on-resistance
130
mΩ
RDSON_L
70
mΩ
Low side FET on-resistance
Output Voltage
VS
Output Voltage(SCT2323)
3.267
3.3
3.333
V
Output Voltage(SCT2325)
4.95
5
5.05
V
Current Limit
ILIM_HSD
HSD peak current limit
2.5
2.8
3.1
A
ILIM_HSD
2.8
3.2
3.6
0.99
1.1
1.21
LSD valley current limit
Switching Frequency
FSW
Switching frequency
VIN=12V, VOUT=5V
MHz
tON_MIN
Minimum on-time
80
ns
FJITTER
FSS percentage
±6
%
4
ms
110
%
5
%
Soft Start Time
tSS
Internal soft-start time
Protection
VOVP
THIC_W
THIC_R
TSD
4
Output overvoltage protection
threshold
Hysteresis
Over current protection hiccup wait
time
Over current protection hiccup restart
time
Thermal shutdown threshold
Hysteresis
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VOUT rising
TJ rising
TJ falling below TSD
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512
Cycles
8192
Cycles
160
25
°C
°C
All Rights Reserved
SCT2323, SCT2325
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
TYPICAL CHARACTERISTICS
60
50
40
30
60
50
40
30
20
VIN=12V, SCT2325
20
VIN=12V, SCT2323
10
VIN=24V, SCT2325
10
VIN=24V, SCT2323
0
0
1
10
100
1
1000
10
100
1000
Output Current (mA)
Output Current (mA)
Figure 2. SCT2323 Efficiency, Vout=3.3V
Figure 1. SCT2325 Efficiency, Vout=5V
40
2
30
Iq (uA)
I_SD (uA)
1.5
1
20
0.5
I_SD
Iq
0
10
-50
0
50
100
150
-50
0
Temperature (°C)
100
150
Temperature (°C)
Figure 3. Shut down Current vs Temperature
Figure 4. Quiescent Current vs Temperature
5.5
4
5
3.5
Current (A)
VOUT (V)
50
4.5
SCT2323
4
SCT2325
3
2.5
3.5
ILIM_LSD
ILIM_HSD
2
3
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
Figure 5. Output Voltage & Temperature
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Figure 6. Peak Current Limit & Temperature
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5
SCT2323, SCT2325
3.6
6
3.5
5.5
Output Voltage (v)
SCT2325
VIN (V)
3.4
3.3
UVLO RISING
3.2
UVLO FALLING
3.1
4.5
4
3.5
3
3
2.9
-50
0
50
Temperature(°C)
100
0
150
Output Voltage (v)
4.98
4.96
4.94
VIN=12V
VIN=24V
4.9
0
500
1000
1500
2000
3.32
3.32
3.31
3.31
3.30
3.30
3.29
3.29
3.28
3.28
3.27
30
40
VIN=12V
VIN=24V
0
500
1000
1500
Output Current (mA)
Output Current (mA)
Figure 9. Load Regulation, Vout=5V
6
20
Figure 8. Line Regulation (SCT2323, SCT2325), ILoad=2A
5
4.92
10
VIN (V)
Figure 7. VIN UVLO & Temperature
Output Voltage (v)
SCT2323
5
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Figure 10. Load Regulation, Vout=3.3V
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2000
SCT2323, SCT2325
FUNCTIONAL BLOCK DIAGRAM
VIN
3
4uA
1.5uA
UVLO
20K
EN
2
+
VIN UVLO
and LDO
EN
VCC
1.21V
VCC
HS MOSFET
Current Limit
VS
1
BOOT
Strap
BOOT
UVLO
Ramp
6
BST
5
SW
4
GND
SS/4ms
+
+ GM
0.8V
PWM
+
36k
PWM and Dead
Time Control
Logic
3.8nF
+
OVP
0.88V
Oscillator
with PLL
Thermal
Protection
CLK
LS MOSFET
Current Limit
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7
SCT2323, SCT2325
OPERATION
Overview
The SCT2323 and SCT2325 devices are 3.8V-32V input, 2A output, EMI friendly, fully integrated synchronous buck
converters. The device employs fixed frequency peak current mode control. An internal clock with 1.1MHz frequency
initiates turning on the integrated high-side power MOSFET Q1 in each cycle, then inductor current rises linearly
and the converter charges output cap. When sensed voltage on high-side MOSFET peak current rising above the
voltage of internal COMP (see functional block diagram), the device turns off high-side MOSFET Q1 and turns on
low-side MOSFET Q2. The inductor current decreases when MOSFET Q2 is ON. In the next rising edge of clock
cycle, the low-side MOSFET Q2 turns off. This repeats on cycle-by-cycle based.
The peak current mode control with the internal loop compensation network and the built-in 4ms soft-start simplify
the SCT2323 and SCT2325 footprints and minimize the off-chip component counts. The SCT2323 and SCT2325
integrate the output voltage feedback resistor divider network to further simplify the off-chip components design.
The SCT2323 has the 3.3V output and the SCT2325 has 5V output.
The error amplifier serves the COMP node by comparing the voltage on the FB pin with an internal 0.8V reference
voltage. When the load current increases, a reduction in the feedback voltage relative to the reference raises COMP
voltage till the average inductor current matches the increased load current. This feedback loop well regulates the
output voltage. The device also integrates an internal slope compensation circuitry to prevent sub-harmonic
oscillation when duty cycle is greater than 50% for a fixed frequency peak current mode control.
The quiescent current of SCT2323 or SCT2325 is 20uA typical under no-load condition and no switching. When
disabling the device, the supply shut down current is only 1μA. The SCT2323 and SCT2325 work at Pulse Skipping
Mode (PSM) to further increase the power efficiency in light load condition. Hence the power efficiency can be
achieved up to 88% at 5mA load condition.
The SCT2323 and SCT2325 implement the Frequency Spread Spectrum (FSS) modulation spreading of ±6%
centered 1.1MHz switching frequency. FSS improves EMI performance by not allowing emitted energy to stay in
any one receiver band for a significant length of time. The converter has optimized gate driver scheme to achieve
switching node voltage ringing-free without sacrificing the MOSFET switching time to further damping high
frequency radiation EMI noise.
The hiccup mode minimizes power dissipation during prolonged output over current or short conditions. The hiccup
wait time is 512 cycles and the hiccup restart time is 8192 cycles. The SCT2323 and SCT2325 device also features
full protections including cycle-by-cycle high-side MOSFET peak current limit, over-voltage protection, and overtemperature protection.
VIN Power
The SCT2323 and SCT2325 are designed to operate from an input voltage supply range between 3.8V to 32V, at
least 0.1uF decoupling ceramic cap is recommended to bypass the supply noise. If the input supply locates more
than a few inches from the converter, an additional electrolytic or tantalum bulk capacitor or with recommended
22uF may be required in addition to the local ceramic bypass capacitors.
Under Voltage Lockout UVLO
The SCT2323 and SCT2325 feature Under Voltage Lock Out(UVLO) functions. The default startup threshold is
typical 3.5V with VIN rising and shutdown threshold is 3.1V with VIN falling. The more accurate UVLO threshold
can be programmed through the precision enable threshold of EN pin.
8
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Enable and Start up
When applying a voltage higher than the EN high threshold (typical 1.18V rising), the SCT2323 and SCT2325
enable all functions and the devices start soft-start phase. The SCT2323 and SCT2325 have the built-in 4ms softstart time to prevent the output overshoot and inrush current. When EN pin is pulled low, the internal SS net will be
discharged to ground. Buck operation is disabled when EN voltage falls below its lower threshold (typically 1.1V
falling).
An internal 1.5uA pull up current source connected from internal LDO power rail to EN pin guarantees that floating
EN pin automatically enables the device. For the application requiring higher VIN UVLO voltage than the default
setup, there is a 4uA hysteresis pull up current source on EN pin which configures the VIN UVLO voltage with an
off-chip resistor divider R3 and R4, shown in Figure 11. The resistor divider R3 and R4 are calculated by equation
(1) and (2).
EN pin is a high voltage pin, and can be directly connected to VIN to automatically start up the device with VIN
rising to its internal UVLO threshold.
VIN
I2
4uA
I1
1.5uA
R3
20K
EN
+
EN
1.21V
R4
Figure 11. Adjustable VIN UVLO
𝑅3 =
𝑅4 =
𝑉𝑆𝑡𝑎𝑟𝑡 (
𝑉𝐸𝑁𝐹
) − 𝑉𝑆𝑡𝑜𝑝
𝑉𝐸𝑁𝑅
𝑉𝐸𝑁𝐹
𝐼1 (1 −
𝑉𝐸𝑁𝑅
(1)
) + 𝐼2
𝑅3 × 𝑉𝐸𝑁𝐹
𝑉𝑆𝑡𝑜𝑝 − 𝑉𝐸𝑁𝐹 + 𝑅3 (𝐼1 + 𝐼2 )
(2)
Where,
Vstart: Vin rise threshold to enable the device
Vstop: Vin fall threshold to disable the device
I1=1.5uA
I2=4uA
VENR=1.18V
VEMF=1.1V
EMI Reduction with Frequency Spread Spectrum and Switching Node Ringing-free(Patent Submitted)
In the some applications, the system EMI test must meet EMI standards EN55011 and EN55022. To improve EMI
performance, the SCT2323 and SCT2325 adopt Frequency Spread Spectrum (FSS) to spread the
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9
SCT2323, SCT2325
switching noise over a wider band and therefore reduces conducted and radiated interference peak amplitude at a
particular frequency. The SCT2323 and SCT2325 feature 1.1MHz switching frequency with spreading frequency of
+/-6% and modulation rate 1/512 of switching frequency. The FSS technique effectively decreases the EMI noise
by spreading the switching frequency from fixed 1.1MHz to a range 1034kHz ~ 1166kHz. As a result, the harmonic
wave amplitude is reduced and the harmonic wave band is wider.
In buck converter, the switching node ringing
amplitude and cycles are critical especially related to
the high frequency radiation EMI noise. The SCT2323
and SCT2325 implement the multi-level gate driver
speed technique to achieve the switching node
ringing-free without scarifying the switching node
rise/fall slew rate and power efficiency of the
converter. The switching node ringing amplitude and
cycles are damped by the built-in MOSFETs gate
driving technique (SCT Proprietary Design). The
switching node zoomed in wave form is shown in
Figure 12.
Figure 12. Switching Node Waveform
Peak Current Limit and Hiccup Mode
The SCT2323 and SCT2325 have cycle-by-cycle peak current limit with sensing the internal high side MOSFET Q1
current during over current condition. While the Q1 turns on, its conduction current is monitored by the internal
sensing circuitry. Once the high-side MOSFET Q1 current exceeds the limit, it turns off immediately. If the Q1 over
current time exceeds 512 switching cycles (hiccup waiting time), the buck converter enters hiccup mode and shuts
down. After 8192 cycles off, the buck converter restarts to power up. The hiccup modes reduce the power dissipation
in over current condition.
Over Voltage Protection and Minimum On-time
The SCT2323 and SCT2325 feature the output over-voltage protection (OVP). If the output pin voltage exceeds
110% of reference output voltage (5V or 3.3V), the converter stops switching immediately. When the output
feedback pin voltage drops below 105% of set output voltage, the converter resumes to switching. The OVP function
prevents the connected output circuitry damaged from un-predictive overvoltage. Featured feedback overvoltage
protection also prevents dynamic voltage spike to damage the circuitry at load during fast loading transient.
The high-side MOSFET Q1 has minimum on-time 80ns typical limitation. While the device operates at minimum ontime, further increasing VIN results in pushing output voltage beyond regulation point. With output feedback over
voltage protection, the converter skips pulse by turning off high-side MOSFET Q1 and prevents output running away
higher to damage the load.
Pulse Skipping Modulation PSM Mode
In heavy load condition, the SCT2323 and SCT2325 force the device operating at forced Pulse Width Modulation
(PWM) mode. When the load current decreasing, the internal COMP net voltage decreases as the inductor current
down. With the load current further decreasing, the COMP net voltage decreases and be clamped at a voltage
corresponding to the 450mA peak inductor current. When the load current approaches zero, the SCT2323 and
SCT2325 enter Pulse Skipping Modulation (PSM) mode to increase the converter power efficiency at light load
condition. When the inductor current decreases to zero, zero-cross detection circuitry on high-side MOSFET Q1
forces the Q1 off till the beginning of the next switching cycle. The buck converter does not sink current from the
load when the output load is light and converter works in PSM mode.
10
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Bootstrap Voltage Regulator
An external bootstrap capacitor between BST and SW pin powers floating high-side power MOSFET gate driver.
The bootstrap capacitor voltage is charged from an integrated voltage regulator when high-side power MOSFET is
off and low-side power MOSFET is on.
The floating supply (BST to SW) UVLO threshold is 2.7V rising and hysteresis of 350mV. When the converter
operates with high duty cycle or prolongs in sleep mode for certain long time, the required time interval to recharging
bootstrap capacitor is too long to keep the voltage at bootstrap capacitor sufficient. When the voltage across
bootstrap capacitor drops below 2.35V, BST UVLO occurs. The SCT2323 and SCT2325 intervene to turn on low
side MOSFET periodically to refresh the voltage of bootstrap capacitor to guarantee operation over a wide duty
range.
Low Drop-Out LDO Regulation
To support the application of small voltage-difference between Vout and Vin, the Low Drop-Out (LDO) operation is
implemented by the SCT2323 or SCT2325. The Low Drop Out operation is triggered automatic when the off time
of the high-side power MOSFET exceeds the minimum off time limitation
In LDO operation, high-side MOSFET remains ON as
long as the BST pin to SW pin voltage is higher than
BST UVLO threshold. When the voltage from BST to
SW drops below 2.35V, the high-side MOSFET turns
off and low-side MOSFET turns on to recharge
bootstrap capacitor periodically in the following
several switching cycles. Only 100ns of low side
MOSFET turning on in each refresh cycle minimizes
the output voltage ripple. Low-side MOSFET may turn
on for several times till bootstrap voltage is charged
to higher than 2.7V for high-side MOSFET working
normally. Then high-side MOSFET turns on and
remains on until bootstrap voltage drops to trigger
bootstrap UVLO again. Thus, the effective duty cycle
of the switching regulator during Low Drop-out LDO
operation can be very high even approaching 100%
as shown in Figure 13.
Figure 13. LDO Operation During Power Down
Thermal Shutdown
Once the junction temperature in the SCT2323 or SCT2325 exceeds 160C, the thermal sensing circuit stops
converter switching and restarts with the junction temperature falling below 125C. Thermal shutdown prevents the
damage on device during excessive heat and power dissipation condition.
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SCT2323, SCT2325
APPLICATION INFORMATION
Typical Application
ON
OFF
VS
BST
EN
SW
VIN
GND
C2
0.1uF
L1
6.8uH
VOUT=5V
VIN=12V
C1
10uF
C3
22uF
C2
0.1uF
Figure 14. 12V Input, 5V/2A Output
Design Parameters
12
Design Parameters
Example Value
Input Voltage
12V
Output Voltage
5V
Output Current
2A
Output voltage ripple (peak to peak)
±0.3A
Switching Frequency
1.1MHz
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Input Capacitor Selection
For good input voltage filtering, choose low-ESR ceramic capacitors. A ceramic capacitor 10μF is recommended
for the decoupling capacitor and a 0.1μF ceramic bypass capacitor is recommended to be placed as close as
possible to the VIN pin of the SCT2323 or SCT2325.
Use Equation (3) to calculate the input voltage ripple:
∆𝑉𝐼𝑁 =
𝐼𝑂𝑈𝑇
VOUT
𝑉𝑂𝑈𝑇
×
× (1 −
)
𝐶𝐼𝑁 × 𝑓𝑆𝑊
VIN
𝑉𝐼𝑁
(3)
Where:
•
CIN is the input capacitor value
•
fsw is the converter switching frequency
•
IOUT is the maximum load current
Due to the inductor current ripple, the input voltage changes if there is parasitic inductance and resistance between
the power supply and the VIN pin. It is recommended to have enough input capacitance to make the input voltage
ripple less than 100mV. Generally, a 35V/10uF input ceramic capacitor is recommended for most of applications.
Choose the right capacitor value carefully with considering high-capacitance ceramic capacitors DC bias effect,
which has a strong influence on the final effective capacitance.
Inductor Selection
The performance of inductor affects the power supply’s steady state operation, transient behavior, loop stability,
and buck converter efficiency. The inductor value, DC resistance (DCR), and saturation current influences both
efficiency and the magnitude of the output voltage ripple. Larger inductance value reduces inductor current ripple
and therefore leads to lower output voltage ripple. For a fixed DCR, a larger value inductor yields higher efficiency
via reduced RMS and core losses. However, a larger inductor within a given inductor family will generally have a
greater series resistance, thereby counteracting this efficiency advantage.
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current approaches
saturation level, its inductance can decrease 20% to 35% from the value at 0-A current depending on how the
inductor vendor defines saturation. When selecting an inductor, choose its rated current especially the saturation
current larger than its peak current during the operation.
To calculate the current in the worst case, use the maximum input voltage, minimum output voltage, maxim load
current and minimum switching frequency of the application, while considering the inductance with -30% tolerance
and low-power conversion efficiency.
For a buck converter, calculate the inductor minimum value as shown in equation (4).
𝐿𝐼𝑁𝐷𝑀𝐼𝑁 =
(4)
𝑉𝑂𝑈𝑇 × (𝑉𝐼𝑁𝑀𝐴𝑋 − 𝑉𝑂𝑈𝑇 )
𝑉𝐼𝑁𝑀𝐴𝑋 × 𝐾𝐼𝑁𝐷 × 𝐼𝑂𝑈𝑇 × 𝑓𝑆𝑊
Where:
•
KIND is the coefficient of inductor ripple current relative to the maximum output current.
Therefore, the peak switching current of inductor, ILPEAK, is calculated as in equation (5).
𝐼𝐿𝑃𝐸𝐴𝐾 = 𝐼𝑂𝑈𝑇 + 𝐾𝐼𝑁𝐷 ×
𝐼𝑂𝑈𝑇
2
(5)
Set the current limit of the SCT2323 or SCT2325 higher than the peak current ILPEAK and select the inductor with
the saturation current higher than the current limit. The inductor’s DC resistance (DCR) and the core loss
significantly affect the efficiency of power conversion. Core loss is related to the core material and different inductors
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13
SCT2323, SCT2325
have different core loss. For a certain inductor, larger current ripple generates higher DCR and ESR conduction
losses and higher core loss.
Table 1 lists recommended inductors for the SCT2323 and SCT2325. Verify whether the recommended inductor
can support the user's target application with the previous calculations and bench evaluation. In this application,
the WE's inductor 744314101 is used on SCT2323 and SCT2325 evaluation board.
Table 1. Recommended Inductors
Part Number
L
(uH)
DCR Max
(mΩ)
Saturation Current/Heat
Rating Current (A)
Size Max
(LxWxH mm)
Vendor
744314101
10
33
3.5
7x7x5
Wurth Electronik
Output Capacitor Selection
For buck converter, the output capacitor value determines the regulator pole, the output voltage ripple, and how the
regulator responds to a large change in load current. The output capacitance needs to be selected based on the
most stringent of these three criteria.
For small output voltage ripple, choose a low-ESR output capacitor like a ceramic capacitor, for example, X5R and
X7R family. Typically, 1～3x 22μF ceramic output capacitors work for most applications. Higher capacitor values
can be used to improve the load transient response. Due to a capacitor’s de-rating under DC bias, the bias can
significantly reduce capacitance. Ceramic capacitors can lose most of their capacitance at rated voltage. Therefore,
leave margin on the voltage rating to ensure adequate effective capacitance.
From the required output voltage ripple, use the equation (6) to calculate the minimum required effective
capacitance, COUT.
𝐶𝑂𝑈𝑇 =
∆𝐼𝐿𝑃𝑃
8 × 𝑉𝑂𝑈𝑇𝑅𝑖𝑝𝑝𝑙𝑒 × 𝑓𝑆𝑊
(6)
Where
• VOUTRipple is output voltage ripple caused by charging and discharging of the output capacitor.
• ΔILPP is the inductor peak to peak ripple current, equal to kIND * IOUT.
• ƒSW is the converter switching frequency.
The allowed maximum ESR of the output capacitor is calculated by the equation (7).
𝑅𝐸𝑆𝑅 =
𝑉𝑂𝑈𝑇𝑅𝑖𝑝𝑝𝑙𝑒
∆𝐼𝐿𝑃𝑃
(7)
The output capacitor affects the crossover frequency ƒC. Considering the loop stability and effect of the internal loop
1
compensation parameters, choose the crossover frequency less than 55 kHz ( × fSW ) without considering the
10
feed-forward capacitor. A simple estimation for the crossover frequency without feed forward capacitor is shown in
equation (8), assuming COUT has small ESR.
𝐶𝑂𝑈𝑇 >
18𝑘 × 𝐺𝑀 × 𝐺𝑀𝑃 × 0.8𝑉
2𝜋 × 𝑉𝑂𝑈𝑇 × 𝑓𝐶
(8)
Where
• GM is the transfer conductance of the error amplifier (300uS).
• GMP is the gain from internal COMP to inductor current, which is 5A/V.
14
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•
fC is the cross over frequency.
Additional capacitance de-rating for aging, temperature and DC bias should be factored in which increases this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. An output capacitor that can support the inductor ripple current must be specified. The
capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation (9) can
be used to calculate the RMS ripple current the output capacitor needs to support.
𝐼𝐶𝑂𝑈𝑇𝑅𝑀𝑆 =
𝑉𝑂𝑈𝑇 ∙ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
(9)
√12 ∙ 𝑉𝐼𝑁 ∙ 𝐿𝐼𝑁𝐷 ∙ 𝑓𝑆𝑊
Output Feed-Forward Capacitor Selection
The SCT2323 and SCT2325 have the internal integrated loop compensation as shown in the function block diagram.
The compensation network includes a 18k resistor and a 7.6nF capacitor. Usually, the type II compensation network
has a phase margin between 60 and 90 degree. However, if the output capacitor has ultra-low ESR, the converter
results in low phase margin. To increase the converter phase margin, a feed-forward cap Cff is used to boost the
phase margin at the converter cross-over frequency fc. Equation (10) is used to calculate the feed-forward capacitor.
𝐶𝑓𝑓 =
1
2𝜋 ∙ 𝑓𝐶 × 𝑅1
(10)
Output Feed-back Resistor Divider Selection
The SCT2323 and SCT2325 feature external programmable output voltage by using a resistor divider network R1
and R2 as shown in the typical application circuit Figure. 19. Use equation (11) to calculate the resistor divider value.
𝑅1 =
(𝑉𝑂𝑈𝑇 − 𝑉𝑟𝑒𝑓 ) × 𝑅2
𝑉𝑟𝑒𝑓
(11)
Set the resistor R2 value to be approximately 30k. Slightly increasing or decreasing R1 can result in closer output
voltage matching when using standard value resistors.
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SCT2323, SCT2325
Application Waveforms
16
Figure 15. SW node waveform and Output Ripple, Iout=2A
Figure 16. SW node Waveform and Output Ripple,
Iout=10mA
Figure 17. Power Up, Iout=2A
Figure 18. Power Down, Iout=2A
Figure 19. Load Transient
(Vout=5V, Iout=0.2A to 1.8A,SR=250mA/us)
Figure 20. Load Transient
(Vout=5V, Iout=0.5A to 1.5A,SR=250mA/us)
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Layout Guideline
The regulator could suffer from instability and noise problems without carefully layout of PCB. Radiation of highfrequency noise induces EMI, so proper layout of the high-frequency switching path is essential. Minimize the length
and area of all traces connected to the SW pin, and always use a ground plane under the switching regulator to
minimize coupling. The input capacitor needs to be very close to the VIN pin and GND pin to reduce the input supply
ripple. Place the capacitor as close to VIN pin as possible to reduce high frequency ringing voltage on SW pin as
well. Figure 21 is the recommended PCB layout of the SCT2323 and SCT2325.
The layout needs be done with well consideration of the thermal. A large top layer ground plate using multiple
thermal vias is used to improve the thermal dissipation. The bottom layer is a large ground plane connected to the
top layer ground by vias.
VOUT BST
Enable Control
EN
SW
VIN
GND
VIN
SW
VOUT
GND
Figure 21. PCB Layout Example
Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. Calculate
the maximum allowable dissipation, PD(max) , and keep the actual power dissipation less than or equal to P D(max) .
The maximum-power-dissipation limit is determined using Equation (12).
𝑃𝐷(𝑀𝐴𝑋) =
125 − 𝑇𝐶𝐴
𝑅θJA
(12)
where
• TA is the maximum ambient temperature for the application.
• RθJA is the junction-to-ambient thermal resistance given in the Thermal Information table.
The real junction-to-ambient thermal resistance RθJA of the package greatly depends on the PCB type, layout,
thermal pad connection and environmental factor. Using thick PCB copper and soldering the GND to a large ground
plate enhance the thermal performance. Using more vias connects the ground plate on the top layer and bottom
layer around the IC without solder mask also improves the thermal capability.
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17
SCT2323, SCT2325
PACKAGE INFORMATION
TOP VIEW
BOTTOM VIEW
SYMBOL
SIDE VIEW
NOTE:
1.
2.
3.
4.
5.
6.
18
Drawing proposed to be made a JEDEC package outline MO220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not
include mold flash.
Contact PCB board fabrication for minimum solder mask web
tolerances between the pins.
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A
A1
A2
D
E
E1
b
c
e
L
ɵ
Silicon Content Technology Co., Ltd.
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Unit: Millimeter
MIN
TYP
MAX
------1.10
0.000
0.10
0.70
1.00
2.85
2.95
2.65
2.95
1.55
1.65
0.30
0.50
0.08
0.20
0.95(BSC)
0.30
0.60
0º
8º
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SCT2323, SCT2325
TAPE AND REEL INFORMATION
Feeding Direction
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SCT2323, SCT2325
TYPICAL APPLICATION
24V Input, 5V Output, 500kHz Synchronous Buck
Converter
Efficiency, VIN=12V
R2
ON
OFF
VIN
FB
BST
EN
SW
VIN
GND
C2
Efficiency (%)
R1
L1
VOUT
C3
100
90
80
70
60
50
40
30
20
10
0
SCT2321, VOUT=3.3V
SCT2321, VOUT=5V
SCT2320, VOUT=5V
SCT2320, VOUT=3.3V
1
C1
10
100
1000
Output Current (mA)
RELATED PARTS
PART NUMBERS
DESCRIPTION
COMMENTS
3.8V-32V Vin, 2A/3A, 500kHz
Synchronous Buck Converter with EMI
Reduction
SCT2320
SCT2330
•
•
•
3.8V-32V Vin, 2A/3A, 500kHz
Synchronous Buck Converter with PWM
Mode
SCT2321
SCT2331
C5
68pF
R1
158k
•
•
C4
0.1uF
R2
30k
ON
OFF
VIN=3.8V~32V
C1
10uF
FB
BST
EN
SW
VIN
GND
20uA quiescent current
500kHz switching frequency with ±6%
frequency spread spectrum.
EMI reduction with switching node
ringing-free.
Forced PWM mode operation.
Fixed 500kHz Switching Frequency.
L1
10uH
VOUT=5V
C3
3 x 22uF
C2
0.1uF
Figure 22. SCT2320 and SCT2321 Typical Application
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee the third
party Intellectual Property rights are not infringed upon when integrating Silicon Content Technology (SCT) products into any
application. SCT will not assume any legal responsibility for any said applications.
20
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