XT25F04BSOIGT

3V Single IO Serial Flash XT25F04B XT25F04B Single IO Serial NOR Flash Datasheet 深圳市芯天下技术有限公司 XTX Technology Limited Tel: (86 755) 28229862 Fax: (86 755) 28229847 Web Site: http://www.xtxtech.com/ Technical Contact: fae@xtxtech.com * Information furnished is believed to be accurate and reliable. However, XTX Technology Limited assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of XTX Technology Limited. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. XTX Technology Limited products are not authorized for use as critical components in life support devices or systems without express written approval of XTX Technology Limited. The XTX logo is a registered trademark of XTX Technology Limited. All other names are the property of their respective own. Rev 1.5 Sep/17/2019 Page 0 3V Single IO Serial Flash XT25F04B Serial NOR Flash Memory 4M bits 3V Single I/O Serial Flash Memory with 4KB Uniform Sector   512 K-byte  10mA maximum active current  256 bytes per programmable page  5uA maximum Standby current Single Power Supply Voltage: Full voltage range:  Standard SPI: SCLK, CS#, SI, SO 2.7~3.6V Flexible Architecture  Minimum 100,000 Program/Erase Cycle  Sector of 4K-byte  Support 128 bits Unique ID  Block of 64k-byte  High Speed Clock Frequency Package Options   See 1.1 Available Ordering OPN  All Pb-free packages are compliant RoHS, Halogen-Free and REACH.  Temperature Range & Moisture Sensitivity Level    Standard, Dual SPI   Low Power Consumption     4M -bit Serial Flash Industrial Level Temperature. (-40℃ to +85℃), MSL3 120MHz for fast read with 30PF load Program/Erase Speed  Page Program time: 1.5ms typical  Sector Erase time: 150ms typical  Block Erase time: 0.8s typical  Chip Erase time: 6s typical Software Write Protection  Rev 1.5 Write protect all/portion of memory via software Sep/17/2019 Page 1 3V Single IO Serial Flash XT25F04B CONTENTS 1. GENERAL DESCRIPTION ................................................................................................................3 1.1. Available Ordering OPN .................................................................................................................................. 3 1.2. Connection Diagram ....................................................................................................................................... 3 1.3. Pin Description ............................................................................................................................................... 3 1.4. Block Diagram ................................................................................................................................................ 4 2. MEMORY ORGANIZATION ............................................................................................................5 3. DEVICE OPERATION ......................................................................................................................6 4. DATA PROTECTION .......................................................................................................................6 5. STATUS REGISTER .........................................................................................................................7 6. COMMANDS DESCRIPTION ...........................................................................................................8 6.1. Write Enable (WREN) (06H) ............................................................................................................................ 9 6.2. Write Disable (WRDI) (04H)............................................................................................................................. 9 6.3. Read Status Register (RDSR) (05H) .................................................................................................................. 9 6.4. Write Status Register (WRSR) (01H) .............................................................................................................. 10 6.5. Read Data Bytes (READ) (03H)....................................................................................................................... 10 6.6. Read Data Bytes At Higher Speed (Fast Read) (0BH) ...................................................................................... 11 6.7. Page Program (PP) (02H)............................................................................................................................... 11 6.8. Sector Erase (SE) (20H) ................................................................................................................................. 12 6.9. 64KB Block Erase (BE) (D8H).......................................................................................................................... 12 6.10. Chip Erase (CE) (60/C7H) ............................................................................................................................... 13 6.11. Read Manufacture ID/ Device ID (REMS) (90H).............................................................................................. 13 6.12. Read Unique ID (RUID) (90H) ........................................................................................................................ 14 6.13. Read Identification (RDID) (9FH) ................................................................................................................... 14 6.14. Write Enable for Volatile Status Register (50H).............................................................................................. 15 7. ELECTRICAL CHARACTERISTICS ...................................................................................................16 7.1. Power-on Timing........................................................................................................................................... 16 7.2. Initial Delivery State...................................................................................................................................... 16 7.3. Data Retention and Endurance ..................................................................................................................... 16 7.4. Latch up Characteristics ................................................................................................................................ 16 7.5. Absolute Maximum Ratings........................................................................................................................... 17 7.6. Capacitance Measurement Condition ........................................................................................................... 17 7.7. DC Characteristics......................................................................................................................................... 18 7.8. AC Characteristics ......................................................................................................................................... 19 Rev 1.5 Sep/17/2019 Page 1 3V Single IO Serial Flash XT25F04B 8. ORDERING INFORMATION..........................................................................................................21 9. PACKAGE INFORMATION ............................................................................................................22 9.1. Package SOP8 150MIL................................................................................................................................... 22 9.2. Package SOP8 208MIL ................................................................................................................................... 23 9.3. Package TSSOP8 173MIL ............................................................................................................................... 24 9.4. Package DFN8 (2x3x0.55) mm ....................................................................................................................... 25 9.5. Package VSOP 208MIL .................................................................................................................................. 26 10. REVISION HISTORY ......................................................................................................................27 Rev 1.5 Sep/17/2019 Page 2 XT25F04B 3V Single IO Serial Flash 1. GENERAL DESCRIPTION The XT25F04B (4M) bits Serial flash supports the standard Serial Peripheral Interface (SPI). SPI clock frequency of up to 120MHz is supported for fast read command. 1.1. 1.2. Available Ordering OPN OPN Package Type Package Carrier XT25F04BSOIGU SO8 150mil Tube XT25F04BSOIGT SO8 150mil Tape & Reel XT25F04BSOIGA SO8 150mil Tray XT25F04BSSIGU SO8 208mil Tube XT25F04BSSIGT SO8 208mil Tape & Reel XT25F04BTSIGU TSSOP8 Tube XT25F04BTSIGT TSSOP8 Tape & Reel XT25F04BDFIGT DFN8 2x3x0.55mm Tape & Reel Connection Diagram CS# 1 8 VCC SO 2 7 NC Top View NC 3 6 SCLK VSS 4 5 SI 8 – LEAD SOP / DFN8 1.3. Pin Description Pin Name I/O CS# I Chip Select Input SO (IO1) O Data Output Ground VSS SI (IO0) I Data Input SCLK I Serial Clock Input VCC Rev 1.5 Description Power Supply Sep/17/2019 Page 3 XT25F04B 3V Single IO Serial Flash Block Diagram Status Register SCLK CS# SI(IO0) SPI Command & Control Logic High Voltage Generators Page Address Latch/Counter Write Prot ect Logic And Row Decode 1.4. Flash Memory Column Decode And 256-Byte Page Buffer SO(IO1) Byte Address Latch/Counter Rev 1.5 Sep/17/2019 Page 4 XT25F04B 3V Single IO Serial Flash 2. MEMORY ORGANIZATION XT25F04B Memory Description Each Device has Each block has Each sector has Each page has 512K 64K 4K 256 bytes 2K 256 16 - pages 128 16 - - sectors 8 - - - blocks UNIFORM BLOCK SECTOR ARCHITECTURE XT25F04B 64K Bytes Block Sector Architecture Block Sector Address range 127 7 6 …… …… 2 1 0 Rev 1.5 07F000H 07FFFFH …… …… 112 070000H 070FFFH 111 06F000H 06FFFFH …… …… 96 060000H …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… …… 47 02F000H 02FFFFH …… …… 32 020000H 020FFFH 31 01F000H 01FFFFH …… …… 16 010000H 010FFFH 15 00F000H 00FFFFH …… …… 0 000000H Sep/17/2019 …… …… 060FFFH …… …… …… 000FFFH Page 5 XT25F04B 3V Single IO Serial Flash 3. DEVICE OPERATION The XT25F04B features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. 4. DATA PROTECTION The XT25F04B provides the following data protection methods:  Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation:  Power-Up  Write Disable (WRDI)  Write Status Register (WRSR)  Page Program (PP)  Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)  Software Protection Mode:  SRWD=0, the Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be read but not change  SRWD=1, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. Table1.0 XT25F04B Protected Area Sizes Status bit Rev 1.5 Protect level Protect Block BP2 BP1 BP0 0 0 0 0(none) None 0 0 1 1 (1 block) Block 7 0 1 0 2 (2 blocks) Block 6-7 0 1 1 3 (4 blocks) Block 4-7 1 0 0 4 (8 blocks) All 1 0 1 5 (All) All 1 1 0 6 (All) All 1 1 1 7 (All) All Sep/17/2019 Page 6 XT25F04B 3V Single IO Serial Flash 5. STATUS REGISTER S7 SRWD S6 Reserved S5 Reserved S4 BP2 S3 BP1 S2 BP0 S1 WEL S0 WIP The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1.0) becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. Chip Erase command will be ignored if one or more of the Block Protect (BP2, BP1, BP0) bits are 1. SRWD bit. The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP) bit in the status register that provide another software protection. Once it is set to 1, the Write Status Register (WRSR) instruction is no longer accepted and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. Rev 1.5 SRWD Status register Memory 0 Status register can be written in (WEL bit is set to “1”) and the SRWD, BP2-BP0 bits can be changed The protected area cannot be program or erase 1 The SRWD, BP2-BP0 of status register bits cannot be changed The protected area cannot be program or erase Sep/17/2019 Page 7 XT25F04B 3V Single IO Serial Flash 6. COMMANDS DESCRIPTION All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 2, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable or Write Disable command, CS# must be driven high exactly at the byte boundary, otherwise the command is rejected, and is not executed. That is CS# must be driven high when the number of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. Table 2. Commands Command Name Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 n-Bytes Write Enable 06H Write Disable 04H Write Enable for Volatile Status Register 50H Read Status Register 05H (S7-S0) (continuous) Write Status Register 01H (S7-S0) (continuous) Read Data 03H A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) Page Program 02H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) Sector Erase 20H A23-A16 A15-A8 A7-A0 Block Erase D8H A23-A16 A15-A8 A7-A0 Chip Erase C7/60H (MID7MID0) (DID7-DID0) (continuous) Manufacturer/Device ID 90H dummy dummy 00H Read Unique ID 90H 00H 00H 00H 9FH (MID7MID0) (JDID15JDID8) (JDID7JDID0) Read Identification (Next byte) (continuous) Dummy (1) Dummy (2) (continuous) Dummy..(16) D0..D7 (continuous) Table of ID Definitions: XT25F04B Rev 1.5 Operation Code M7-M0 ID15-ID8 9FH 0B 40 90H 0B ID7-ID0 13 12 Sep/17/2019 Page 8 XT25F04B 3V Single IO Serial Flash 6.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low sending the Write Enable commandCS# goes high. Figure1. Write Enable Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 06H High-Z SO 6.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes lowsending the Write Disable commandCS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. Figure 2. Write Disable Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 04H High-Z SO 6.3. Read Status Register (RDSR) (05H) The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. Figure 3. Read Status Register Sequence Diagram CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Command SI 05H S7~S0 out SO High-Z MSB Rev 1.5 S7~S0 out 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 Sep/17/2019 MSB Page 9 XT25F04B 3V Single IO Serial Flash 6.4. Write Status Register (WRSR) (01H) The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1.0. The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP) bit, the Write Status Register (WRSR) command allows the user to set the Status Register Write Disable (SRWD) bit to 1. The Status Register Write Disable (SRWD) bit allow the device to be put in another Software Protected Mode. Once the SRWD bit is set to 1, the Write Status Register (WRSR) command is not executed, and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. The Write Status Register (WRSR) command has no effect on S6, S5, S1 and S0 of the Status Register. CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. Figure 4. Write Status Register Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Command SI Status Register in 7 6 5 4 3 2 1 01H MSB 0 15 14 13 12 11 10 9 8 MSB High-Z SO 6.5. Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 5. Read Data Bytes Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SCLK Command SI 03H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB SO Rev 1.5 Data Out1 High-Z MSB Sep/17/2019 7 6 5 4 3 2 1 Data Out2 0 Page 10 XT25F04B 3V Single IO Serial Flash 6.6. Read Data Bytes At Higher Speed (Fast Read) (0BH) The Read Data Bytes at Higher Speed (Fast Read) command is for fast reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next address after each byte of data is shifted out. Figure 6. Read Data Bytes at Higher Speed Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 0BH 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy Byte SI 7 6 5 4 3 2 1 0 Data Out1 SO 7 6 5 4 3 2 1 Data Out3 MSB MSB 6.7. Data Out2 0 7 6 5 4 3 2 1 0 Page Program (PP) (02H) The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low  sending Page Program command  3-byte address on SI  at least 1 byte data on SI  CS# goes high. The command sequence is shown in Figure 7. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP1, BP0) is not executed. Rev 1.5 Sep/17/2019 Page 11 XT25F04B 3V Single IO Serial Flash Figure 7. Page Program Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 24-bit address(A23:A0) Command SI 02H 23 22 21 20 19 Data Byte1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 2072 2073 2074 2075 2076 2077 2078 2079 CS# SCLK Data Byte2 SI Data Byte3 7 6 5 4 3 2 1 Data Byte256 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB 6.8. Data Byte4 MSB MSB 7 6 5 4 3 2 1 0 MSB Sector Erase (SE) (20H) The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low sending Sector Erase command  3-byte address on SI  CS# goes high. The command sequence is shown in Figure 8. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP2, BP1, BP0) bit (see Table1.0) is not executed. Figure 8. Sector Erase Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 20H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB 6.9. 64KB Block Erase (BE) (D8H) The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. Rev 1.5 Sep/17/2019 Page 12 XT25F04B 3V Single IO Serial Flash The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command 3byte address on SI  CS# goes high. The command sequence is shown in Figure 9. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Block Erase cycle. Block Erase (BE) command applied to a block which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table1.0) is not executed. Figure 9. 64KB Block Erase Sequence Diagram CS 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI D8H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB 6.10. Chip Erase (CE) (60/C7H) The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low  sending Chip Erase command  CS# goes high. The command sequence is shown in Figure 10. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the selftimed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset to 0 at the end of the Chip Erase cycle. The Chip Erase (CE) command is ignored if one or more sectors are protected by (BP2, BP1, BP0) bits. Figure 10. Chip Erase Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60H or C7H 6.11. Read Manufacture ID/ Device ID (REMS) (90H) The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first is shown in Figure 11. If the 24-bit address is initially set to 000001H, the Device ID will be read first. Rev 1.5 Sep/17/2019 Page 13 XT25F04B 3V Single IO Serial Flash Figure 11. Read ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 24 25 26 27 28 29 30 31 SCLK Command SI 90H 24-bit address(A23:A0) 23 22 21 20 19 7 6 5 4 3 2 1 0 MSB High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK SI Manufacturer ID SO Manufacturer ID Device ID 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB MSB 6.12. Read Unique ID (RUID) (90H) Please contact XTX FAE for detail 6.13. Read Identification (RDID) (9FH) The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure 12. The Read Identification (RDID) command is terminated by driving CS# to high at any time during data output. After CS# is driven high, the device returns to Standby Mode and awaits for new command. Figure 12. Read Identification ID Sequence Diagram CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCLK Command SI 9FH Manufacturer ID SO High-Z 7 6 5 4 3 2 1 Memory Type JDID15-JDID8 0 7 6 5 4 3 2 1 Capacity JDID7-JDID0 0 7 6 5 4 3 2 1 0 High-Z MSB Rev 1.5 Sep/17/2019 Page 14 3V Single IO Serial Flash XT25F04B 6.14. Write Enable for Volatile Status Register (50H) The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical nonvolatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command must be issued prior to a Write Status Register command and any other commands can’t be inserted between them. Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register bit values. Figure 13. Write Enable for Volatile Status Register Sequence Diagram CS# 0 1 2 3 4 5 6 7 SCLK Command SI SO Rev 1.5 50H High-Z Sep/17/2019 Page 15 XT25F04B 3V Single IO Serial Flash 7. ELECTRICAL CHARACTERISTICS 7.1. Power-on Timing Vcc(max) Chip Selection is not allowed Vcc(min) Reset State tVSL Device is fully accessible VWI tPUW Time Table3. Power-Up Timing and Write Inhibit Threshold Note: At power-down, need to ensure VCC drop to 0.5V before the next power-on in order for the device to have a proper power-on reset. Symbol Parameter Min Max Unit tVSL VCC(min) To CS# Low 10 us tPUW Time Delay Before Write Instruction 1 - ms VWI Write Inhibit Voltage 1.5 2.5 V 7.2. Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0). 7.3. Data Retention and Endurance Parameter Data Retention Time Erase/Program Endurance Typical Unit 20 Years 100K Cycles Min Max 7.4. Latch up Characteristics Parameter Input Voltage Respect To VSS On I/O Pins -1.0V VCC Current Rev 1.5 -100mA Sep/17/2019 VCC+1.0V 100mA Page 16 XT25F04B 3V Single IO Serial Flash 7.5. Absolute Maximum Ratings Parameter Value Unit Ambient Operating Temperature -40 to 85 ℃ Storage Temperature -65 to 150 ℃ Output Short Circuit Current 200 mA Applied Input/Output Voltage -0.5 to 4.0 V -0.5 to 4.0 V VCC 7.6. Capacitance Measurement Condition Symbol Parameter Typ Min Max Unit Conditions CIN Input Capacitance 6 pF VIN=0V COUT Output Capacitance 8 pF VOUT=0V CL Load Capacitance 30 Input Rise And Fall time pF 5 ns Input Pulse Voltage 0.1VCC to 0.8VCC V Input Timing Reference Voltage 0.2VCC to .8 0.7VCC V Output Timing Reference Voltage VCC 0.5VCC V Figure 14. Input Test Waveform and Measurement Level Maximum Negative Overshoot Waveform 20ns 20ns VSS VSS-2.0V 20ns Maximum Positive Overshoot Waveform 20ns VCC+2.0V VCC 20ns Rev 1.5 Sep/17/2019 20ns Page 17 XT25F04B 3V Single IO Serial Flash 7.7. DC Characteristics (T=-40℃~85℃,VCC=2.7~3.6V) Symbol Parameter Test Condition Min. Typ Max. Unit ILI Input Leakage Current ±2 μA ILO Output Leakage Current ±2 μA ICC1 Standby Current 1 5 μA 15 20 mA 13 18 mA CS#=VCC VIN=VCC or VSS CLK=0.1VCC/0.9VCC at 120MHz for Fast Read ICC3 Operating Current(Read) CLK=0.1VCC/0.9VCC at 40MHz for Read ICC4 Operating Current(PP) CS#=VCC 20 mA ICC5 Operating Current(WRSR) CS#=VCC 20 mA ICC6 Operating Current(SE) CS#=VCC 20 mA ICC7 Operating Current(BE) CS#=VCC 20 mA VIL Input Low Voltage -0.5 0.2VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage IOL=1.6mA VOH Output High Voltage IOH=-100uA Rev 1.5 Sep/17/2019 0.4 VCC-0.2 V V Page 18 XT25F04B 3V Single IO Serial Flash 7.8. AC Characteristics (T=-40℃~85℃,VCC=2.7~3.6V，CL=30pF) Symbol fC fR Parameter Min. Typ Serial Clock Frequency For:Fast Read(0BH), Serial Clock Frequency For:Read(03H) Max. Unit 120 40 MHz MHz tCLH tCLL Serial Clock High Time 4 ns Serial Clock Low Time 4 ns tCLCH tCHCL Serial Clock Rise Time(Slew Rate) 0.2 V/ns Serial Clock Fall Time(Slew Rate) 0.2 V/ns tSLCH tCHSH CS# Active Setup Time 5 ns CS# Active Hold Time 5 ns tSHCH tCHSL CS# Not Active Setup Time 5 ns CS# Not Active Hold Time 5 ns tSHSL tSHQZ CS# High Time (read/write) 20 ns tCLQX tDVCH Output Hold Time 1 ns Data In Setup Time 2 ns tCHDX tHLCH Data In Hold Time 2 ns Hold# Low Setup Time(relative to Clock) 5 ns tHHCH tCHHL Hold# High Setup Time(relative to Clock) 5 ns Hold# High Hold Time(relative to Clock) 5 ns tCHHH tHLQZ Hold# Low Hold Time(relative to Clock) 5 ns Hold# Low To High-Z Output 6 ns tHHQX tCLQV Hold# Low To Low-Z Output 6 ns 6.5 ns tWHSL tSHWL Write Protect Setup Time Before CS# Low tRES2 Output Disable Time 6 Clock Low To Output Valid Write Protect Hold Time After CS# High ns 20 ns 100 ns CS# High To Standby Mode With Electronic Signature Read 0.1 us tW Write Status Register Cycle Time 100 200 ms tPP tSE Page Programming Time 1.5 5 ms Sector Erase Time 120 300 ms tBE tCE Block Erase Time 0.8 1.5 s Chip Erase Time 6 10 s Max Value 4KB tSE with50K &