SILICON CONTENT
TECHNOLOGY
SCT2452
Rev 1.1
3.8V-36V Vin, 5A, High Efficiency Synchronous Step-down DCDC Converter
with Programmable Frequency
FEATURES
DESCRIPTION
•
•
•
•
The SCT2452 is 5A synchronous buck converters with
wide input voltage, ranging from 3.8V to 36V, which
integrates a 45mΩ high-side MOSFET and a 20mΩ
low-side MOSFET. The SCT2452, adopting the peak
current mode control, supports the Pulse Skipping
Modulation (PSM) with typical 25uA low quiescent
current which assists the converter on achieving high
efficiency at light load or standby condition.
Wide Input Range: 3.8V-36V
Up to 5A Continuous Output Current
0.8V ±1% Feedback Reference Voltage
Integrated 45mΩ High-Side and 20mΩ Low-Side
Power MOSFETs
Pulse Skipping Mode (PSM) with 25uA Quiescent
Current in Sleep Mode
100ns Minimum On-time
Adjustable Soft-start Time
Adjustable Frequency 100KHz to 1.1MHz
External Clock Synchronization
Frequency Spread Spectrum (FSS) Modulation for
EMI Reduction
Precision Enable Threshold for Programmable
Input Voltage Under Voltage Lock Out Protection
(UVLO) Threshold and Hysteresis
Low Dropout Mode Operation
Derivable Inverting Voltage Regulator
Over-voltage and Over-Temperature Protection
Available in an ESOP-8 Package
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
•
Battery Pack Powered System - Cordless Power
Tools, Cordless Home Appliance, Drone, Aero
Modeling, GPS Tracker etc.
Cigarette Lighter Adapters, Chargers
LCD Display
USB Type-C Power Delivery, USB Charging
Industrial and Medical Distributed Power Supplies
Optical Communication and Networking System
Automotive System
•
•
•
•
•
•
The SCT2452 features programmable switching
frequency from 100 kHz to 1.1 MHz with an external
resistor, which provides the flexibility to optimize either
efficiency or external component size. The converter
supports external clock synchronization with a
frequency band from 100kHz to 1.1MHz. The SCT2452
allows power conversion from high input voltage to low
output voltage with a minimum 100ns on-time of highside MOSFET.
The SCT2452 is an Electromagnetic Interference (EMI)
friendly buck converter with implementing optimized
design for EMI reduction. The SCT2452 features
Frequency Spread Spectrum FSS with ±6% jittering
span of the 500kHz switching frequency and
modulation rate 1/512 of switching frequency to reduce
the conducted EMI.
The SCT2452 offers cycle-by-cycle current limit and
hiccup over current protection, thermal shutdown
protection, output over-voltage protection and input
voltage under-voltage protection. The device is
available in an 8-pin thermally enhanced SOP-8
package.
TYPICAL APPLICATION
100
BOOT
VIN
L1
SW
VOUT
C5
VIN
GND
SCT2452
EN
SS
C1 C2
RT/CLK
R4
R1
FB
C4
R2
90
Efficiency(%)
C3
80
VIN=24V, VOUT=5V
70
VIN=24V, VOUT=3.3V
VIN=12V, VOUT=5V
60
VIN=12V,VOUT=3.3V
50
0.001
0.01
0.1
1
10
Output Current (A)， Freq.=500KHz
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1
SCT2452
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision 1.0: Release to product
Revision 1.1: Updated Max Vin Transient voltage
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE DISCRIPTION
SCT2452STE
2452
8-Lead Plastic ESOP
1)
For Tape & Reel, Add Suffix R (e.g. SCT2452STER)
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Over operating free-air temperature unless otherwise noted(1)
DESCRIPTION
MIN
MAX
UNIT
VIN
-0.3
38
V
VIN Transient (300ms) (2)
-0.3
42
V
EN
-0.3
38
V
BOOT
-0.3
44
V
SW
-1
38
V
BOOT-SW
-0.3
6
V
-0.3
6
V
-40
150
°C
-65
150
°C
SS, FB, RT/CLK
Operating junction temperature
TJ(2)
Storage temperature TSTG
(1)
(2)
(3)
BOOT
1
VIN
2
EN
3
RT/CLK
4
Thermal
Pad
8
SW
7
GND
6
SS
5
FB
Figure 1. 8-Lead Plastic E-SOP
Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The max VIN transient voltage is guaranteed by design and verified on bench.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime.
PIN FUNCTIONS
NAME
NO.
BOOT
1
VIN
2
EN
3
RT/CLK
4
2
PIN FUNCTION
Power supply bias for high-side power MOSFET gate driver. Connect a 0.1uF capacitor
from BOOT pin to SW pin. Bootstrap capacitor is charged when low-side power
MOSFET is on or SW voltage is low.
Input supply voltage. Connect a local bypass capacitor from VIN pin to GND pin. Path
from VIN pin to high frequency bypass capacitor and GND must be as short as possible.
Enable pin to the regulator with internal pull-up current source. Pull below 1.1V to
disable the converter. Float or connect to VIN to enable the converter. The tap of resistor
divider from VIN to GND connecting EN pin can adjust the input voltage lockout
threshold.
Set the internal oscillator clock frequency or synchronize to an external clock. Connect
a resistor from this pin to ground to set switching frequency. An external clock can be
input directly to the RT/CLK pin. The internal oscillator synchronizes to the external
clock frequency with PLL. If detected clocking edges stops, the operation mode
automatically returns to resistor programmed frequency.
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SCT2452
FB
5
SS
6
Inverting input of the trans-conductance error amplifier. The tap of external feedback
resistor divider from the output to GND sets the output voltage. The device regulates
FB voltage to the internal reference value of 0.8V typical.
Connect a cap to ground, program the soft start time.
GND
7
Ground
SW
Thermal
Pad
8
Regulator switching output. Connect SW to an external power inductor
Heat dissipation path of die. Electrically connection to GND pin. Must be connected to
ground plane on PCB for proper operation and optimized thermal performance.
9
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
DEFINITION
VIN
VOUT
TJ
Input voltage range
Output voltage range
Operating junction temperature
MIN
MAX
UNIT
3.8
0.8
-40
36
36
125
V
V
°C
MIN
MAX
UNIT
-2
+2
kV
-0.5
+0.5
kV
ESD RATINGS
PARAMETER
VESD
DEFINITION
Human Body Model(HBM), per ANSI-JEDEC-JS-001-2014
specification, all pins(1)
Charged Device Model(CDM), per ANSI-JEDEC-JS-0022014 specification, all pins(2)
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
THERMAL INFORMATION
PARAMETER
RθJA
RθJC
THERMAL METRIC
Junction to ambient thermal resistance(1)
Junction to case thermal
resistance(1)
SOP-8L
42
45.8
UNIT
°C/W
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit board
(PCB) on which the SCT2452 is mounted, thermal pad size, and external environmental factors. The PCB board is a heat sink that is
soldered to the leads and thermal pad of the SCT2452. Changing the design or configuration of the PCB board changes the efficiency
of the heat sink and therefore the actual RθJA and RθJC.
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3
SCT2452
ELECTRICAL CHARACTERISTICS
VIN=24V, TJ=-40°C~125°C, typical value is tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
Power Supply
VIN
Operating input voltage
ISHDN
IQ
Quiescent current from VIN pin
VIN rising
3.5
400
1
EN=0, no load
EN floating, no load, nonswitching, BOOT-SW=5V
Power MOSFETs
RDSON_H
High-side MOSFET on-resistance
RDSON_L
VBOOT-VSW=5V
Low-side MOSFET on-resistance
Reference and Control Loop
VREF
Reference voltage of FB
Current Limit and Over Current Protection
High-side power MOSFET peak
ILIM_HS
current limit threshold
Low-side power MOSFET souring
ILIM_LSSRC
current limit threshold
Over current protection hiccup wait
THIC_W
time
Over current protection hiccup restart
THIC_R
time
V
3.7
V
mV
μA
3
25
μA
45
mΩ
20
mΩ
0.8
0.808
V
6.8
8
9.2
A
IEN_L
Enable pin pull-up current
EN=1V
IEN_H
Enable pin pull-up current
EN=1.5V
Iss
SS pin current
cycle
8192
cycle
1.03
1.1
1
1.5
Switching Frequency and External Clock Synchronization
FRANGE_RT
Frequency range using RT mode
100
FSW
Switching frequency
450
FRANGE_CLK
Frequency range using CLK mode
Frequency spread spectrum in
percentage of Fsw
Minimum on-time
RRT=200 kΩ(1%)
A
512
1.18
Enable low threshold
UNIT
36
9
VEN_L
tON_MIN
MAX
0.792
Enable and Soft Startup
VEN_H
Enable high threshold
FJITTER
TYP
3.8
Input UVLO Threshold
Hysteresis
Shutdown current from VIN pin
VIN_UVLO
MIN
1.25
V
V
2
μA
5.5
uA
3
uA
500
100
1100
kHz
550
kHz
1100
kHz
±6
%
VIN=24V
100
ns
VFB/VREF rising
VFB/VREF falling
BOOT-SW falling
Hysteresis
TJ rising
Hysteresis
110
105
2.36
300
170
25
%
%
V
mV
°C
°C
Protection
VOVP
VBOOTUV
TSD
4
Feedback overvoltage with respect to
reference voltage
BOOT-SW UVLO threshold
Thermal shutdown threshold
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SCT2452
100
100
90
90
80
80
Efficiency(%)
Efficiency(%)
TYPICAL CHARACTERISTICS
70
60
70
60
VIN=36V, VOUT=3.3V
VIN=36V, VOUT=5V
VIN=36V, VOUT=12V
50
40
0.001
0.01
0.1
VIN=24V, VOUT=3.3V
VIN=24V, VOUT=5V
VIN=24V, VOUT=12V
50
1
40
10
0.001
0.01
Output Current(A)
Figure 2. Efficiency vs Load Current, Vin=36V
1
10
Figure 3. Efficiency vs Load Current, Vin=24V
100
5.01
90
5.00
Output Voltage (V)
Efficiency(%)
0.1
Output Current(A)
80
70
60
VIN=12V,VOUT=3.3V
50
4.99
4.98
VIN=24V, VOUT=5V
4.97
VIN=12V,VOUT=5V
VIN=12V,VOUT=5V
40
0.001
0.01
0.1
1
4.96
0.001
10
0.01
Output Current(A)
0.1
1
10
Output Current(A)
Figure 4. Efficiency vs Load Current, Vin=12V
Figure 5. Load Regulation (Vout=5V)
1,100
3.31
Switching Frequency (kHz)
1,000
Output Voltage (V)
3.31
3.30
3.30
900
800
700
600
500
400
300
200
3.29
0
10
20
30
40
100
0
100
Input Voltage (V)
200
300
400
500
600
RT (kΩ)
Figure 6. Line Regulation (Iout=5A)
Figure 7.Clock Frequency vs RT/CLK Resistor
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5
SCT2452
38
8
36
Quiescent Current (uA)
40
9
Shutdown Current (uA)
10
7
6
5
4
3
2
34
32
30
28
26
24
22
1
20
0
-50
-25
0
25
50
75
100
-50
125
-25
0
25
Temperature (ºC)
Figure 8． Shutdown Current vs Temperature
75
100
125
Figure 9.Quiescent Current vs Temperature
1.22
9.00
1.21
8.00
Ien_1P5V_post (uA)
EN Rising Threshold (V)
50
Temperature (ºC)
1.20
1.19
1.18
1.17
7.00
6.00
5.00
4.00
3.00
1.16
2.00
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (ºC)
25
50
75
100
125
Temperature (°C)
Figure 11. EN Pull-up Current vs Temperature
Figure 10. EN Threshold vs Temperature
0.808
10
0.806
8
0.802
Current ( A )
Vref (V)
0.804
0.800
0.798
0.796
6
4
2
0.794
0.792
-50
-25
0
25
50
75
100
125
0
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 12. Reference Voltage vs Temperature
6
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Figure 13. Peak Current Limit vs Temperature
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125
SCT2452
FUNCTIONAL BLOCK DIAGRAM
VIN
2
1.5uA
4uA
Thermal
Shutdown
20K
EN 3
+
EN LOGIC
VIN UVLO
Reference
1.21V
VREF
VCC
VCC
3uA
SS
HS MOSFET
Current limit
Boot
Charge
6
Slop
FB
5
0.8V
+
+ EA
+
+
Control
Logic
4
8
SW
7
GND
VCC
0.88V
RT/CLK
BOOT
Boot
UVLO
PWM
OVP
1
Oscillator
With PLL
CLK
LS MOSFET
Current limit
Figure 14. Functional Block Diagram
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7
SCT2452
OPERATION
Overview
The SCT2452 is a 3.8V-36V input, 5A output, EMI friendly synchronous buck converter with built-in 45mΩ Rdson
high-side and 20mΩ Rdson low-side power MOSFETs. It implements constant frequency peak current mode control
to regulate output voltage, providing excellent line and load transient response and simplifying the frequency
compensation design.
The switching frequency is programmable from 100kHz to 1.1MHz with two setting modes, resistor setting frequency
mode and the clock synchronization mode, to optimizes either the power efficiency or the external components’
sizes. The SCT2452 features a programmable soft-start time to avoid large inrush current and output voltage
overshoot during startup. The device also supports monolithic startup with pre-biased output condition. The
seamless mode-transition between PWM mode and PSM mode operations ensure high efficiency over wide load
current range. The quiescent current is typically 25uA under no load or sleep mode condition to achieve high
efficiency at light load.
The SCT2452 has a default input start-up voltage of 3.5V with 400mV hysteresis. The EN pin is a high-voltage pin
with a precision threshold that can be used to adjust the input voltage lockout thresholds with two external resistors
to meet accurate higher UVLO system requirements. Floating EN pin enables the device with the internal pull-up
current to the pin. Connecting EN pin to VIN directly starts up the device automatically.
The SCT2452 implements the Frequency Spread Spectrum FSS modulation spreading of ±6% centered selected
switching frequency. FSS improves EMI performance by not allowing emitted energy to stay in any one receiver
band for a significant length of time.
The SCT2452 full protection features include the input under-voltage lockout, the output over-voltage protection,
over current protection with cycle-by-cycle current limiting and hiccup mode, output hard short protection and
thermal shutdown protection.
Peak Current Mode Control
The SCT2452 employs fixed frequency peak current mode control. An internal clock initiates turning on the
integrated high-side power MOSFET Q1 in each cycle, then inductor current rises linearly. When the current through
high-side MOSFET reaches the threshold level set by the COMP voltage of the internal error amplifier, the highside MOSFET turns off. The synchronous low-side MOSFET Q2 turns on till the next clock cycle begins or the
inductor current falls to zero.
The error amplifier serves the COMP node by comparing the voltage of the FB pin with an internal 0.8V reference
voltage. When the load current increases, a reduction in the feedback voltage relative to the reference raises COMP
voltage till the average inductor current matches the increased load current. This feedback loop well regulates the
output voltage to the reference. The device also integrates an internal slope compensation circuitry to prevent subharmonic oscillation when duty cycle is greater than 50% for a fixed frequency peak current mode control.
The SCT2452 operates in Pulse Skipping Mode (PSM) with light load current to improve efficiency. When the load
current decreases, an increment in the feedback voltage leads COMP voltage drop. When COMP falls to a low
clamp threshold (400mV typically), device enters PSM. The output voltage decays due to output capacitor
discharging during skipping period. Once FB voltage drops lower than the reference voltage, and the COMP voltage
rises above low clamp threshold. Then high-side power MOSFET turns on in next clock pulse. After several
switching cycles with typical 1A peak inductor current, COMP voltage drops and is clamped again and pulse skipping
mode repeats if the output continues light loaded.
This control scheme helps achieving higher efficiency by skipping cycles to reduce switching power loss and gate
drive charging loss. The controller consumption quiescent current is 25uA during skipping period with no switching
to improve efficiency further.
Enable and Under Voltage Lockout Threshold
The SCT2452 is enabled when the VIN pin voltage rises about 3.5V and the EN pin voltage exceeds the enable
threshold of 1.18V. The device is disabled when the VIN pin voltage falls below 3.1V or when the EN pin voltage is
8
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SCT2452
below 1.1V. An internal 1.5uA pull up current source to EN pin allows the device enable when EN pin floats.
EN pin is a high voltage pin that can be connected to VIN directly to start up the device.
For a higher system UVLO threshold, connect an external resistor divider (R1 and R2) shown in Figure 15 from VIN
to EN. The UVLO rising and falling threshold can be calculated by Equation 1 and Equation 2 respectively.
Vrise = 1.18 ∗ (1 +
Vfall
VIN
R1
) − 1.5uA ∗ R1
R2
(1)
1.5uA
4uA
R1
EN
R1
= 1.1 ∗ (1 + ) − 5.5uA ∗ R1
R2
(2)
R2
20K
+
1.21V
where
•
Vrise is rising threshold of Vin UVLO
•
Vfall is falling threshold of Vin UVLO
Figure 15. System UVLO by enable divide
Output Voltage
The SCT2452 regulates the internal reference voltage at 0.8V with 1% tolerance over the operating temperature
and voltage range. The output voltage is set by a resistor divider from the output node to the FB pin. It is
recommended to use 1% tolerance or better resistors. Use Equation 3 to calculate resistance of resistor dividers.
To improve efficiency at light loads, larger value resistors are recommended. However, if the values are too high,
the regulator will be more susceptible to noise affecting output voltage accuracy.
𝑉𝑂𝑈𝑇
𝑅𝐹𝐵_𝑇𝑂𝑃 = (
− 1) ∗ 𝑅𝐹𝐵_𝐵𝑂𝑇
𝑉𝑅𝐸𝐹
(3)
where
•
RFB_TOP is the resistor connecting the output to the FB pin.
•
RFB_BOT is the resistor connecting the FB pin to the ground.
Programmable Soft-Start
The SCT2452 features programmable soft-start time to prevent inrush current during start-up stage. The soft-start
time can be programmed easily by connecting a soft-start capacitor Css (Css is the C6 on Figure 18) from SS pin to
ground.
The SS pin sources an internal 3µA current charging the external soft-start capacitor Css when the EN pin exceeds
turn-on threshold. The device adopts the lower voltage between the internal voltage reference 0.8V and the SS pin
voltage as the reference input voltage of the error amplifier and regulates the output. The soft-start completes when
the voltage at the SS pin exceeds the internal reference voltage of 0.8V.
The soft-start capacitor value can be calculated going with following equation 4. Attention should be taken here that
the programmed soft-start time should be larger than 4ms.
𝐶𝑠𝑜𝑓𝑡−𝑠𝑡𝑎𝑟𝑡 = 𝑡𝑠𝑠 ∗
Where:
•
•
3𝑢𝐴
0.8𝑉
(4)
CSS is the soft-start capacitor connected from SS pin to the ground
tss is the soft-start time
Switching Frequency and Clock Synchronization
The switching frequency of the SCT2452 is set by placing a resistor between RT/CLK pin and the ground, or
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SCT2452
synchronizing to an external clock.
In resistor setting frequency mode, a resistor placed between RT/CLK pin to the ground sets the switching frequency
over a wide range from 100KHz to 1.1MHz. The RT/CLK pin voltage is typical 0.5V. RT/CLK pin is not allowed to
be left floating or shorted to the ground. Use Equation 5 or the plot in Figure 16. to determine the resistance for a
switching frequency needed.
𝑅𝑇(𝐾𝛺) =
100000
𝑓𝑠𝑤(𝐾𝐻𝑧)
RT/CLK
(5)
Oscillator
With PLL
CLK
where,
Figure 16. Setting Frequency and Clock Synchronization
fsw is switching clock frequency
In clock synchronization mode, the switching frequency synchronizes to an external clock applied to RT/CLK pin.
The synchronization frequency range is from 100KHz to 1.1MHz and the rising edge of the SW synchronizes to the
falling edge of the external clock at RT/CLK pin with typical 66ns time delay. A square wave clock signal to RT/CLK
pin must have high level no lower than 2V, low level no higher than 0.4V, and pulse width larger than 80ns.
In applications where both resistor setting frequency mode and clock synchronization mode are needed, the device
can be configured as shown in Figure 16. Before an external clock is present, the device works in resistor setting
frequency mode. When an external clock presents, the device automatically transitions from resistor setting mode
to external clock synchronization mode. An internal phase locked loop PLL locks internal clock frequency onto the
external clock within typical 85us. The converter transitions from the clock synchronization mode to the resistor
setting frequency mode when the external clock disappears.
Frequency Spread Spectrum
To reduce EMI, the SCT2452 implements Frequency Spread Spectrum (FSS). The FSS circuitry shifts the switching
frequency of the regulator periodically within a certain frequency range around the programmed switching frequency.
The jittering span is ±6% of the switching frequency with 1/512 swing frequency. This frequency dithering function
is effective for both frequency programmed by resistor placed at RT/CLK pin and an external clock synchronization
application.
Bootstrap Voltage Regulator and Low Drop-out Operation
An external bootstrap capacitor between BOOT pin and SW pin powers the floating gate driver to high-side power
MOSFET. The bootstrap capacitor voltage is charged from an integrated voltage regulator when high-side power
MOSFET is off and low-side power MOSFET is on.
The UVLO of high-side MOSFET gate driver has rising threshold of 2.7V and hysteresis of 350mV. When the device
operates with high duty cycle or extremely light load, bootstrap capacitor may be not recharged in considerable long
time. The voltage at bootstrap capacitor is insufficient to drive high-side MOSFET fully on. When the voltage across
bootstrap capacitor drops below 2.35V, BOOT UVLO occurs. The converter forces turning on low-side MOSFET
periodically to refresh the voltage of bootstrap capacitor to guarantee the converter’s operation over a wide duty
range.
During the condition of ultra-low voltage difference from the input to the output, SCT2452 operates in Low Drop-Out
LDO mode. High-side MOSFET remains turning on as long as the BOOT pin to SW pin voltage is higher than BOOT
UVLO threshold 2.7V. When the voltage from BOOT to SW drops below 2.4V, the high-side MOSFET turns off and
low-side MOSFET turns on to recharge bootstrap capacitor periodically in the following several switching cycles.
Low-side MOSFET only turns on for 100ns in each refresh cycle to minimize the output voltage ripple. Low-side
MOSFET may turn on for several times till the bootstrap voltage is charged to higher than 2.7V for high-side
MOSFET working normally. The effective duty cycle of the converter during LDO operation can be approaching to
100%
10
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SCT2452
During slowing power up and power down application, the output voltage can closely track the input voltage ramping
down thanks to LDO operation mode. As the input voltage is reduced to near the output voltage, i.e. during slowing
power-up and power-down application, the off-time of the high side MOSFET starts to approach the minimum value.
Without LDO operation mode, beyond this point the switching may become erratic and/or the output voltage will fall
out of regulation. To avoid this problem the SCT2452 LDO mode automatically reduces the switching frequency to
increase the effective duty cycle and maintain regulation.
5.50
Vout (V)
5.00
4.50
0-A
1-A
2-A
4.00
3-A
4-A
5-A
3.50
4
4.5
5
5.5
6
6.5
Vin (V)
Figure 17. LDO Operation Characteristic ( Vout =5V )
Over Current Limit and Hiccup Mode
The inductor current is monitored during high-side MOSFET Q1 and low-side MOSFET Q2 on. The SCT2452
implements over current protection with cycle-by-cycle limiting high-side MOSFET peak current and low-side
MOSFET valley current to avoid inductor current running away during unexpected overload or output hard short
condition.
When overload or hard short happens, the converter cannot provide output current to satisfy loading requirement.
The inductor current is clamped at over current limitation. Thus, the output voltage drops below regulated voltage
with FB voltage less than internal reference voltage continuously. The COMP voltage ramps up to high clamp
voltage 3.7V typical. When COMP voltage is clamped for 512 cycles, the converter stops switching. After remaining
OFF for 8192 cycles，the device restarts from soft starting phase. If overload or hard short condition still exists
during soft-start and make COMP voltage clamped at high for 512 cycles，the device enters into turning-off mode
again. When overload or hard short condition is removed, the device automatically recovers to enters normal
regulating operation.
The hiccup protection mode above makes the average short circuit current to alleviate thermal issues and protect
the regulator.
Over voltage Protection
The SCT2452 implements the Over-voltage Protection OVP circuitry to minimize output voltage overshoot during
load transient, recovering from output fault condition or light load transient. The overvoltage comparator in OVP
circuit compares the FB pin voltage to the internal reference voltage. When FB voltage exceeds 110% of internal
0.8V reference voltage, the high-side MOSFET turns off to avoid output voltage continue to increase. When the FB
pin voltage falls below 105% of the 0.8V reference voltage, the high-side MOSFET can turn on again.
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SCT2452
Thermal Shutdown
The SCT2452 protects the device from the damage during excessive heat and power dissipation conditions. Once
the junction temperature exceeds 170C, the internal thermal sensor stops power MOSFETs switching. When the
junction temperature falls below 145C, the device restarts with internal soft start phase.
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APPLICATION INFORMATION
Typical Application
C12
0.1uF
BOOT
L1
5.5uH
C8
C9
47uF 47uF
VIN=3.8V~36V
VIN
R1
180K
C1
C3
C4
C5
C2
4.7uF 4.7uF 4.7uF 4.7uF 0.1uF
R2
43K
VOUT=3.3V IOUT=5A
SW
GND
C10
47uF
C11
47uF
EN
SS
RT/CLK
FB
C13
Optional
R5
31.6K
SCT2452
C6
10nF
R3
200K
R6
10.2K
Figure 18. SCT2452 Design Example, 3.3V Output with Programmable UVLO
Design Parameters
Design Parameters
Example Value
Input Voltage
24V Normal 3.8V to 36V
Output Voltage
3.3V
Maximum Output Current
5A
Switching Frequency
500 KHz
Output voltage ripple (peak to peak)
16.5mV
Transient Response 1.25A to 3.75A load step
∆Vout = 135mV
Start Input Voltage (rising VIN)
5.76V
Stop Input Voltage (falling VIN)
4.66V
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SCT2452
Output Voltage
The output voltage is set by an external resistor divider
R5 and R6 in typical application schematic.
Recommended R6 resistance is 10.2KΩ. Use equation
6 to calculate R5.
where:
𝑉𝑂𝑈𝑇
𝑅5 = (
− 1) ∗ 𝑅6
𝑉𝑅𝐸𝐹
Table 1. R5, R6Value for Common Output Voltage
(Room Temperature)
(6)
• VREF is the feedback reference voltage, typical
0.8V
VOUT
R5
R6
1.8 V
12.7 KΩ
10.2 KΩ
2.5 V
21.5 KΩ
10.2 KΩ
3.3 V
31.6 KΩ
10.2 KΩ
5 V
53.6 KΩ
10.2 KΩ
12 V
143 KΩ
10.2 KΩ
24V
294 KΩ
10.2 KΩ
Switching Frequency
Higher switching frequencies support smaller profiles of output inductors and output capacitors, resulting in lower
voltage and current ripples. However, the higher switching frequency causes extra switching loss, which downgrads
converter’s overall power efficiency and thermal performance. The 100ns minimum on-time limitation also restricts
the selection of higher switching frequency. In this design, a moderate switching frequency of 500 kHz is selected
to achieve both small solution size and high efficiency operation.
The resistor connected from RT/CLK to GND sets
switching frequency of the converter. The resistor value
required for a desired frequency can be calculated using
equation 7, or determined from Figure 7.
𝑅3 (KΩ) =
100000
Table 2. RFSW Value for Common Switching Frequencies
(Room Temperature)
(7)
fsw (KHz )
where:
•
fSW is the desired switching frequency
Fsw
R3 (RFSW)
200 KHz
500 KΩ
330 KHz
301 KΩ
500 KHz
200 KΩ
1100 KHz
90.9 KΩ
Under Voltage Lock-Out
An external voltage divider network of R1 from the input to EN pin and R2 from EN pin to the ground can set the
input voltage’s Under Voltage Lock-Out (UVLO) threshold. The UVLO has two thresholds, one for power up when
the input voltage is rising and the other for power down or brown outs when the input voltage is falling. For the
example design, the supply should turn on and start switching once the input voltage increases above 5.7V (start
or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 4.64 V
(stop or disable). Use Equation 8 and Equation 9 to calculate the values 173 kΩ and 42 kΩ of R1 and R2 resistors.
Vrise = 1.18 ∗ (1 +
Vfall = 1.1 ∗ (1 +
𝑅1
) − 1.5uA ∗ R1
𝑅2
𝑅1
) − 5.5uA ∗ 𝑅1
𝑅2
(8)
(9)
Inductor Selection
There are several factors should be considered in selecting inductor such as inductance, saturation current, the
RMS current and DC resistance(DCR). Larger inductance results in less inductor current ripple and therefore leads
to lower output voltage ripple. However, the larger value inductor always corresponds to a bigger physical size,
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higher series resistance, and lower saturation current. A good rule for determining the inductance to use is to allow
the inductor peak-to-peak ripple current to be approximately 20%~40% of the maximum output current.
The peak-to-peak ripple current in the inductor ILPP can be calculated as in Equation 10.
𝐼𝐿𝑃𝑃 =
Where
•
•
•
•
•
𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
𝑉𝐼𝑁 ∗ 𝐿 ∗ 𝑓𝑆𝑊
(10)
ILPP is the inductor peak-to-peak current
L is the inductance of inductor
fSW is the switching frequency
VOUT is the output voltage
VIN is the input voltage
Since the inductor-current ripple increases with the input voltage, so the maximum input voltage in application is
always used to calculate the minimum inductance required. Use Equation 11 to calculate the inductance value.
𝐿𝑀𝐼𝑁 =
Where
•
•
•
•
•
•
𝑉𝑂𝑈𝑇
𝑉𝑂𝑈𝑇
∗ (1 −
)
𝑓𝑆𝑊 ∗ 𝐿𝐼𝑅 ∗ 𝐼𝑂𝑈𝑇(𝑚𝑎𝑥)
𝑉𝐼𝑁(𝑚𝑎𝑥)
(11)
LMIN is the minimum inductance required
fsw is the switching frequency
VOUT is the output voltage
VIN(max) is the maximum input voltage
IOUT(max) is the maximum DC load current
LIR is coefficient of ILPP to IOUT
The total current flowing through the inductor is the inductor ripple current plus the output current. When selecting
an inductor, choose its rated current especially the saturation current larger than its peak operation current and
RMS current also not be exceeded. Therefore, the peak switching current of inductor, ILPEAK and ILRMS can be
calculated as in equation 12 and equation 13.
𝐼𝐿𝑃𝐸𝐴𝐾 = 𝐼𝑂𝑈𝑇 +
𝐼𝐿𝑃𝑃
2
𝐼𝐿𝑅𝑀𝑆 = √(𝐼𝑂𝑈𝑇 )2 +
Where
•
•
•
•
(12)
1
∗ (𝐼𝐿𝑃𝑃 )2
12
(13)
ILPEAK is the inductor peak current
IOUT is the DC load current
ILPP is the inductor peak-to-peak current
ILRMS is the inductor RMS current
In overloading or load transient conditions, the inductor peak current can increase up to the switch current limit of
the device which is typically 8A. The most conservative approach is to choose an inductor with a saturation current
rating greater than 8A. Because of the maximum ILPEAK limited by device, the maximum output current that the
SCT2452 can deliver also depends on the inductor current ripple. Thus, the maximum desired output current also
affects the selection of inductance. The smaller inductor results in larger inductor current ripple leading to a higher
maximum output current.
For this design, use LIR=0.2 or 0.3, and the inductor value is calculated to be 5uH, the RMS inductor current is 6A
and the peak inductor current is 7.2A. The chosen inductor is a WE 744325550, which has a saturation current
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SCT2452
rating of 12A and a RMS current rating of 10A. This also has a typical inductance of 5.5µH at no load and 4.7 µH
at 6A load. The inductor DCR is 10.3 mΩ.
Input Capacitor Selection
The input current to the step-down DCDC converter is discontinuous, therefore it requires a capacitor to supply the
AC current to the step-down DCDC converter while maintaining the DC input voltage. Use capacitors with low ESR
for better performance. Ceramic capacitors with X5R or X7R dielectrics are usually suggested because of their low
ESR and small temperature coefficients, and it is strongly recommended to use another lower value capacitor (e.g.
0.1uF) with small package size (0603) to filter high frequency switching noise. Place the small size capacitor as
close to VIN and GND pins as possible.
The voltage rating of the input capacitor must be greater than the maximum input voltage. And the capacitor must
also have a ripple current rating greater than the maximum input current ripple. The RMS current in the input
capacitor can be calculated using Equation 14.
ICINRMS = IOUT ∗ √
VOUT
VOUT
∗ (1 −
)
VIN
VIN
(14)
The worst case condition occurs at VIN=2*VOUT, where:
(15)
ICINRMS = 0.5 ∗ IOUT
For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load
current.
When selecting ceramic capacitors, it needs to consider the effective value of a capacitor decreasing as the DC
bias voltage across a capacitor increases.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 16 and the maximum input voltage ripple occurs at 50% duty cycle.
∆VIN =
IOUT
VOUT
VOUT
∗
∗ (1 −
)
fSW ∗ CIN VIN
VIN
(16)
For this example, three 4.7μF, X7R ceramic capacitors rated for 50 V in parallel are used. And a 0.1 μF for highfrequency filtering capacitor is placed as close as possible to the device pins.
Bootstrap Capacitor Selection
A 0.1μF ceramic capacitor must be connected between BOOT pin and SW pin for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10V or higher voltage
rating.
Output Capacitor Selection
The selection of output capacitor will affect output voltage ripple in steady state and load transient performance.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through
the Equivalent Series Resistance ESR of the output capacitors and the other is caused by the inductor current ripple
charging and discharging the output capacitors. To achieve small output voltage ripple, choose a low-ESR output
capacitor like ceramic capacitor. For ceramic capacitors, the capacitance dominates the output ripple. For
simplification, the output voltage ripple can be estimated by Equation 17 desired.
∆VOUT =
𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
(17)
8 ∗ 𝑓𝑆𝑊 2 ∗ 𝐿 ∗ 𝐶𝑂𝑈𝑇 ∗ 𝑉𝐼𝑁
Where
• ΔVOUT is the output voltage ripple
16
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•
•
•
•
•
fSW is the switching frequency
L is the inductance of inductor
COUT is the output capacitance
VOUT is the output voltage
VINis the input voltage
Due to capacitor’s degrading under DC bias, the bias voltage can significantly reduce capacitance. Ceramic
capacitors can lose most of their capacitance at rated voltage. Therefore, leave margin on the voltage rating to
ensure adequate effective capacitance. Typically, two 47μF ceramic output capacitors work for most applications.
Inverting Power application
The SCT2452 can be used to convert a positive input voltage to a negative output voltage. Typical applications
are amplifiers requiring a negative power supply.
C3
BOOT
L1
GND
SW
VIN
VIN
GND
SCT2452
C1
C2
EN
SS
RT/CLK
FB
C4
R1
C5
R2
R4
VOUT
Figure 19. SCT2452 Inverting Power Supply
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SCT2452
Application Waveforms
18
Figure 20. Power up
Figure 21. Power down
Figure 22.Load Transient (0.5A-4.5A, 250mA/us)
Figure 23. Load Transient (1.5A-3.5A, 250mA/us)
Figure 24. SW and Vout Ripple
Figure 25. Thermal, 3.3Vout/5A
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Layout Guideline
Proper PCB layout is a critical for SCT2452’s stable and efficient operation. The traces conducting fast switching
currents or voltages are easy to interact with stray inductance and parasitic capacitance to generate noise and
degrade performance. For better results, follow these guidelines as below:
1. Power grounding scheme is very critical because of carrying power, thermal, and glitch/bouncing noise
associated with clock frequency. The thumb of rule is to make ground trace lowest impendence and power are
distributed evenly on PCB. Sufficiently placing ground area will optimize thermal and not causing over heat area.
2. Place a low ESR ceramic capacitor as close to VIN pin and the ground as possible to reduce parasitic effect.
3. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. Make
sure top switching loop with power have lower impendence of grounding.
4. The bottom layer is a large ground plane connected to the ground plane on top layer by vias. The power pad
should be connected to bottom PCB ground planes using multiple vias directly under the IC. The center thermal
pad should always be soldered to the board for mechanical strength and reliability, using multiple thermal vias
underneath the thermal pad. Improper soldering thermal pad to ground plate on PCB will cause SW higher ringing
and overshoot besides downgrading thermal performance. it is recommended 8mil diameter drill holes of thermal
vias, but a smaller via offers less risk of solder volume loss. On applications where solder volume loss thru the vias
is of concern, plugging or tenting can be used to achieve a repeatable process.
5. Output inductor should be placed close to the SW pin. The area of the PCB conductor minimized to prevent
excessive capacitive coupling.
6. The RT/CLK terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC
and routed with minimal lengths of trace.
7. UVLO adjust and RT resistors, soft start components should connect to small signal ground which must return
to the GND pin without any interleaving with power ground.
8. Route BOOT capacitor trace on the other layer than top layer to provide wide path for topside ground.
9. For achieving better thermal performance, a four-layer layout is strongly recommended.
VOUT
Output capacitors
GND
Inductor
Top layer ground area
Via
Input bypass
capacitor
Via
1
BOOT
SW
VIN
VIN
GND
Programmable
UVLO resistors
EN
SS
Thermal VIA
RT/CLK
FB
Small signal
ground
Softstart
Capacitor
Feedback resistors
Freq. set resistor
GND
Top layer ground area
Figure 26. PCB Layout Example
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SCT2452
PACKAGE INFORMATION
eSOP8/PP(95x130) Package Outline Dimensions
Symbol
A
A1
A2
b
c
D
D1
E
E1
E2
e
L
Dimensions in Millimeters
Min.
Max.
1.300
1.700
0.000
0.100
1.350
1.550
0.330
0.510
0.170
0.250
4.700
5.100
3.050
3.250
3.800
4.000
5.800
6.200
2.160
2.360
1.270(BSC)
Dimensions in Inches
Min.
Max.
0.051
0.067
0.000
0.004
0.053
0.061
0.013
0.020
0.007
0.010
0.185
0.201
0.120
0.128
0.150
0.157
0.228
0.244
0.085
0.093
0.050(BSC)
0.400
0°
0.016
0°
1.270
8°
0.050
8°
NOTE:
1.
2.
3.
4.
5.
6.
Drawing proposed to be made a JEDEC package outline MO-220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not include mold flash.
Contact PCB board fabrication for minimum solder mask web tolerances between the pins.
TAPE AND REEL INFORMATION
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SCT2452
RELATED PARTS
PART NUMBERS
SCT2451
SCT2430A
SCT2431A
SCT2430
SCT2432
SCT2433
DESCRIPTION
COMMENTS
36V Vin, 5A Synchronous Step-down
DCDC Converter with Adjustable Soft
Start Time
36V Vin, 3.5A Synchronous Step-down
DCDC Converter with 100KHz-1.1MHz
Programmable Switching Frequency
36V Vin, 3.5A Synchronous Step-down
DCDC Converter with Adjustable Soft
Start Time
40V Vin, 3.5A Synchronous Step-down
DCDC Converter with 100KHz-2.2MHz
Programmable Switching Frequency
40V Vin, 3.5A Synchronous Step-down
DCDC Converter with 100KHz-2.2MHz
Programmable Switching Frequency,
Programmable Soft Start Time and
Internal-compensation
40V Vin, 3.5A Synchronous Step-down
DCDC Converter
C3
BOOT
VIN
45mΩ / 20mΩ HS/LS MOSFETs
Programmable soft start time
Freq. = 570KHz
55mΩ / 30mΩ HS/LS MOSFETs
Internal 4ms Soft-time
Freq. = 100KHz-1.1MHz adjustable.
Clock synchronization
55mΩ / 30mΩ HS/LS MOSFETs
Programmable soft start time
Freq. = 570KHz
80mΩ / 50mΩ HS/LS MOSFETs
Internal 4ms Soft-time
Freq. = 100KHz-2.2MHz adjustable.
Clock synchronization
80mΩ / 50mΩ HS/LS MOSFETs
Programmable soft start time
Freq. = 100KHz-2.2MHz adjustable.
Clock synchronization
Internal Compensation
80mΩ / 50mΩ HS/LS MOSFETs
Internal 2ms Soft-time
Freq. = 570kHz Fix.
Clock synchronization
L1
SW
C5
VIN
GND
SCT2451
EN
COMP
C1 C2
SS
FB
VOUT
R1
R3
C4
R2
C6
Figure 27. SCT2451 Typical Application
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee the third
party Intellectual Property rights are not infringed upon when integrating Silicon Content Technology (SCT) products into any
application. SCT will not assume any legal responsibility for any said applications.
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