Industrial eMMC Datasheet
FEMDRW008G - 88 A 37
FEMDRW016G - 88 A 37
FORESEE
®
Industrial eMMC Datasheet
A-00031
FEMDRW008G-88A37
FEMDRW016G-88A37
Version 1.0
LONGSYS ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an “AS IS” basis, without
warranties of any kind. All brand names, trademarks and registered trademarks belong to their respective owners.
This document and all information discussed herein remain the sole and exclusive property of Longsys Electronics. No license of any patent, copyright,
mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel
or other-wise.
For updates or additional information about Longsys products, contact your nearest Longsys office.
2020 Shenzhen Longsys Electronics Co., Ltd. All rights reserved.
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Industrial eMMC Datasheet
FEMDRW008G - 88 A 37
FEMDRW016G - 88 A 37
Revision History
Rev.
Date
Changes
Editor
1.0
2020/05/11
Document Create.
MSG
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Industrial eMMC Datasheet
FEMDRW008G - 88 A 37
FEMDRW016G - 88 A 37
CONTENTS
Revision History ............................................................................................................................................................ 2
CONTENTS .................................................................................................................................................................... 3
1
INTRODUCTION ..................................................................................................................................................... 5
2
PRODUCT LIST ...................................................................................................................................................... 5
3
KEY FEATURES ...................................................................................................................................................... 5
4
PACKAGE CONFIGURATIONS .............................................................................................................................. 6
5
6
4.1
Ball Pin Configuration .................................................................................................................................... 6
4.2
Package Dimension ....................................................................................................................................... 8
PRODUCT SPECIFICATIONS................................................................................................................................. 9
5.1
Write/Read Performance ............................................................................................................................... 9
5.2
Power Consumption ....................................................................................................................................... 9
5.2.1
Active Power Consumption During Operation ...................................................................................... 9
5.2.2
Low power mode (stand-by) ................................................................................................................ 10
5.2.3
Low power mode (sleep) ...................................................................................................................... 10
Technical Notes................................................................................................................................................... 11
6.1
Functional Description ................................................................................................................................. 11
6.2
Interface timing mode .................................................................................................................................. 12
6.3
System Architecture ..................................................................................................................................... 12
6.4
Partition Management ................................................................................................................................. 13
6.5
Automatic Sleep Mode................................................................................................................................. 15
6.6
Sleep (CMD5) ................................................................................................................................................ 16
6.7
H/W Reset operation .................................................................................................................................... 16
6.8
Initial Data Acceleration(IDA) ...................................................................................................................... 16
6.9
High-speed mode selection ......................................................................................................................... 17
6.10
Bus width selection .................................................................................................................................. 17
6.11
Partition Configuration ............................................................................................................................. 17
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Industrial eMMC Datasheet
FEMDRW008G - 88 A 37
FEMDRW016G - 88 A 37
6.12
7
Reference Schematics ............................................................................................................................. 18
REGISTER VALUE ................................................................................................................................................ 19
7.1
CID register ................................................................................................................................................... 19
7.2
CSD register .................................................................................................................................................. 20
7.3
Extended CSD register ................................................................................................................................. 22
7.4
OCR Register ................................................................................................................................................. 30
7.5
Field firmware update(FFU) ......................................................................................................................... 31
7.5.1
Longsys eMMC (FEMDRWxxxG-88A37) Field F/W update flow - CMD sequence ........................... 31
7.5.2
SUPPORTED_MODE [493] (Read Only) ................................................................................................ 31
7.5.3
FFU_FEATURE [492] (Read Only) ......................................................................................................... 32
7.5.4
FFU_ARG [490-487] (Read Only) .......................................................................................................... 32
7.5.5
FW_CONFIG[169] (R/W) ........................................................................................................................ 32
7.5.6
FFU_STATUS [26] (R/W/E_P) ............................................................................................................... 32
7.5.7
OPERATION_CODES_TIMEOUT[491](Read Only) ............................................................................... 33
7.5.8
MODE_OPERATION_CODES[29] (W/E_P) ............................................................................................ 33
7.6
1
S.M.A.R.T. Health Report ............................................................................................................................. 33
INTRODUCTION
FORESEE eMMC is an embedded storage solution designed in the BGA package. The FORESEE eMMC consists of NAND
flash and eMMC controller. The controller could manage the interface protocols, wearleveling, bad block management
and ECC.
FORESEE eMMC has high performance at a competitive cost, high quality and low power consumption, and eMMC is
compatible with JEDEC standard eMMC 5.1 specifications.
2
PRODUCT LIST
Table 1. Product List
Capacity
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Part Number
NAND Flash Type
User Density
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Package Size(mm)
Package Type
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Industrial eMMC Datasheet
FEMDRW008G - 88 A 37
FEMDRW016G - 88 A 37
8GB
FEMDRW008G-88A37
64Gb x1
7.28GB
11.5
13.0
1.0
153 FBGA
16GB
FEMDRW016G-88A37
128Gb x1
14.5GB
11.5
13.0
1.0
153 FBGA
- Storage without operation: -40℃ ~
+85℃
3
Sudden-Power-Loss safeguard
Hardware ECC engine
Unique firmware backup mechanism
Global-wear-leveling Supported
features.
- HS400, HS200
- Partitioning, RPMB
- Boot feature, boot partition
- HW Reset/SW Reset
- Discard, Trim, Erase, Sanitize
- Background operations, HPI
- Enhanced reliable write
- S.M.A.R.T. Health Report
- FFU
- Sleep / awake
KEY FEATURES
eMMC5.1 specification compatibility
- Backward compatible to eMMC4.41/4.5/5.0
Bus mode
- Data bus width: 1 bit (default), 4 bits, 8 bits
- Data transfer rate: up to 400MB/s (HS400)
- MMC I/F Clock frequency: 0~200MHz
Operating voltage range
- VCC(NAND): 2.7 ~ 3.6V
- VCCQ(Controller): 1.7 ~ 1.95V / 2.7 ~ 3.6V
Temperature
Others
- Compliance with the RoHS Directive
- Operation: -40℃ ~ +85℃
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Industrial eMMC Datasheet
FEMDRW008G - 88 A 37
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4
PACKAGE CONFIGURATIONS
4.1
Ball Pin Configuration
Figure 1. Ball Array (Top View through package)
Table 2. Ball Array Description
Pin No.
Pin Name
Description
A3
DAT0
A4
DAT1
A5
DAT2
B2
DAT3
data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-DAT7, by the eMMC host controller.
B3
DAT4
The eMMC device includes internal pull-ups for data lines DAT1-DAT7.
B4
DAT5
B5
DAT6
B6
DAT7
K5
RSTN
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These are bidirectional data signal. The DAT signals operate in push-pull mode. Only the device or the host is
driving these signals at a time. By default, after power up or reset, only DAT0 is used for data transfer. A wider
Immediately after entering the 4-bit mode, the device disconnects the internal pull ups of lines DAT1, DAT2, and
DAT3. Correspondingly, immediately after entering to the 8-bit mode the device disconnects the internal pull-ups
of lines DAT1–DAT7
Hardware Reset Input
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Pin No.
Pin Name
C6
VCCQ
M4
VCCQ
N4
VCCQ
P3
VCCQ
P5
VCCQ
E6
VCC
F5
VCC
J10
VCC
K9
VCC
C2
VDDi
Description
VCCQ is the power supply line for host interface, have two power mode: High power mode:2.7V~3.6V; Lower
power mode:1.7V~1.95V.
VCC is the power supply line for internal flash memory, its power voltage range is:2.7V~3.6V.
VDDi is internal power node, not the power supply. Connect 1uF capacitor VDDi to ground.
This signal is a bidirectional command channel used for device initialization and command transfer.
M5
CMD
H5
DS
M6
CLK
J5
VSS
A6
VSS
C4
VSS
E7
VSS
G5
VSS
H10
VSS
K8
VSS
N2
VSS
N5
VSS
P4
VSS
P6
VSS
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Commands are sent from the host to the device, and responses are sent from the device to the host. The CMD
Signal has 2 operation modes: open drain for initialization, and push-pull for command transfer.
Data Strobe signal. Newly assigned pin for HS400 mode. Data Strobe is generated from eMMC to host.
In HS400 mode, read data and CRC response are synchronized with Data Strobe.
Each cycle of this signal directs a one-bit transfer on the command and either a one-bit (1x) or a twobits transfer
(2x) on all the data lines.
Ground connections
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Industrial eMMC Datasheet
FEMDRW008G - 88 A 37
FEMDRW016G - 88 A 37
4.2
Package Dimension
Figure 2. Package Dimension
5
PRODUCT SPECIFICATIONS
5.1
Write/Read Performance
Table 3. Write/Read Performance
Part Number
Write
Read
FEMDRW008G-88A37
Up to 110 MB/s
Up to 235 MB/s
FEMDRW016G-88A37
Up to 110 MB/s
Up to 235 MB/s
Note:
Test Condition: Bus width x8, 200MHz DDR, 512KB data transfer, w/o file system overhead, measured on internal board.
Test tool: uBOOT (Without O/S)
Chunk size: 1MB
Test area: 100MB/ Full-range of LBA.
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Industrial eMMC Datasheet
FEMDRW008G - 88 A 37
FEMDRW016G - 88 A 37
5.2
Power Consumption
Active Power Consumption During Operation
Table 4. Active Power Consumption During Operation
Part Number
ICC
ICCQ
FEMDRW008G-88A37
70mA
120mA
FEMDRW016G-88A37
80mA
120mA
VCC = 3.3V & VCCQ = 1.8V.
The measurement for max RMS current is the average RMS current consumption over a period of 100ms.
Low power mode (stand-by)
Table 5. Low power mode (stand-by)
Part Number
ICC
ICCQ
FEMDRW008G-88A37
70uA
150uA
FEMDRW016G-88A37
80uA
150uA
Power Measurement conditions: Bus configuration =x8 @200MHz DDR, 23
Standby: NAND Flash VCC & Controller VCCQ power supply is switched on.
The measurement for max RMS current is the average RMS current consumption over a period of 100ms.
Low power mode (sleep)
Table 6. Low power mode (sleep)
Part Number
ICC
ICCQ
FEMDRW008G-88A37
0
150uA
FEMDRW016G-88A37
0
150uA
Power Measurement conditions: Bus configuration =x8 @200MHz DDR, 23
Sleep: NAND Flash VCC power supply is switched off (Controller VCCQ on)
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Industrial eMMC Datasheet
FEMDRW008G - 88 A 37
FEMDRW016G - 88 A 37
The measurement for max RMS current is the average RMS current consumption over a period of 100ms.
6
Technical Notes
6.1
Functional Description
FORESEE eMMC with powerful L2P (Logical to Physical) NAND Flash management algorithm provides unique functions:
⚫ Host independence from details of operating NAND flash
The eMMC Controller already includes Flash management technologies such as data storage and retrieval, defect
handling and diagnostics, and power management. Host can be free from considering about NAND Flash data
operating.
⚫ Internal ECC to correct defect in NAND flash
The hardware error correction code (ECC) function, which can prevent data corruption data corruption is included in
the eMMC controller.
⚫ Sudden-Power-Loss Safeguard
To prevent from data loss, a mechanism named Sudden-Power-Loss Safeguard is added in the eMMC. In the case of
sudden power-failure, the eMMC would work properly after power cycling.
⚫ Global-wear-leveling
To achieve the best stability and device endurance, this eMMC equips the Global Wear Leveling algorithm. It
ensures that not only normal area, but also the frequently accessed area, such as FAT, would be programmed and
erased evenly.
⚫ IDA (Initial Data Acceleration)
The eMMC prevents the pre-burned data from data-loss with IDA, in case of our customer had pre-burned data to
eMMC, before the eMMC being SMT.
⚫ Cache
The eMMC enhanced the data written performance with Cache, with which our customer would get more
endurance and reliability.
6.2
Interface timing mode
FORESEE eMMC support supports high speed DDR interface timing mode up to 400MB/s at 200MHz with 1.8V I/O
supply.
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Table 7. Device Type Value (EXT_CSD register : DEVICE_TYPE [196])
6.3
Bit
Device Type
Supportability
7
HS400 Dual Data Rate eMMC at 200 MHz – 1.2 V I/O
Not support
6
HS400 Dual Data Rate eMMC at 200 MHz – 1.8 V I/O
Support
5
HS200 Single Data Rate eMMC at 200 MHz - 1.2 V I/O
Not support
4
HS200 Single Data Rate eMMC at 200 MHz - 1.8 V I/O
Support
3
High-Speed Dual Data Rate eMMC at 52 MHz - 1.2 V I/O
Not support
2
High-Speed Dual Data Rate eMMC at 52 MHz - 1.8 V or 3.3 V I/O
Support
1
High-Speed eMMC at 52 MHz - at rated device voltage(s)
Support
0
High-Speed eMMC at 26 MHz - at rated device voltage(s)
Support
System Architecture
The eMMC can be operated in 1-bit, 4-bit, or 8-bit mode. NAND flash memory is managed by a controller inside, which
manages ECC, wear leveling and bad block management. The eMMC provides easy integration with the host process
that all flash management hassles are invisible to the host.
Figure 3. eMMC System Architecture
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6.4
Partition Management
The embedded device offers also the possibility of configuring by the host additional split local memory partitions with
independent addressable space starting from logical address 0x00000000 for different usage models. Default size of
each Boot Area Partition is 4096 KB and can be changed by Vendor Command as multiple of 128KB. Boot area partition
size is calculated as (128KB * BOOT_SIZE_MULTI) The size of Boot Area Partition 1 and 2 cannot be set independently
and is set as same value Boot area partition which is enhanced partition. Therefore, memory block area scan is classified
as follows:
⚫ Factory configuration supplies boot partitions.
⚫ The RPMB partition is 4MB.
⚫ The host is free to configure one segment in the User Data Area to be implemented as enhanced storage media,
and to specify its starting location and size in terms of Write Protect Groups. The attributes of this Enhanced User
Data Area can be programmed only once during the device life-cycle (one-time programmable).
⚫ Up to four General Purpose Area Partitions can be configured to store user data or sensitive data, or for other host
usage models. The size of these partitions is a multiple of the write protect group. Size and attributes can be
programmed once in device life-cycle (one-time programmable). Each of the GeneralPurpose Area Partitions can
be implemented with enhanced technological features.
Figure 4 Partitions and user data area configuration
In boot operation mode, the master can read boot data from the slave (device) by keeping CMD line low or sending
CMD0 with argument + 0xFFFFFFFA, before issuing CMD1. The data can be read from either boot area or user area
depending on register setting.
Table 8. Boot ack, boot data and initialization Time
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FEMDRW008G - 88 A 37
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Timing Factor
Value
Boot ACK Time
< 50 ms
Boot Data Time
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