PMS171B
8bit OTP MCU with 8-bit ADC
Datasheet
Version 1.00 – Nov. 7, 2018
Copyright 2018 by PADAUK Technology Co., Ltd., all rights reserved
6F-6, No.1, Sec. 3, Gongdao 5th Rd., Hsinchu City 30069, Taiwan, R.O.C.
TEL: 886-3-572-8688
www.padauk.com.tw
PMS171B
8bit OTP MCU with 8-bit ADC
IMPORTANT NOTICE
PADAUK Technology reserves the right to make changes to its products or to terminate
production of its products at any time without notice. Customers are strongly
recommended to contact PADAUK Technology for the latest information and verify
whether the information is correct and complete before placing orders.
PADAUK Technology products are not warranted to be suitable for use in life-support
applications or other critical applications. PADAUK Technology assumes no liability for
such applications. Critical applications include, but are not limited to, those which may
involve potential risks of death, personal injury, fire or severe property damage.
PADAUK Technology assumes no responsibility for any issue caused by a customer’s
product design. Customers should design and verify their products within the ranges
guaranteed by PADAUK Technology. In order to minimize the risks in customers’ products,
customers should design a product with adequate operating safeguards.
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
Table of content
1. Features ................................................................................................................................. 8
1.1.
Special Features .....................................................................................................................8
1.2.
System Features .....................................................................................................................8
1.3.
CPU Features .........................................................................................................................8
1.4.
Package Information ...............................................................................................................8
2. General Description and Block Diagram ............................................................................ 9
3. Pin Definition and Functional Description ....................................................................... 10
4. Device Characteristics ....................................................................................................... 16
4.1.
AC/DC Device Characteristics ..............................................................................................16
4.2.
Absolute Maximum Ratings...................................................................................................18
4.3.
Typical ILRC frequency vs. VDD ...........................................................................................18
4.4.
Typical IHRC frequency deviation vs. VDD (calibrated to 16MHz)......................................... 19
4.5.
Typical ILRC Frequency vs. Temperature .............................................................................19
4.6.
Typical IHRC Frequency vs. Temperature (calibrated to 16MHz) .......................................... 20
4.7.
Typical operating current vs. VDD @ system clock = ILRC/n ................................................ 20
4.8.
Typical operating current vs. VDD @ system clock = IHRC/n ...............................................21
4.9.
Typical operating current vs. VDD @ system clock = 4MHz EOSC / n .................................. 21
4.10.
Typical operating current vs. VDD @ system clock = 32KHz EOSC / n................................. 22
4.11.
Typical operating current vs. VDD @ system clock = 1MHz EOSC / n .................................. 22
4.12.
Typical IO driving current (IOH) and sink current (IOL) .............................................................23
4.13.
Typical IO input high/low threshold voltage (VIH/VIL) ..............................................................25
4.14.
Typical resistance of IO pull high device ...............................................................................25
4.15.
Typical resistance of IO pull Low device................................................................................26
4.16.
Typical power down current (IPD) and power save current (IPS) .............................................. 26
4.17.
Timing charts for boot up conditions......................................................................................27
5. Functional Description ....................................................................................................... 28
5.1.
Program Memory - OTP ........................................................................................................28
5.2.
Boot Procedure .....................................................................................................................28
5.3.
Data Memory - SRAM ...........................................................................................................29
5.4.
Oscillator and clock ...............................................................................................................29
5.4.1. Internal High RC oscillator and Internal Low RC oscillator ......................................... 29
5.4.2. Chip calibration ..........................................................................................................29
5.4.3. IHRC Frequency Calibration and System Clock ........................................................30
5.4.4. External Crystal Oscillator .........................................................................................31
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
5.4.5. System Clock and LVR level .....................................................................................33
5.4.6. System Clock Switching ............................................................................................34
5.5.
Comparator ...........................................................................................................................35
5.5.1
Internal reference voltage (Vinternal R) ...........................................................................36
5.5.2
Using the comparator ................................................................................................38
5.5.3
Using the comparator and band-gap 1.20V ...............................................................39
5.6
16-bit Timer (Timer16) ..........................................................................................................40
5.7
8-bit Timer (Timer2/Timer3) with PWM generation ................................................................41
5.7.1
Using the Timer2 to generate periodical waveform ....................................................43
5.7.2
Using the Timer2 to generate 8-bit PWM waveform...................................................44
5.7.3
Using the Timer2 to generate 6-bit / 7-bit PWM waveform ......................................... 46
5.8
WatchDog Timer ...................................................................................................................47
5.9
Interrupt ................................................................................................................................48
5.10
Power-Save and Power-Down ..............................................................................................50
5.10.1 Power-Save mode (“stopexe”) ...................................................................................50
5.10.2 Power-Down mode (“stopsys”) ..................................................................................51
5.10.3 Wake-up ....................................................................................................................52
5.11
IO Pins ..................................................................................................................................52
5.12
Reset and LVR......................................................................................................................55
5.12.1 Reset .........................................................................................................................55
5.12.2 LVR reset ..................................................................................................................55
5.13
Analog-to-Digital Conversion (ADC) module .........................................................................55
5.13.1 The input requirement for AD conversion ..................................................................56
5.13.2 Select the reference high voltage ..............................................................................57
5.13.3 ADC clock selection...................................................................................................57
5.13.4 Configure the analog pins ..........................................................................................57
5.13.5 Using the ADC...........................................................................................................57
6. IO Registers ........................................................................................................................ 59
6.1.
ACC Status Flag Register (flag), IO address = 0x00 .............................................................59
6.2.
Stack Pointer Register (sp), IO address = 0x02 ....................................................................59
6.3.
Clock Mode Register (clkmd), IO address = 0x03 .................................................................59
6.4.
Interrupt Enable Register (inten), IO address = 0x04 ............................................................60
6.5.
Interrupt Request Register (intrq), IO address = 0x05 ...........................................................60
6.6.
Timer16 mode Register (t16m), IO address = 0x06...............................................................61
6.7.
Timer2 Bound Register (tm2b), IO address = 0x09 ...............................................................61
6.8.
External Oscillator setting Register (eoscr), IO address = 0x0a............................................. 61
6.9.
Interrupt Edge Select Register (integs), IO address = 0x0c ...................................................62
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
6.10.
Port A Digital Input Enable Register (padier), IO address = 0x0d .......................................... 62
6.11.
Port B Digital Input Enable Register (pbdier), IO address = 0x0e .......................................... 62
6.12.
Port A Data Register (pa), IO address = 0x10 .......................................................................63
6.13.
Port A Control Register (pac), IO address = 0x11 .................................................................63
6.14.
Port A Pull-High Register (paph), IO address = 0x12 ............................................................63
6.15.
Port B Data Register (pb), IO address = 0x14 .......................................................................63
6.16.
Port B Control Register (pbc), IO address = 0x15 .................................................................63
6.17.
Port B Pull-High Register (pbph), IO address = 0x16 ............................................................63
6.18.
Port B Pull Low Register (pbpl), IO address = 0x38 ..............................................................63
6.19.
Miscellaneous Register (misc), IO address = 0x17................................................................64
6.20.
Comparator Control Register (gpcc), IO address = 0x18 .......................................................64
6.21.
Comparator Selection Register (gpcs), IO address = 0x19 ....................................................65
6.22.
Timer2 Control Register (tm2c), IO address = 0x1c ..............................................................65
6.23.
Timer2 Counter Register (tm2ct), IO address = 0x1d ............................................................65
6.24.
Timer2 Scalar Register (tm2s), IO address = 0x1e................................................................66
6.25.
Timer3 Control Register (tm3c), IO address = 0x32 ..............................................................66
6.26.
Timer3 Counter Register (tm3ct), IO address = 0x33 ............................................................66
6.27.
Timer3 Scalar Register (tm3s), IO address = 0x34................................................................67
6.28.
Timer3 Bound Register (tm3b), IO address = 0x3f ................................................................67
6.29.
ADC Control Register (adcc), IO address = 0x3b ..................................................................67
6.30.
ADC Mode Register (adcm), IO address = 0x3c....................................................................68
6.31.
ADC Regulator Control Register (adcrgc), IO address = 0x3d............................................... 68
6.32.
ADC Result High Register (adcr), IO address = 0x3e ............................................................68
7. Instructions ......................................................................................................................... 69
7.1.
Data Transfer Instructions .....................................................................................................70
7.2.
Arithmetic Operation Instructions ..........................................................................................72
7.3.
Shift Operation Instructions ...................................................................................................74
7.4.
Logic Operation Instructions..................................................................................................75
7.5.
Bit Operation Instructions ......................................................................................................77
7.6.
Conditional Operation Instructions ........................................................................................78
7.7.
System control Instructions ...................................................................................................79
7.8.
Summary of Instructions Execution Cycle .............................................................................81
7.9.
Summary of affected flags by Instructions .............................................................................81
7.10.
BIT definition .........................................................................................................................81
8. Code Options ...................................................................................................................... 82
9. Special Notes ...................................................................................................................... 83
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PMS171B
8bit OTP MCU with 8-bit ADC
9.1.
Warning ................................................................................................................................83
9.2.
Using IC ................................................................................................................................83
9.2.1. IO pin usage and setting ............................................................................................83
9.2.2. Interrupt .....................................................................................................................84
9.2.3. System clock switching ..............................................................................................84
9.2.4. Watchdog ..................................................................................................................85
9.2.5. TIMER time out .........................................................................................................85
9.2.6. IHRC .........................................................................................................................85
9.2.7. LVR ...........................................................................................................................86
9.2.8. Programming Writing .................................................................................................86
9.3
Using ICE..............................................................................................................................87
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
Revision History:
Revision
Date
0.00
2018/10/11
Description
Preliminary version
1. Amend 1.1 Special Features
1.00
2018/11/07
2. Amend Fig. 4: Hardware diagram of comparator
3. Amend 9.2.8 Programming Writing
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
1. Features
1.1. Special Features
General purpose OTP series
Not supposed to use in AC RC step-down powered or high EFT requirement applications.
PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.
Operating temperature range: -20°C ~ 70°C
1.2. System Features
1.5KW OTP program memory
96 Bytes data RAM
Clock sources: internal high RC oscillator, internal low RC oscillator and external crystal oscillator
Band-gap circuit to provide 1.20V reference voltage
One hardware 16-bit timer
Two hardware 8-bit timers with PWM generation
One hardware comparator
Up to 11-channel 8-bit resolution ADC with one channel comes from band gap voltage
Provide ADC reference high voltage: external input, internal VDD
Eight levels of LVR reset by code option: 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V, 1.8V
Max. 14 IO pins with optional pull-high resistor, two of them with additional pull-low resistor
PB0 provides NMOS and PB7 provides PMOS super large current output (typ. 135mA@VDD=5.0V)
Two selectable external interrupt pins by code option
Every IO pin can be configured to enable wake-up function
For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast
1.3. CPU Features
One processing unit operating mode
82 powerful instructions
Most instructions are 1T execution cycle
Programmable stack pointer to provide adjustable stack level
Support direct and indirect addressing modes for data access. Data memories are available for use as an
index pointer of Indirect addressing mode
IO space and memory space are independent
1.4. Package Information
PMS171B-S16: SOP16 (150mil)
PMS171B-1J16A: QFN3*3-16pin (0.5pitch)
PMS171B-S14: SOP14 (150mil)
PMS171B-M10: MSOP10 (118mil)
PMS171B-S08: SOP8 (150mil)
PMS171B-U06: SOT23-6 (60mil)
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
2. General Description and Block Diagram
The PMS171B family is an ADC-Type, fully static, OTP-based CMOS 8-bit microcontroller. It employs RISC
architecture and all the instructions are executed in one cycle except that some instructions are two cycles that
handle indirect memory access.
1.5KW OTP program memory and 96 bytes data SRAM are inside, one up to 11 channels 8-bit ADC is built
inside the chip with one channel for internal band-gap reference voltage. PMS171B also provides three
hardware timers: one is 16-bit timer and two are 8-bit timers with PWM generation. PMS171B also supports one
hardware comparator and two super large current outputs.
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Page 9 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
3. Pin Definition and Functional Description
©Copyright 2018, PADAUK Technology Co. Ltd
Page 10 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
©Copyright 2018, PADAUK Technology Co. Ltd
Page 11 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 7 of port A. It can be configured as digital input, two-state output with pull-high
PA7 /
X1
IO
ST /
CMOS
resistor by software independently.
(2) X1 is Crystal XIN when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 7 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 7 of padier register is “0”.
The functions of this pin can be:
(1) Bit 6 of port A. It can be configured as digital input, two-state output with pull-high
PA6 /
X2
IO
ST /
CMOS
resistor by software independently.
(2) X2 is Crystal XOUT when crystal oscillator is used.
If this pin is used for crystal oscillator, bit 6 of padier register must be programmed “0”
to avoid leakage current. This pin can be used to wake-up system during sleep mode;
however, wake-up function is also disabled if bit 6 of padier register is “0”.
The functions of this pin can be:
PA5 /
IO (OD)
PRSTB
ST /
CMOS
(1) Bit 5 of port A. It can be configured as input or open-drain output pin.
(2) Hardware reset.
This pin can be used to wake-up system during sleep mode; however, wake-up
function is also disabled if bit 5 of padier register is “0”. Please put 33Ω resistor in
series to have high noise immunity when this pin is in input mode.
The functions of this pin can be:
(1) Bit 4 of port A. It can be configured as digital input, two-state output with pull-high
resistor by software independently.
(2) Channel 9 of ADC analog input.
PA4 /
AD9 /
CIN+ /
CIN1- /
INT1A
IO
ST /
CMOS /
Analog
(3) Plus input source of comparator.
(4) Minus input source 1 of comparator.
(5) External interrupt line 1A. It can be used as an external interrupt line 1. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
When this pin is configured as analog input, please use bit 4 of register padier to
disable the digital input to prevent current leakage. The bit 4 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 3 of port A. It can be configured as digital input, two-state output with pull-high
resistor independently by software.
PA3 /
IO
(2) Channel 8 of ADC analog input.
AD8 /
ST /
CIN0- /
CMOS /
(4) PWM output from Timer2.
TM2PWM
Analog
When this pin is configured as analog input, please use bit 3 of register padier to
(3) Minus input source 0 of comparator.
disable the digital input to prevent current leakage. The bit 3 of padier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 0 of port A. It can be configured as digital input, two-state output with pull-high
resistor independently by software.
PA0 /
IO
AD10 /
ST /
(2) Channel 10 of ADC analog input.
CO /
CMOS /
(4) External interrupt line 0. It can be used as an external interrupt line 0. Both rising
INT0
Analog
edge and falling edge are accepted to request interrupt service and configurable
(3) Output of comparator.
by register setting.
The bit 0 of padier register can be set to “0” to disable wake-up from power-down by
toggling this pin.
The functions of this pin can be:
(1) Bit 7 of port B. It can be configured as digital input, two-state output with pull-high
resistor independently by software.
PB7 /
IO
(2) Channel 7 of ADC analog input.
AD7 /
ST /
CIN5- /
CMOS /
(3) Minus input source 5 of comparator.
(4) PWM output from Timer3.
TM3PWM
Analog
When this pin is configured as analog input, please use bit 7 of register pbdier to
disable the digital input to prevent current leakage. The bit 7 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 6 of port B. It can be configured as digital input, two-state output with pull-high
/ pull-low resistor independently by software.
PB6 /
IO
AD6 /
ST /
CIN4- /
CMOS /
(4) PWM output from Timer3.
TM3PWM
Analog
When this pin is configured as analog input, please use bit 6 of register pbdier to
(2) Channel 6 of ADC analog input.
(3) Minus input source 4 of comparator.
disable the digital input to prevent current leakage. The bit 6 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 5 of port B. It can be configured as digital input, two-state output with pull-high
resistor independently by software.
(2) Channel 5 of ADC analog input.
PB5 /
IO
AD5 /
ST /
TM3PWM /
CMOS /
INT0A
Analog
(3) PWM output from Timer3.
(4) External interrupt line 0A. It can be used as an external interrupt line 0. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
When this pin is configured as analog input, please use bit 5 of register pbdier to
disable the digital input to prevent current leakage. The bit 5 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 4 of port B. It can be configured as digital input, two-state output with pull-high
PB4 /
AD4 /
TM2PWM
IO
ST /
CMOS /
Analog
resistor independently by software.
(2) Channel 4 of ADC analog input.
(3) PWM output from Timer2.
When this pin is configured as analog input, please use bit 4 of register pbdier to
disable the digital input to prevent current leakage. The bit 4 of pbdier register can be
set to “0” to disable digital input; wake-up from power-down by toggling this pin is also
disabled.
The functions of this pin can be:
(1) Bit 3 of port B. It can be configured as digital input, two-state output with pull-high
IO
/ pull-low resistor independently by software.
PB3 /
ST /
AD3
CMOS /
When this pin is configured as analog input, please use bit 3 of register pbdier to
Analog
disable the digital input to prevent current leakage. The bit 3 of pbdier register can
(2) Channel 3 of ADC analog input.
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 2 of port B. It can be configured as digital input, two-state output with pull-high
PB2 /
AD2 /
TM2PWM
IO
ST /
CMOS /
Analog
resistor independently by software.
(2) Channel 2 of ADC analog input.
(3) PWM output from Timer2.
When this pin is configured as analog input, please use bit 2 of register pbdier to
disable the digital input to prevent current leakage. The bit 2 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
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Page 14 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
Pin Name
Pin Type &
Description
Buffer Type
The functions of this pin can be:
(1) Bit 1 of port B. It can be configured as digital input, two-state output with pull-high
PB1 /
AD1 /
Vref
IO
ST /
CMOS /
Analog
resistor independently by software.
(2) Channel 1 of ADC analog input.
(3) External reference high voltage for ADC.
When this pin is configured as analog input, please use bit 1 of register pbdier to
disable the digital input to prevent current leakage. The bit 1 of pbdier register can
be set to “0” to disable digital input; wake-up from power-down by toggling this pin is
also disabled.
The functions of this pin can be:
(1) Bit 0 of port B. It can be configured as input or open-drain output pin.
PB0 /
IO (OD)
TM2PWM /
ST /
INT1
CMOS
(2) PWM output from Timer2.
(3) External interrupt line 1. It can be used as an external interrupt line 1. Both rising
edge and falling edge are accepted to request interrupt service and configurable
by register setting.
If bit 0 of pbdier register is set to “0” to disable digital input, wake-up from
power-down by toggling this pin is also disabled.
VDD: Digital positive power
VDD /
VDD /
AVDD: Analog positive power
AVDD
AVDD
VDD is the IC power supply while AVDD is the ADC power supply. AVDD and VDD
are double bonding internally and they have the same external pin.
GND: Digital negative power
GND /
GND /
AGND: Analog negative power
AGND
AGND
GND is the IC ground pin while AGND is the ADC ground pin. AGND and GND are
double bonding internally and they have the same external pin.
Notes: IO: Input/Output; ST: Schmitt Trigger input; OD: Open Drain; Analog: Analog input pin;
CMOS: CMOS voltage level
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PMS171B
8bit OTP MCU with 8-bit ADC
4. Device Characteristics
4.1. AC/DC Device Characteristics
All data are acquired under the conditions of VDD=5.0V, fSYS =2MHz unless noted.
Symbol
VDD
LVR%
fSYS
IOP
IPD
IPS
VIL
VIH
Description
Operating Voltage
Low Voltage Reset Tolerance
System clock (CLK)* =
IHRC/2
IHRC/4
IHRC/8
ILRC
Min
Typ.
Max
Unit
1.8*
-5
5.0
5.5
5
V
%
0
0
0
8M
4M
2M
Operating Current
Power Down Current
(by stopsys command)
Power Save Current
(by stopexe command)
Input low voltage for IO lines
Input high voltage for IO lines
Hz
50K
0.7
35
1
0.6
mA
uA
uA
uA
3
uA
0
0.1 VDD
0
0.2 VDD
0.8 VDD
VDD
0.7 VDD
VDD
V
V
o
Conditions (Ta=25 C)
* Subject to LVR tolerance
VDD ≧3.0V
VDD ≧2.2V
VDD ≧1.8V
VDD = 5.0V
fSYS=IHRC/16=1MIPS@5.0V
fSYS=ILRC=50KHz@3.3V
fSYS= 0Hz, VDD =5.0V
fSYS= 0Hz, VDD =3.3V
VDD =5.0V; fSYS= ILRC
Only ILRC module is enabled.
PA5
other IO
PA5
other IO
IO lines sink current
IOL
PB0
135
PB4, PB5 (normal)
16
PB4, PB5 (strong)
38
others
16
mA
VDD=5.0V, VOL=0.5V
mA
VDD=5.0V, VOH=4.5V
IO lines drive current
IOH
PA5, PB0
0
PB4, PB5 (normal)
6
PB4, PB5 (strong)
20
PB7
135
others
VIN
IINJ (PIN)
Input voltage
6
-0.3
Injected current on pin
VDD +0.3
V
1
mA
VDD =5.0V
100
RPH
RPL
Pull-high Resistance
KΩ
200
Pull-Low Resistance
Band-gap Reference Voltage
VDD =2.2V
100
VDD =5.0V
KΩ
200
©Copyright 2018, PADAUK Technology Co. Ltd
1.145*
VDD =3.3V
450
350
VBG
VDD +0.3≧VIN≧ -0.3
1.20*
Page 16 of 87
VDD =3.3V
VDD =2.2V
1.255*
V
VDD =1.8V ~ 5.5V
o
o
-20 C minus input
Select whether the comparator result output will be sampled by TM2_CLK?
5
0
R/W
0: result output NOT sampled by TM2_CLK
1: result output sampled by TM2_CLK
Inverse the polarity of result output of comparator.
4
0
R/W
0: polarity is NOT inversed.
1: polarity is inversed.
Selection the minus input (-) of comparator.
000 : PA3
001 : PA4
3-1
000
R/W
010 : Internal 1.20 volt band-gap reference voltage
011 : Vinternal R
100 : PB6 (not for EV5)
101 : PB7 (not for EV5)
11X: reserved
0
0
R/W
Selection the plus input (+) of comparator. 0/1: Vinternal R / PA4
©Copyright 2018, PADAUK Technology Co. Ltd
Page 64 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
6.21. Comparator Selection Register (gpcs), IO address = 0x19
Bit
Reset
R/W
Description
7
0
WO
6
0
WO
5
0
WO
Selection of high range of comparator.
4
0
WO
Selection of low range of comparator.
3-0
0000
WO
Comparator output enable (to PA0).
0 / 1 : Disable / Enable
GPC Wakeup enable.
0 / 1: Disable / Enable
Selection the voltage level of comparator.
0000 (lowest) ~ 1111 (highest)
6.22. Timer2 Control Register (tm2c), IO address = 0x1c
Bit
Reset
R/W
Description
Timer2 clock selection.
0000 : disable
0001 : CLK (system clock)
0010 : IHRC or IHRC *2 (by code option TMx_source)
0011 : EOSC
0100 : ILRC
0101 : comparator output
011x : reserved
7-4
0000
R/W
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does
NOT be stopped, Timer2 will keep counting when ICE is in halt state.
Timer2 output selection.
00 : disable
3-2
00
R/W
01 : PB2 or PB0 (by code option TM2 Output) (ICE doesn’t support PB0.)
10 : PA3
11 : PB4
1
0
R/W
0
0
R/W
Timer2 mode selection.
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer2 output.
0 / 1: disable / enable
6.23. Timer2 Counter Register (tm2ct), IO address = 0x1d
Bit
Reset
R/W
7-0
0x00
R/W
Description
Bit [7:0] of Timer2 counter register.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 65 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
6.24. Timer2 Scalar Register (tm2s), IO address = 0x1e
Bit
Reset
R/W
7
0
WO
Description
PWM resolution selection.
0 : 8-bit
1 : 6-bit or 7-bit (by code option TMx_bit)
Timer2 clock pre-scalar.
00 : ÷ 1
6-5
00
WO
01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4-0
00000
WO
Timer2 clock scalar.
6.25. Timer3 Control Register (tm3c), IO address = 0x32
Bit
Reset
R/W
Description
Timer3 clock selection.
0000 : disable
0001 : CLK (system clock)
0010 : IHRC or IHRC *2 (by code option TMx_source)
0011 : EOSC
0100 : ILRC
0101 : comparator output
7-4
0000
R/W
011x : reserved
1000 : PA0 (rising edge)
1001 : ~PA0 (falling edge)
1010 : PB0 (rising edge)
1011 : ~PB0 (falling edge)
1100 : PA4 (rising edge)
1101 : ~PA4 (falling edge)
Notice: In ICE mode and IHRC is selected for Timer3 clock, the clock sent to Timer3 does
NOT be stopped, Timer3 will keep counting when ICE is in halt state.
Timer3 output selection.
00 : disable
3-2
00
R/W
01 : PB5
10 : PB6
11 : PB7
1
0
R/W
0
0
R/W
Timer3 mode selection.
0 / 1 : period mode / PWM mode
Enable to inverse the polarity of Timer3 output.
0 / 1: disable / enable
6.26. Timer3 Counter Register (tm3ct), IO address = 0x33
Bit
Reset
R/W
7-0
0x00
R/W
Description
Bit [7:0] of Timer3 counter register.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 66 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
6.27. Timer3 Scalar Register (tm3s), IO address = 0x34
Bit
Reset
R/W
Description
PWM resolution selection.
7
0
WO
0 : 8-bit
1 : 6-bit or 7bit (by code option TMx_bit)
Timer3 clock pre-scalar.
00 : ÷ 1
6-5
00
WO
01 : ÷ 4
10 : ÷ 16
11 : ÷ 64
4-0
00000
WO
Timer3 clock scalar.
6.28. Timer3 Bound Register (tm3b), IO address = 0x3f
Bit
Reset
R/W
7-0
0x00
WO
Description
Timer3 bound register.
6.29. ADC Control Register (adcc), IO address = 0x3b
Bit
Reset
R/W
7
0
R/W
6
0
R/W
Description
Enable ADC function. 0/1: Disable/Enable.
ADC process control bit.
Read “1” to indicate the ADC is ready.
Channel selector. These four bits are used to select input signal for AD conversion.
0000: reserved,
0001: PB1,
0010: PB2,
0011: PB3,
0100: PB4,
5-2
0001
R/W
0101: PB5,
0110: PB6,
0111: PB7,
1000: PA3,
1001: PA4,
1010: PA0,
1111: (Channel F) Band-gap reference voltage 1.2V
Others: reserved
0-1
-
-
Reserved. (keep 0 for future compatibility)
©Copyright 2018, PADAUK Technology Co. Ltd
Page 67 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
6.30. ADC Mode Register (adcm), IO address = 0x3c
Bit
Reset
R/W
7-4
-
-
Description
Reserved (keep 0 for future compatibility)
ADC clock source selection.
000: CLK (system clock) ÷ 1,
001: CLK (system clock) ÷ 2,
010: CLK (system clock) ÷ 4,
3-1
000
R/W
011: CLK (system clock) ÷ 8,
100: CLK (system clock) ÷ 16,
101: CLK (system clock) ÷ 32,
110: CLK (system clock) ÷ 64,
111: CLK (system clock) ÷ 128,
0
-
-
Reserved
6.31. ADC Regulator Control Register (adcrgc), IO address = 0x3d
Bit
Reset
R/W
Description
ADC reference high voltage.
7
0
WO
0: VDD,
1: External PIN (PB1)
6-0
-
-
Reserved.
6.32. ADC Result High Register (adcr), IO address = 0x3e
Bit
Reset
R/W
7-0
-
RO
Description
These eight read-only bits will be the bit [7:0] of AD conversion result.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 68 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
7. Instructions
Symbol
ACC
a
sp
flag
Description
Accumulator (Abbreviation of accumulator)
Accumulator (symbol of accumulator in program)
Stack pointer
ACC status flag register
I
Immediate data
&
Logical AND
|
Logical OR
←
Movement
^
Exclusive logic OR
+
Add
－
Subtraction
〜
NOT (logical complement, 1’s complement)
〒
NEG (2’s complement)
OV
Overflow (The operational result is out of range in signed 2’s complement number system)
Z
Zero (If the result of ALU operation is zero, this bit is set to 1)
Carry (The operational result is to have carry out for addition or to borrow carry for subtraction in
C
unsigned number system)
Auxiliary Carry
AC
(If there is a carry out from low nibble after the result of ALU operation, this bit is set to 1)
pc0
Program counter for CPU
M.n
Only addressed in 0~0x3F (0~63) is allowed
©Copyright 2018, PADAUK Technology Co. Ltd
Page 69 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
7.1. Data Transfer Instructions
mov
a, I
mov
M, a
mov
a, M
mov
a, IO
mov
IO, a
ldt16
stt16
word
word
Move immediate data into ACC.
Example: mov
a, 0x0f;
Result:
a ← 0fh;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from ACC into memory
Example: mov
MEM, a;
Result:
MEM ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move data from memory into ACC
Example: mov
a, MEM ;
Result:
a ← MEM; Flag Z is set when MEM is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Move data from IO into ACC
Example: mov
a, pa ;
Result:
a ← pa; Flag Z is set when pa is zero.
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Move data from ACC into IO
Example: mov
pb, a;
Result:
pb ← a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move 16-bit counting values in Timer16 to memory in word.
Example: ldt16 word;
Result:
word ← 16-bit timer
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------word
T16val ;
// declare a RAM word
…
clear
lb@ T16val ;
// clear T16val (LSB)
clear
hb@ T16val ;
// clear T16val (MSB)
stt16
T16val ;
// initial T16 with 0
…
set1
t16m.5 ;
// enable Timer16
…
set0
t16m.5 ;
// disable Timer 16
ldt16
T16val ;
// save the T16 counting value to T16val
….
-----------------------------------------------------------------------------------------------------------------------Store 16-bit data from memory in word to Timer16.
Example: stt16 word;
Result:
16-bit timer ←word
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 70 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
idxm
Idxm
a, index
index, a
Application Example:
-----------------------------------------------------------------------------------------------------------------------word
T16val ;
// declare a RAM word
…
mov
a, 0x34 ;
mov
lb@ T16val , a ; // move 0x34 to T16val (LSB)
mov
a, 0x12 ;
mov
hb@ T16val , a ; // move 0x12 to T16val (MSB)
stt16
T16val ;
// initial T16 with 0x1234
…
---------------------------------------------------------------------------------------------------------------------Move data from specified memory to ACC by indirect method. It needs 2T to execute this
instruction.
Example: idxm a, index;
Result:
a ← [index], where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
----------------------------------------------------------------------------------------------------------------------word
RAMIndex ;
// declare a RAM pointer
…
mov
a, 0x5B ;
// assign pointer to an address (LSB)
mov
lb@RAMIndex, a ;
// save pointer to RAM (LSB)
mov
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
mov
hb@RAMIndex, a ; // save pointer to RAM (MSB)
…
idxm
a, RAMIndex ;
// move memory data in address 0x5B to ACC
-----------------------------------------------------------------------------------------------------------------------Move data from ACC to specified memory by indirect method. It needs 2T to execute this
instruction.
Example: idxm index, a;
Result:
[index] ← a; where index is declared by word.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------word
RAMIndex ;
// declare a RAM pointer
…
mov
a, 0x5B ;
// assign pointer to an address (LSB)
mov
lb@RAMIndex, a ;
// save pointer to RAM (LSB)
mov
a, 0x00 ;
// assign 0x00 to an address (MSB), should be 0
mov
hb@RAMIndex, a ; // save pointer to RAM (MSB)
…
mov
a, 0xA5 ;
idxm
RAMIndex, a ;
// move 0xA5 to memory in address 0x5B
------------------------------------------------------------------------------------------------------------------------
©Copyright 2018, PADAUK Technology Co. Ltd
Page 71 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
xch
M
pushaf
Exchange data between ACC and memory.
Example: xch MEM ;
Result:
MEM ← a , a ← MEM
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Move the ACC and flag register to memory that address specified in the stack pointer.
Example: pushaf;
Result:
[sp] ← {flag, ACC};
sp ← sp + 2 ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------.romadr 0x10 ;
// ISR entry address
pushaf ;
// put ACC and flag into stack memory
…
// ISR program
…
// ISR program
popaf ;
// restore ACC and flag from stack memory
reti ;
-----------------------------------------------------------------------------------------------------------------------Restore ACC and flag from the memory which address is specified in the stack pointer.
Example: popaf;
Result:
sp ← sp - 2 ;
{Flag, ACC} ← [sp] ;
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
popaf
7.2. Arithmetic Operation Instructions
add
a, I
add
a, M
add
M, a
addc
a, M
addc
M, a
Add immediate data with ACC, then put result into ACC.
Example: add
a, 0x0f ;
Result:
a ← a + 0fh
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into ACC.
Example: add
a, MEM ;
Result:
a ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC, then put result into memory.
Example: add
MEM, a;
Result:
MEM ← a + MEM
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into ACC.
Example: addc
a, MEM ;
Result:
a ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add data in memory with ACC and carry bit, then put result into memory.
Example: addc
MEM, a ;
Result:
MEM ← a + MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 72 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
addc
a
addc
M
sub
a, I
sub
a, M
sub
M, a
subc
a, M
subc
M, a
subc
a
subc
M
inc
dec
clear
M
M
M
Add carry with ACC, then put result into ACC.
Example: addc
a;
Result:
a←a+C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Add carry with memory, then put result into memory.
Example: addc
MEM ;
Result:
MEM ← MEM + C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction immediate data from ACC, then put result into ACC.
Example: sub
a, 0x0f;
Result:
a ← a - 0fh ( a + [2’s complement of 0fh] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction data in memory from ACC, then put result into ACC.
Example: sub
a, MEM ;
Result:
a ← a - MEM ( a + [2’s complement of M] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction data in ACC from memory, then put result into memory.
Example: sub
MEM, a;
Result:
MEM ← MEM - a ( MEM + [2’s complement of a] )
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction data in memory and carry from ACC, then put result into ACC.
Example: subc
a, MEM;
Result:
a ← a – MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction ACC and carry bit from memory, then put result into memory.
Example: subc
MEM, a ;
Result:
MEM ← MEM – a - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction carry from ACC, then put result into ACC.
Example: subc
a;
Result:
a←a-C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Subtraction carry from the content of memory, then put result into memory.
Example: subc
MEM;
Result:
MEM ← MEM - C
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Increment the content of memory.
Example: inc
MEM ;
Result:
MEM ← MEM + 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Decrement the content of memory.
Example: dec
MEM;
Result:
MEM ← MEM - 1
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Clear the content of memory.
Example: clear
MEM ;
Result:
MEM ← 0
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 73 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
7.3. Shift Operation Instructions
sr
a
src
sr
a
M
src
sl
slc
sl
slc
M
a
a
M
M
swap
a
Shift right of ACC, shift 0 to bit 7.
Example: sr
a;
Result:
a (0,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of ACC with carry bit 7 to flag.
Example: src a ;
Result:
a (c,b7,b6,b5,b4,b3,b2,b1) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right the content of memory, shift 0 to bit 7.
Example: sr MEM ;
Result:
MEM(0,b7,b6,b5,b4,b3,b2,b1) ← MEM(b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift right of memory with carry bit 7 to flag.
Example: src MEM ;
Result:
MEM(c,b7,b6,b5,b4,b3,b2,b1) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b0)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC shift 0 to bit 0.
Example: sl a ;
Result:
a (b6,b5,b4,b3,b2,b1,b0,0) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of ACC with carry bit 0 to flag.
Example: slc a ;
Result: a (b6,b5,b4,b3,b2,b1,b0,c) ← a (b7,b6,b5,b4,b3,b2,b1,b0), C ← a(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory, shift 0 to bit 0.
Example: sl MEM ;
Result:
MEM (b6,b5,b4,b3,b2,b1,b0,0) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM(b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Shift left of memory with carry bit 0 to flag.
Example: slc MEM ;
Result:
MEM (b6,b5,b4,b3,b2,b1,b0,C) ← MEM (b7,b6,b5,b4,b3,b2,b1,b0), C ← MEM (b7)
Affected flags: 『N』Z 『Y』C 『N』AC 『N』OV
Swap the high nibble and low nibble of ACC.
Example: swap
a;
Result:
a (b3,b2,b1,b0,b7,b6,b5,b4) ← a (b7,b6,b5,b4,b3,b2,b1,b0)
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 74 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
7.4. Logic Operation Instructions
and
a, I
and
a, M
and
M, a
or
a, I
or
a, M
or
M, a
xor
a, I
xor
IO, a
Perform logic AND on ACC and immediate data, then put result into ACC.
Example: and
a, 0x0f ;
Result:
a ← a & 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into ACC.
Example: and
a, RAM10 ;
Result:
a ← a & RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic AND on ACC and memory, then put result into memory.
Example: and
MEM, a ;
Result:
MEM ← a & MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and immediate data, then put result into ACC.
Example: or
a, 0x0f ;
Result:
a ← a | 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and memory, then put result into ACC.
Example: or
a, MEM ;
Result:
a ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic OR on ACC and memory, then put result into memory.
Example: or
MEM, a ;
Result:
MEM ← a | MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and immediate data, then put result into ACC.
Example: xor
a, 0x0f ;
Result:
a ← a ^ 0fh
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and IO register, then put result into IO register.
Example:
xor
a, M
xor
M, a
xor
pa, a ;
Result:
pa ← a ^ pa ; // pa is the data register of port A
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into ACC.
Example: xor
a, MEM ;
Result:
a ← a ^ RAM10
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Perform logic XOR on ACC and memory, then put result into memory.
Example:
xor
MEM, a ;
Result:
MEM ← a ^ MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 75 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
not
not
neg
neg
a
M
a
M
Perform 1’s complement (logical complement) of ACC.
Example: not
a;
Result:
a ← 〜a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
// ACC=0X38
not
a;
// ACC=0XC7
-----------------------------------------------------------------------------------------------------------------------Perform 1’s complement (logical complement) of memory.
Example: not
MEM ;
Result:
MEM ← 〜MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
mov
mem, a ;
// mem = 0x38
not
mem ;
// mem = 0xC7
-----------------------------------------------------------------------------------------------------------------------Perform 2’s complement of ACC.
Example: neg
a;
Result:
a ← 〒a
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
// ACC=0X38
neg
a;
// ACC=0XC8
-----------------------------------------------------------------------------------------------------------------------Perform 2’s complement of memory.
Example: neg
MEM;
Result:
MEM ← 〒MEM
Affected flags: 『Y』Z 『N』C 『N』AC 『N』OV
Application Example:
-----------------------------------------------------------------------------------------------------------------------mov
a, 0x38 ;
mov
mem, a ;
// mem = 0x38
not
mem ;
// mem = 0xC8
------------------------------------------------------------------------------------------------------------------------
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
7.5. Bit Operation Instructions
set0
IO.n
set1
IO.n
swapc
IO.n
Set bit n of IO port to low.
Example: set0 pa.5 ;
Result: set bit 5 of port A to low
Affected flags: 『N』Z 『N』C
Set bit n of IO port to high.
Example: set1 pb.5 ;
Result: set bit 5 of port B to high
Affected flags: 『N』Z 『N』C
『N』AC
『N』OV
『N』AC
『N』OV
Swap the nth bit of IO port with carry bit.
Example:
Result:
swapc
IO.0;
C ← IO.0 , IO.0 ← C
When IO.0 is a port to output pin, carry C will be sent to IO.0;
When IO.0 is a port from input pin, IO.0 will be sent to carry C;
Affected flags: 『N』Z
『Y』C
『N』AC
『N』OV
Application Example1 (serial output) :
set0
M.n
set1
M.n
-----------------------------------------------------------------------------------------------------------------------...
set1
pac.0 ;
// set PA.0 as output
...
set0
flag.1 ;
// C=0
swapc
pa.0 ;
// move C to PA.0 (bit operation), PA.0=0
set1
flag.1 ;
// C=1
swapc
pa.0 ;
// move C to PA.0 (bit operation), PA.0=1
...
-----------------------------------------------------------------------------------------------------------------------Application Example2 (serial input) :
-----------------------------------------------------------------------------------------------------------------------...
set0
pac.0 ;
// set PA.0 as input
...
swapc
pa.0 ;
// read PA.0 to C (bit operation)
src
a;
// shift C to bit 7 of ACC
swapc
pa.0 ;
// read PA.0 to C (bit operation)
src
a;
// shift new C to bit 7, old C
...
-----------------------------------------------------------------------------------------------------------------------Set bit n of memory to low.
Example: set0 MEM.5 ;
Result:
set bit 5 of MEM to low
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Set bit n of memory to high.
Example: set1 MEM.5 ;
Result:
set bit 5 of MEM to high
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 77 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
7.6. Conditional Operation Instructions
ceqsn
a, I
ceqsn
a, M
cneqsn
a, M
Compare ACC with immediate data and skip next instruction if both are equal.
Flag will be changed like as (a ← a – I)
Example: ceqsn
a, 0x55 ;
inc
MEM ;
goto
error ;
Result:
If a=0x55, then “goto error”; otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are equal.
Flag will be changed like as (a ← a - M)
Example: ceqsn
a, MEM;
Result:
If a=MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Compare ACC with memory and skip next instruction if both are not equal.
Flag will be changed like as (a ← a - M)
Example:
cneqsn
a, MEM;
Result:
If a≠MEM, skip next instruction
Affected flags: 『Y』Z 『Y』C 『Y』AC
cneqsn
a, I
『Y』OV
Compare ACC with immediate data and skip next instruction if both are no equal.
Flag will be changed like as (a ← a - I)
Example:
cneqsn
inc
goto
Result:
t0sn
IO.n
t1sn
IO.n
t0sn
M.n
t1sn
M.n
izsn
a
a,0x55 ;
MEM ;
error ;
If a≠0x55, then “goto error”; Otherwise, “inc MEM”.
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Check IO bit and skip next instruction if it’s low.
Example: t0sn
pa.5;
Result:
If bit 5 of port A is low, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check IO bit and skip next instruction if it’s high.
Example: t1sn
pa.5 ;
Result:
If bit 5 of port A is high, skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s low .
Example: t0sn MEM.5 ;
Result:
If bit 5 of MEM is low, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Check memory bit and skip next instruction if it’s high.
Example: t1sn MEM.5 ;
Result:
If bit 5 of MEM is high, then skip next instruction
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Increment ACC and skip next instruction if ACC is zero.
Example: izsn
a;
Result:
a ← a + 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 78 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
dzsn
a
izsn
M
dzsn
M
Decrement ACC and skip next instruction if ACC is zero.
Example: dzsn
a;
Result:
A ← A - 1,skip next instruction if a = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Increment memory and skip next instruction if memory is zero.
Example: izsn
MEM;
Result:
MEM ← MEM + 1, skip next instruction if MEM= 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
Decrement memory and skip next instruction if memory is zero.
Example: dzsn
MEM;
Result:
MEM ← MEM - 1, skip next instruction if MEM = 0
Affected flags: 『Y』Z 『Y』C 『Y』AC 『Y』OV
7.7. System control Instructions
call
label
goto
label
ret
ret
reti
nop
I
Function call, address can be full range address space.
Example: call
function1;
Result: [sp] ← pc + 1
pc ← function1
sp ← sp + 2
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Go to specific address which can be full range address space.
Example: goto
error;
Result:
Go to error and execute program.
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Place immediate data to ACC, then return.
Example: ret 0x55;
Result:
A ← 55h
ret ;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program which had function call.
Example: ret;
Result:
sp ← sp - 2
pc ← [sp]
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
Return to program that is interrupt service routine. After this command is executed, global
interrupt is enabled automatically.
Example: reti;
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
No operation.
Example: nop;
Result:
nothing changed
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
©Copyright 2018, PADAUK Technology Co. Ltd
Page 79 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
pcadd
engint
disgint
stopsys
stopexe
a
Next program counter is current program counter plus ACC.
Example: pcadd a;
Result:
pc ← pc + a
Affected flags: 『N』Z 『N』C 『N』AC 『N』OV
-----------------------------------------------------------------------------------------------------------------------Application Example:
-----------------------------------------------------------------------------------------------------------------------…
mov
a, 0x02 ;
pcadd
a;
// PC 33Ω resistor in between PA5 and the long wire
Avoid using PA5 as input in such application.
(6) PA7 and PA6 as external crystal oscillator
Configure PA7 and PA6 as input
Disable PA7 and PA6 internal pull-high resistor
Configure PADIER register to set PA6 and PA7 as analog input
EOSCR register bit [6:5] selects corresponding crystal oscillator frequency :
01 : for lower frequency, ex : 32KHz
10 : for middle frequency, ex : 455KHz,1MHz
11 : for higher frequency, ex : 4MHz
Program EOSCR.7 =1 to enable crystal oscillator
Ensure EOSC working well before switching from IHRC or ILRC to EOSC
©Copyright 2018, PADAUK Technology Co. Ltd
Page 83 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
Note: Please read the PMC-APN013 carefully. According to PMC-APN013, the crystal oscillator should be
used reasonably. If the following situations happen to cause IC start-up slowly or non-startup, PADAUK
Technology is not responsible for this: the quality of the user's crystal oscillator is not good, the usage
conditions are unreasonable, the PCB cleaner leakage current, or the PCB layouts are unreasonable.
9.2.2. Interrupt
(1) When using the interrupt function, the procedure should be:
Step1: Set INTEN register, enable the interrupt control bit
Step2: Clear INTRQ register
Step3: In the main program, using ENGINT to enable CPU interrupt function
Step4: Wait for interrupt. When interrupt occurs, enter to Interrupt Service Routine
Step5: After the Interrupt Service Routine being executed, return to the main program
*Use DISGINT in the main program to disable all interrupts
*When interrupt service routine starts, use PUSHAF instruction to save ALU and FLAG register.
POPAF instruction is to restore ALU and FLAG register before RETI as below:
void Interrupt (void)
// Once the interrupt occurs, jump to interrupt service routine
{
// enter DISGINT status automatically, no more interrupt is accepted
PUSHAF;
…
POPAF;
}
// RETI will be added automatically. After RETI being executed, ENGINT
status will be restored
(2) INTEN and INTRQ have no initial values. Please set required value before enabling interrupt function
(3) There are two sets of external IO pin interrupt source. Every set is decided by code option Interrupt Src0
and Interrupt Src1 corresponding to the unique interrupt pin. Please comply with the inten / intrq / integs
register when selecting IO pin.
9.2.3. System clock switching
(1) System clock can be switched by CLKMD register. Please notice that, NEVER switch the system clock and
turn off the original clock source at the same time. For example: When switching from clock A to clock B,
please switch to clock B first; and after that turn off the clock A oscillator through CLKMD.
Example : Switch system clock from ILRC to IHRC/2
CLKMD
=
CLKMD.2 =
0x36;
0;
// switch to IHRC, ILRC cannot be disabled here
// ILRC can be disabled at this time
ERROR: Switch ILRC to IHRC and turn off ILRC simultaneously
CLKMD
=
0x50;
// MCU will hang
(2) Please ensure the EOSC oscillation has established before switching from ILRC or IHRC to EOSC. MCU
will not check its status. Please wait for a while after enabling EOSC. System clock can be switched to
©Copyright 2018, PADAUK Technology Co. Ltd
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PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
EOSC afterwards. Otherwise, MCU will hang. The example for switching system clock from ILRC to 4MHz
EOSC after boot up as below:
.ADJUST_IC
DISABLE
CLKMD.1 = 0;
$
EOSCR
// turn off WDT for executing delay instruction
Enable, 4MHz;
// 4MHz EOSC start to oscillate
// Delay for EOSC establishment
$ T16M EOSC, /1, BIT10
Word Count = 0;
Stt16 Count;
Intrq.T16 = 0;
while(!Intrq.T16) NULL;
CLKMD
= 0xA4;
// ILRC -> EOSC;
CLKMD.2 = 0;
// turn off ILRC only if necessary
The delay duration should be adjusted in accordance with the characteristic of the crystal and PCB. To
measure the oscillator signal by the oscilloscope, please select (x10) on the probe and measure through
PA6(X2) pin to avoid the interference on the oscillator.
9.2.4. Watchdog
Watchdog will be inactive once ILRC is disabled.
9.2.5. TIMER time out
When select $ INTEGS
BIT_R (default value) and T16M counter BIT8 to generate interrupt, if T16M counts
from 0, the first interrupt will occur when the counter reaches to 0x100 (BIT8 from 0 to 1) and the second
interrupt will occur when the counter reaches 0x300 (BIT8 from 0 to 1). Therefore, selecting BIT8 as 1 to
generate interrupt means that the interrupt occurs every 512 counts. Please notice that if T16M counter is
restarted, the next interrupt will occur once Bit8 turns from 0 to 1.
If select $ INTEGS
BIT_F(BIT triggers from 1 to 0) and T16M counter BIT8 to generate interrupt, the T16M
counter changes to an interrupt every 0x200/0x400/0x600/. Please pay attention to two differences with
setting INTEGS methods.
9.2.6. IHRC
(1)
The IHRC frequency calibration is performed when IC is programmed by the writer.
(2)
Because the characteristic of the Epoxy Molding Compound (EMC) would some degrees affects the
IHRC frequency (either for package or COB), if the calibration is done before molding process, the
actual IHRC frequency after molding may be deviated or becomes out of spec. Normally, the frequency
is getting slower a bit.
(3)
It usually happens in COB package or Quick Turnover Programming (QTP). And PADAUK would not
take any responsibility for this situation.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 85 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
(4)
Users can make some compensatory adjustments according to their own experiences. For example,
users can set IHRC frequency to be 0.5% ~ 1% higher and aim to get better re-targeting after molding.
9.2.7. LVR
User can set MISC.2 as “1” to disable LVR. However, VDD must be kept as exceeding the lowest working
voltage of chip; Otherwise IC may work abnormally.
9.2.8. Programming Writing
There are 6 signals for programming PMS171B: PA3, PA4, PA5, PA6, VDD, and GND.
If using PDK3S-P-002 to program PMS171B, please put the jumper over CN39. For 16pin package, please
put the IC at the very top of the Textool. For 10pin package (such as MSOP10), please put the IC downwards
by three spaces. For 8pin package, please put the IC downwards by four spaces from the top of the Textool.
Other packages could be programmed by appropriate connection by the users. All the signals on the left side
pins of the jumper are identical and same as the labeled on CN42 at left bottom corner: they are VDD, PA0 (not
required), PA3, PA4, PA5, PA6, PA7 (not required), and GND.
If user use PDK5S-P-003 or above to program, please follow the instruction displayed at the software to
connect the jumper.
Special notes about voltage and current while Multi-Chip-Package(MCP) or On-Board Programming
(1)
PA5 (VPP) may be higher than 11V.
(2)
VDD may be higher than 6.5V, and its maximum current may reach about 20mA.
(3)
All other signal pins level (except GND) are the same as VDD.
User should confirm when using this product in MCP or On-Board Programming, the peripheral circuit or
components will not be destroyed or limit the above voltages.
©Copyright 2018, PADAUK Technology Co. Ltd
Page 86 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
PMS171B
8bit OTP MCU with 8-bit ADC
9.3 Using ICE
(1)
PDK5S-I-S01/2(B) supports PMS171B MCU emulation work, the following items should be noted
when using PDK5S-I-S01/2(B) to emulate PMS171B:
PDK5S-I-S01/2(B) doesn’t support SYSCLK=ILRC/16 of PMS171B.
PDK5S-I-S01/2(B) doesn’t support the function TM2C.PB0 of PMS171B.
PDK5S-I-S01/2(B) doesn’t support the code options: GPC_PWM, TMx_source, TMx_bit, TM2_Out1.
PDK5S-I-S01/2(B) doesn’t support the function PBPL (PB pull low)
The ICE’s GPCS wake up function is invalid. If comparator is enabled, CPU may be wake up whereas
CPU will be not wake definitely.
When using PB1 in ADCRGC, PA1 must float.
When using GPCC output, PA3 will be influenced.
Fast Wakeup time is different from ICE: 128 SysClk, PMS171B: 45 ILRC
Watch dog time out period is different from ICE:
WDT period
PDK5S-I-S01/2(B)
PMS171B
misc[1:0]=00
2048 * TILRC
8192 * TILRC
misc[1:0]=01
4096 * TILRC
16384 * TILRC
misc[1:0]=10
16384 * TILRC
65536 * TILRC
misc[1:0]=11
256 * TILRC
262144 * TILRC
Page 87 of 87
PDK-DS-PMS171B-EN_V100 – Nov. 7, 2018
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