PARADE TECHNOLOGIES INC.
Email: sales@paradetech.com
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PS176 DisplayPortTM-to-HDMI 2.0
Protocol Converter Datasheet
Version 0.6
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August. 21, 2014
Notice
All information provided in this document is on an “AS IS” basis without any guarantee or warranty.
Information in this document is provided in relation to Parade products and is subject to change without
notice. No intellectual rights or licenses are implied.
Do Not Distribute Without Permission
PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
KEY FEATURES
Compliant to DisplayPortTM Specification 1.2a for 1.62Gbps, 2.7Gbps and 5.4Gbps
Supports DisplayPortTM 1, 2, and 4 lanes
Supports full link training and no link training
Supports multiple color formats:
- DP: RGB 6/8/10/12-bit per component (bpc) and YCbCr4:4:4, YCbCr4:2:2 bpc 8/10/12 bpc
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- HDMI: RGB 8/10/12 bpc; YCbCr4:4:4, YCbCr4:2:2 and YCbCr4:2:0 8/10/12 bpc
Compliant to HDMI Specification 2.0, data rate up to 6Gbps
Supports TMDS scrambling for EMI/RFI reduction
Supports SCDC (Status and Control Data Channel)
Supports up to 8-channel LPCM, compressed audio (AC-3, DTS) and HBR audio formats
Supports up to 192kHz audio frame rate and up to 24-bit audio sample size
Content protection
- Supports HDCP 1.4 repeater with on-chip keys
- Supports HDCP 2.2 repeater
On-chip microprocessor with embedded SPI ROM
ESD:
1.2V Core Power Supply & 3.3V I/O Power Supply
0°C to 70°C Ambient Operating Temperature Range
48-pin 6x6mm QFN Halogen free RoHS package
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
APPLICATIONS
Dongle Application
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Typical Application
TMDS
Native DP
PS176
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Figure1. Typical Application
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
DESCRIPTION
PS176 is a DisplayPort 1.2a to HDMI 2.0 Protocol Converter which receives both video and audio streams
from DisplayPort link and converts to TMDS output. The TMDS transmitter is compliant to HDMI 2.0
specification with data rate up to 6Gbps.
PS176 supports HDCP 1.4 and HDCP 2.2 repeater for downstream sink with an embedded key.
PS176 has integrated an on-chip microcontroller for system configuration purposes. The device can be
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configured with an SPI Flash for customized applications.
The system level block diagram of PS176 is described in Figure 2. Detailed descriptions of each functional
block are given in the following sections.
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FUNCTIONAL BLOCK DIAGRAM
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Figure2. PS176 Functional Block Diagram
For Customer Internal Use Only
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Parade Technologies Inc.
PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
DISPLAYPORTTM RECEIVER
The DisplayPort™ Receiver interface implemented in PS176 is fully compliant to the VESA DisplayPort
Standard, Version 1.2a.
Physical Layer (PHY)
The DisplayPort™ main link operates at a data rate of 1.62Gbps (Reduced Bit Rate - RBR), 2.7Gbps (High
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Bit Rate - HBR) or 5.4Gbps (High Bit Rate 2 - HBR2). DisplayPort™ Receiver receives serial data stream,
de-serializes it, and decodes it in ANSI 8B/10B format. Subsequently, the receiver unscrambles and
de-skews the decoded data.
The DisplayPort™ AUX channel is a half-duplex, bi-directional channel which supports bit rate at 1 Mbps.
The logical sub-block of AUX channel generates and detects Start/Stop condition and locks to Sync
pattern, encodes or decodes of data using Manchester-II coding. The electrical sub-block of AUX channel
consists of one differential pair which operates as a half-duplex bi-directional channel. The AUX channel
provides Link Configuration, Link maintenance and EDID access.
The DisplayPort™ Hot Plug/Unplug detection is indicated by HPD signal. The HPD signal is asserted
whenever the sink device is connected to its main power supply and the source (DP Tx) is detected. The
pulsed HPD signal is also used as an Interrupt Request (IRQ) by sink device. The low-going pulse width
within 0.5ms to 1.0ms is asserted as Interrupt Request (IRQ) from sink device to source device which shall
read link status field of DisplayPort™ Configuration Data (DPCD) and take proper action.
Link Layer
The DisplayPort™ receiver Link Layer services reconstruct original video and audio data and timing base
through isochronous transport services over main link. It also handles AUX Channel link service and
device service. The main link supports 4-lane, 2-lane and 1-lane at 1.62Gbps, 2.7Gbps or 5.4Gbps data
rate. The optimal lane count and data rate shall be negotiated through capability discovery and link training
between source and sink devices. The isochronous transport services of Link Layer provide
packing/unpacking, stuffing/un-stuffing, framing/un-framing, inter-lane skewing/de-skewing, stream clock
recovery, insertion/extraction of Main Stream Attributes data and/or inserting/extracting of secondary-data
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packet with ECC (Error Control Code) for audio stream packet & CEA861-F InfoFrame packet.
PS176 DisplayPort™ receiver supports RGB444 (6/8/10/12-bit), YCbCr444 (8/10/12-bit) and YCbCr422
(8/10/12-bit) video input formats and supports up to 8 channels LPCM, compressed audio format (AC-3,
DTS) and HBR audio format. It also supports audio frame rate of 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz,
176.4kHz and 192kHz and audio sample size of 16, 20 and 24 bits per sample.
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
HDMI TRANSMITTER
The High Definition Multimedia Interface (HDMI) implemented in PS176 is fully compliant to the
High-Definition Multimedia Interface Specification, Version 2.0, September 4, 2013.
Compliance includes the capability to deliver audio and video content from the decoded DisplayPort™
audio and video streams onto an HDMI TMDS output. The HDMI TMDS provides support for up to
6.0Gbps data rate, allowing display up to 4kx2k at 60Hz refresh rate with 8-bit deep color and 3D video
formats up to 1080p at 120Hz. Audio output support consists of up to 8 channels of LPCM at 32kHz,
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44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz sample rate and audio sample size of 16, 20 and
24-bits per sample, decoded by DisplayPort™ receiver. The PS176 also supports compressed audio
formats (AC-3, DTS) and HBR audio format.
PS176 provides support for a SCDC channel for EDID reading and exchange of point-to-point dynamic
data between the Source and the Sink. PS176 also supports a monitor hot plug detect signal HPD to
detect the attachment and presence of a sink device.
HDCP
The HDCP provides a secure audio and video content on DisplayPort™ receiver and TMDS transmitter
interfaces, it also provides appropriate security measures to prevent discovery and nullification of the
HDCP keys stored within the PS176. PS176 supports both HDCP version 1.4 specification and HDCP
version 2.2 specification. The features of HDCP are summarized as below:
The DisplayPort™ receiver side performs upstream HDCP 1.4/2.2 function including HDCP
authentication and HDCP decryption.
The TMDS transmitter side performs downstream HDCP 1.4/2.2 function including HDCP
authentication and HDCP encryption.
Software will interface with both upstream and downstream HDCP authentication engine to
implement the HDCP repeater functions.
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Integrated both HDCP receiver and transmitter Key ROMs
HOT PLUG DETECTION (HPD)
PS176 has two hot plug detection signals.
HDMI_HPD: downstream port hot plug detection input
DP_HPD: upstream port hot plug detection output
HDMI_HPD
HDMI_HPD is an input signal. A HIGH on this signal indicates that a sink is connected. It is the hardware
that is responsible for detecting the state change on this pin. Firmware will interpret the signal and take
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Parade Technologies Inc.
PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
actions after the HDMI_HPD state change. HDMI_HPD state changes are mainly used in the PS176
operation and power state machine maintained by PS176 firmware.
DP_HPD
DP_HPD is an output signal. A HIGH on this signal indicates that PS176 is ready to take DisplayPort™
input. Firmware will control this signal according to PS176 operation and power state machine.
After power on, DP_HPD signal will stay at low. Once PS176 is ready to take DisplayPort™ input, this
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signal will be asserted HIGH.
In addition to hot plug detection, DP_HPD signal is also used for the following:
DisplayPort™ IRQ, including Link Status change, AUTOMATED_TEST_REQUEST and CP_IRQ.
In these events, hardware will generate short low-going pulse (0.5ms ~ 1ms) on DP_HPD pin
DisplayPort™ MCCS_IRQ and SINK_SPECIFIC_IRQ. Firmware will generate short low-going
pulse (0.5ms ~ 1ms) in the two events
AUX TO I2C BRIDGE
AUX to I2C bridge acts as a bidirectional repeater function from DisplayPort™ AUX CH interface to HDMI
DDC interface. It monitors DisplayPort™ AUX CH traffic and converts only those I2C-over-AUX CH
transactions targeted to the HDMI sink device, as described below, into HDMI DDC interface.
EDID access: I2C slave address of 60h, 61h, A0h and A1h
MCCS communication: I2C slave address of 6Eh and 6Fh
VESA DisplayID standard (proposed and legacy): I2C slave address of A0h through A7h
All other I2C-over-AUX transactions are blocked and assumed to be accessing functions within the PS176.
The AUX to I2C bridge provides an interface for PS176 firmware to interface AUX CH directly. This is to
provide hardware support for firmware to handle all possible native AUX transactions and I2C-over-AUX
transactions, including those targeted to the HDMI sink device.
The AUX to I2C bridge also provides an interface for PS176 to directly access HDMI DDC port. This
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function will be used when firmware needs to read EDID from downstream device, or to read downstream
HDCP port directly.
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
ON-CHIP MICROPROCESSOR (MPU)
PS176 integrates a micro-processor unit (MPU). The MPU core is an 8-bit processor which executes
8031/8051 type instructions. The instructions are stored in an internal flash ROM with Serial Peripheral
Interface (SPI) and can be accessed through the internal ROM bus. 512 bytes internal RAM and 128 bytes
SFR (special function register) provide the temporal data storage space. The MPU accesses the internal
registers through a memory bus.
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There is total 512K bytes SPI ROM space available for the MPU in PS176. PS176 firmware is stored in this
ROM. There are two ways to update the SPI ROM. One is through PS176 control I2C port and another one
is through AUX CH.
EDID
EDID Relay: EDID can be relayed from DDC bus in HDMI transmitter interface to AUX/DDC channel of
upstream Dual-Mode DP source. When relaying the EDID from HDMI to upstream DP source, PS176 does
not do any modifications.
GENERIC I/O INTERFACES
There are 4 dedicated General Purpose Input/Output pin (GPIO) in PS176.
CONTROL I2C SLAVE
Control I2C slave is the programming interface for external device to access internal registers, including
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DPCD registers. This bus is used to configure, control or debug PS176 internal functions.
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
DISPLAY RESOLUTIONS FOR TMDS OUTPUT
Following tables provide the popular video modes that PS176 may support. PS176 will also support other
video modes as long as they are within available DisplayPortTM bandwidth, TMDS clock frequency range of
25MHz to 340MHz (HDMI Specification 1.4b) and TMDS character rate (1/4 of TMDS clock frequency)
range of 85MHz to 150MHz (HDMI Specification 2.0).
Table 1. Video clock table for monitors
Refresh
Rate
Horizontal
Frequency
Pixel Frequency
Standard Type
Original Document
Date
640 x 350
85 Hz
37.9 kHz
31.500 MHz
VESA Standard
VDMTPROP
3/1/96
640 x 400
85 Hz
37.9 kHz
31.500 MHz
VESA Standard
VDMTPROP
3/1/96
720 x 400
85 Hz
37.9 kHz
35.500 MHz
VESA Standard
VDMTPROP
3/1/96
640 x 480
60 Hz
31.5 kHz
25.175 MHz
Industry Standard
n/a
n/a
72 Hz
37.9 kHz
31.500 MHz
VESA Standard
VS901101
12/2/92
75 Hz
37.5 kHz
31.500 MHz
VESA Standard
VDMT75HZ
10/4/93
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Resolution
800 x 600
85 Hz
43.3 kHz
36.000 MHz
VESA Standard
VDMTPROP
3/1/96
56 Hz
35.1 kHz
36.000 MHz
VESA Guidelines
VG900601
8/6/90
60 Hz
37.9 kHz
40.000 MHz
VESA Guidelines
VG900602
8/6/90
72 Hz
48.1 kHz
50.000 MHz
VESA Standard
VS900603A
8/6/90
75 Hz
46.9 kHz
49.500 MHz
VESA Standard
VDMT75HZ
10/4/93
85 Hz
53.7 kHz
56.250 MHz
VESA Standard
VDMTPROP
3/1/96
848 x 480
60 Hz
31.0 kHz
33.750 MHz
VESA Standard
AddDMT
3/4/03
1024 x 768
43 Hz
35.5 kHz
44.900 MHz
Industry Standard
n/a
n/a
60 Hz
48.4 kHz
65.000 MHz
VESA Guidelines
VG901101A
9/10/91
70 Hz
56.5 kHz
75.000 MHz
VESA Standard
VS910801-2
8/9/91
75 Hz
60.0 kHz
78.750 MHz
VESA Standard
VDMT75HZ
10/4/93
85 Hz
68.7 kHz
94.500 MHz
VESA Standard
VDMTPROP
3/1/96
1152 x 864
75 Hz
67.5 kHz
108.000 MHz
VESA Standard
VDMTPROP
3/1/96
1280 x 768
60 Hz
47.4 kHz
68.250 MHz
CVT Red. Blanking
AddDMT
3/4/03
60 Hz
47.8 kHz
79.500 MHz
CVT
AddDMT
3/4/03
75 Hz
60.3 kHz
102.250 MHz
CVT
AddDMT
3/4/03
Interlaced
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1280 x 960
1280 x 1024
85 Hz
68.6 kHz
117.500 MHz
CVT
AddDMT
3/4/03
60 Hz
60.0 kHz
108.000 MHz
VESA Standard
VDMTPROP
3/1/96
85 Hz
85.9 kHz
148.500 MHz
VESA Standard
VDMTPROP
3/1/96
60 Hz
64.0 kHz
108.000 MHz
VESA Standard
VDMTREV
12/18/96
10/4/93
75 Hz
80.0 kHz
135.000 MHz
VESA Standard
VDMT75HZ
85 Hz
91.1 kHz
157.500 MHz
VESA Standard
VDMTPROP
3/1/96
1360 x 768
60 Hz
47.7 kHz
85.500 MHz
VESA Standard
AddDMT
3/4/03
1400 x 1050
60 Hz
64.7 kHz
101.000 MHz
CVT Red. Blanking
AddDMT
5/13/03
60 Hz
65.3 kHz
121.750 MHz
CVT
AddDMT
3/4/03
75 Hz
82.3 kHz
156.000 MHz
CVT
AddDMT
3/4/03
85 Hz
85.0 kHz
179.500 MHz
CVT
AddDMT
3/4/03
1440 x 900
60 Hz
55.5 kHz
88.750 MHz
CVT Red. Blanking
CVT 1.30MA
7/14/04
60 Hz
59.9 kHz
106.500 MHz
CVT
CVT 1.30MA
7/14/04
75 Hz
75.0 kHz
136.750 MHz
CVT
CVT 1.30MA
7/14/04
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
1600 x 1200
84.8 kHz
157.000 MHz
CVT
CVT 1.30MA
7/14/04
60 Hz
75.0 kHz
162.000 MHz
VESA Standard
VDMTREV
12/18/96
65 Hz
81.3 kHz
175.500 MHz
VESA Standard
VDMTREV
12/18/96
70 Hz
87.5 kHz
189.000 MHz
VESA Standard
VDMTREV
12/18/96
75 Hz
93.8 kHz
202.500 MHz
VESA Standard
VDMTREV
12/18/96
85 Hz
106.3 kHz
229.500 MHz
VESA Standard
VDMTREV
12/18/96
60 Hz
64.7 kHz
119.000 MHz
CVT Red. Blanking
CVT 1.76MA
7/14/04
60 Hz
65.3 kHz
146.250 MHz
CVT
CVT 1.76MA
7/14/04
75 Hz
74.9 kHz
187.000 MHz
CVT
CVT 1.76MA
7/14/04
85 Hz
93.9 kHz
214.75 MHz
CVT
CVT 1.76MA
7/14/04
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1680 x 1050
85 Hz
1792 x 1344
60 Hz
83.64 kHz
1856 x 1392
60 Hz
86.33 kHz
1920 x 1200
60 Hz
74.0 kHz
60 Hz
74.6 kHz
75 Hz
60 Hz
1920 x 1440
204.750 MHz
VESA Standard
VDMTREV
9/17/98
218.250 MHz
VESA Standard
VDMTREV
9/17/98
154.000 MHz
CVT Red. Blanking
AddDMT
3/4/03
193.250 MHz
CVT
AddDMT
3/4/03
94.0 kHz
245.250 MHz
CVT
AddDMT
3/4/03
90.000 kHz
234.000 MHz
VESA Standard
VDMTREV
9/17/98
Table 2. Video clock table for TV devices
Field
Rate
Pa
Low
50Hz
VIC
Hactive
Vactive
I/P
Htotal
Hblank
Vtotal
Vblank
H Freq
(kHz)
V Freq
(Hz)
Pixel Freq
(MHz)
60,65
1280
720
Prog
3300
2020
750
30
18.000
24.000
59.400
61,66
1280
720
Prog
3960
2680
750
30
18.750
25.000
74.250
62,67
1280
720
Prog
3300
2020
750
30
22.500
30.000
74.250
32,72
1920
1080
Prog
2750
830
1125
45
27.000
24.000
74.250
33,73
1920
1080
Prog
2640
720
1125
45
28.125
25.000
74.250
34,74
1920
1080
Prog
2200
280
1125
45
33.750
30.000
74.250
79
1680
720
Prog
3300
1620
750
30
18.000
24.000
59.400
80
1680
720
Prog
3168
1488
750
30
18.750
25.000
59.400
81
1680
720
Prog
2640
960
750
30
22.500
30.000
59.400
86
2560
1080
Prog
3750
1190
1100
20
26.400
24.000
99.000
87
2560
1080
Prog
3200
640
1125
45
28.125
25.000
90.000
88
2560
1080
Prog
3520
960
1125
45
33.750
30.000
118.800
93,103
3840
2160
Prog
5500
1660
2250
90
54.000
24.000
297.000
94,104
3840
2160
Prog
5280
1440
2250
90
56.250
25.000
297.000
95,105
3840
2160
Prog
4400
560
2250
90
67.500
30.000
297.000
98
4096
2160
Prog
5500
1404
2250
90
54.000
24.000
297.000
99
4096
2160
Prog
5280
1184
2250
90
56.250
25.000
297.000
100
4096
2160
Prog
4400
304
2250
90
67.500
30.000
297.000
17,18
720
576
Prog
864
144
625
49
31.250
50.000
27.000
19,68
1280
720
Prog
1980
700
750
30
37.500
50.000
74.250
20
1920
1080
Int
2640
720
1125
22.51
28.125
50.000
74.250
21,22
1440
576
Int
1728
288
625
24.51
15.625
50.000
27.000
23,24
1440
288
Prog
1728
288
312
24
15.625
50.080
27.000
23,24
1440
288
Prog
1728
288
313
25
15.625
49.920
27.000
23,24
1440
288
Prog
1728
288
314
26
15.625
49.761
27.000
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
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2880
576
Int
3456
576
625
24.51
15.625
50.000
54.000
27,28
2880
288
Prog
3456
576
312
24
15.625
50.080
54.000
27,28
2880
288
Prog
3456
576
313
25
15.625
49.920
54.000
27,28
2880
288
Prog
3456
576
314
26
15.625
49.761
54.000
29,30
1440
576
Prog
1728
288
625
49
31.250
50.000
54.000
31,75
1920
1080
Prog
2640
720
1125
45
56.250
50.000
148.500
37,38
2880
576
Prog
3456
576
625
49
31.250
50.000
108.000
39
1920
1080
Int
2304
384
1250
85
31.250
50.000
72.000
82
1680
720
Prog
2200
520
750
30
37.500
50.000
82.500
89
2560
1080
Prog
3300
740
1125
45
56.250
50.000
185.625
96,106
3840
2160
Prog
5280
1440
2250
90
112.500
50.000
594.000
101
4096
2160
Prog
5280
1184
2250
90
112.500
50.000
594.000
1
640
480
Prog
800
160
525
45
31.469
59.9403
25.175
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25,26
60Hz
2,3
720
480
Prog
858
138
525
45
31.469
59.9403
27.000
4,69
1280
720
Prog
1650
370
750
30
45.000
60.0003
74.250
5
1920
1080
Int
2200
280
1125
22.51
33.750
60.0003
74.250
6,7
1440
480
Int
1716
276
525
22.51
15.734
59.9403
27.000
8,9
1440
240
Prog
1716
276
262
22
15.734
60.0543
27.000
8,9
1440
240
Prog
1716
276
263
23
15.734
59.8263
27.000
10,11
2880
480
Int
3432
552
525
22.51
15.734
59.9403
54.000
12,13
2880
240
Prog
3432
552
262
22
15.734
60.0543
54.000
12,13
2880
240
Prog
3432
552
263
23
15.734
59.8263
54.000
14,15
1440
480
Prog
1716
276
525
45
31.469
59.9403
54.000
16,76
1920
1080
Prog
2200
280
1125
45
67.500
60.0003
148.500
35,36
2880
480
Prog
3432
552
525
45
31.469
59.9403
108.000
83
1680
720
Prog
2200
520
750
30
45.000
60.0003
99.000
90
2560
1080
Prog
3000
440
1100
20
66.000
60.0003
198.000
97,107
3840
2160
Prog
4400
560
2250
90
135.000
60.0003
594.000
102
4096
2160
Prog
4400
304
2250
90
135.000
60.0003
594.000
(CEC-861-F, March 2013)
Table 3. 4K x 2K video formats
Pa
HDMI_VIC
0x01
Description
Pixel Freq
(MHz)
4K x 2K
297.000
29.97, 30Hz
296.703
Hactive
Hblank
3840
560
Vfreq (Hz)
Vactive
Vblank
30.000
2160
90
29.970
0x02
4K x 2K 25Hz
297.000
3840
1440
25.000
2160
90
0x03
4K x 2K
297.000
3840
1660
24.000
2160
90
23.98, 24Hz
296.703
4K x 2K 24Hz
297.000
2160
90
0x04
23.976
4096
1404
24.000
(SMPTE)
(HDMI Specification Version 1.4b, October 11, 2011)
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11
PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
Table 4. DisplayPort to HDMI 3D video formats mapping and list
DisplayPort 3D Video Formats
HDMI 3D Video Formats
Stacked Frame
Framing packing
Frame Sequential
Framing packing
Pixel Interleaved (Line interleave only)
Line alternative
Side-by-Side (Full mode)
Side-by-Side (Full)
VIC
Description
Hactive
Hblank
Vactive
Vact_space
Vblank
Pixel freq
(MHz)
V freq (Hz)
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3D Structure
0000
32
Frame Packing
1080p,
1920
830
1080
45
45
148.35/148.50
23.976/24.000
1280
370
720
30
30
148.35/148.50
59.940/60.000
23.98/24Hz
4
720p,
59.94/60Hz
0010
19
720p, 50Hz
1280
700
720
30
30
148.50
50.000
16
1080p
1920
280
1080
n.a.
45
297.00
60.000
31
1080p
1920
720
1080
n.a.
45
297.00
50.000
1920
280
1080
n.a.
45
297.00
60.000
1920
720
1080
n.a.
45
297.00
50.000
Line alternative
60Hz
50Hz
0011
16
Side-by-Side(Full)
1080p
60Hz
31
1080p
50Hz
(HDMI Specification Version 1.4b, October 11, 2011)
Note: All the supported 3D video formats in the mapping table can support all the timing data rates less than 3.0Gbps,
Pa
the timing list table only shows some examples.
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12
PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
POWER ON HARDWARE CONFIGURATION
The configuration mechanism is through configuration pin as shown in Table 5.
Table 5. Power On Configuration
Configuration Signal
I2C_ADDR
Purpose
Control I2C address selection
Definition
‘0’: 10h – 2Fh (default)
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‘1’: 90h – 9Fh, D0h – DFh
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
VDD12_ON
DRX0N
DRX0P
DP_HPD
DRX1N
DRX1P
VDDRX12
DRX2P
VDDRX12
DRX2N
DRX3P
VDD33
HDMID2P
HDMID2N
HDMI_HPD
HDMID1P
VDDTX12
HDMID1N
HDMID0P
VDDTX12
HDMID0N
HDMICKP
HDMICKN
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DRX3N
PIN ASSIGNMENT & DESCRIPTION
Pa
Figure3. PS176 PIN Assignment
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
Table 6. PS176 Pin Descriptions
Pin#
Pin Name
I/O Type
I/O Dir
Description
DRX0P
ANALOG
I
DP Main Link: DP_Lane0_p
39
41
DRX0N
DRX1P
ANALOG
ANALOG
I
I
DP Main Link: DP_Lane0_n
DP Main Link: DP_Lane1_p
42
DRX1N
ANALOG
I
DP Main Link: DP_Lane1_n
44
DRX2P
ANALOG
I
DP Main Link: DP_Lane2_p
45
DRX2N
ANALOG
I
DP Main Link: DP_Lane2_n
47
48
DRX3P
DRX3N
ANALOG
ANALOG
I
I
DP Main Link: DP_Lane3_p
DP Main Link: DP_Lane3_n
34
AUXP
ANALOG
I/O
DP AUX_p
33
AUXN
ANALOG
I/O
DP AUX_n
40
DP_HPD
ANALOG
O
DP RX Hot Plug Detect
14
HDMICKP
ANALOG
O
HDMI Tx clock channel positive
13
HDMICKN
ANALOG
O
HDMI Tx clock channel negative
17
16
20
19
HDMID0P
HDMID0N
HDMID1P
HDMID1N
ANALOG
ANALOG
ANALOG
ANALOG
O
O
O
O
HDMI Tx data channel 0 positive
HDMI Tx data channel 0 negative
HDMI Tx data channel 1 positive
HDMI Tx data channel 1 negative
23
HDMID2P
ANALOG
O
HDMI Tx data channel 2 positive
22
7
HDMID2N
DDC_SCL
ANALOG
Schmitt, OD
O
I/O
HDMI Tx data channel 2 negative
HDMI DDC CLK
8
DDC_SDA
Schmitt, OD
I/O
HDMI DDC DATA
21
HDMI_HPD
LVTTL
I
9
HDMI_CEC
ANALOG
I/O
36
REXT
ANALOG
I
Connection to external resistor.
35
RESETB
Schmitt
I
Reset; ACTIVE LOW
4
PDB
Schmitt
I
Power down; ACTIVE LOW
2
37
TESTMODEB
VDD12_ON
Schmitt
DIG
I
O
Test mode control, NC for normal operation
Signal to active 1.2V power supply; Active High
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38
HDMI Hot Plug Detect
HDMI CEC (Optional)
Internal pull-up at 27kΩ
29
CSCL
Schmitt, OD
I/O
Control I2C slave clock for debugging use
28
CSDA
Schmitt, OD
I/O
Control I2C slave data for debugging use
XTLI
ANALOG
I
Crystal oscillator clock input;
25
XTLO
ANALOG
O
Crystal oscillator clock output;
Pa
26
I2C slave address selection
Internal pull-down at ~80kΩ
General Purpose I/O
Internal pull-up at ~80kΩ
General Purpose I/O
Internal pull-up at ~80kΩ
General Purpose I/O
Internal pull-up at ~80kΩ
General Purpose I/O
Internal pull-down at ~80kΩ
3
I2C_ADDR
LVTTL
I/O
5
GPIO1
LVTTL
I/O
27
GPIO2
LVTTL
I/O
10
GPIO3
LVTTL
I/O
12
GPIO4
LVTTL
I/O
31
AUXDCN
ANALOG
I
DP source detection
32
AUXDCP
ANALOG
I
DP source detection
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
VDD33
VDD33
VDDRX12
VDDRX12
VDDA12
VDD12
VDD12
PWR
PWR
PWR
PWR
PWR
PWR
PWR
3.3V VDD Power Supply
3.3V VDD Power Supply
1.2V VDD for DP receiver
1.2V VDD for DP receiver
1.2V VDD for analog
1.2V VDD for digital logic
1.2V VDD for digital logic
15
VDDTX12
PWR
1.2V VDD for HDMI transmitter
18
VDDTX12
EPAD
PWR
1.2V VDD for HDMI transmitter
Ground
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1
24
43
46
11
6
30
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
ABSOLUTE MAXIMUM RATINGS
Parameters
Comments
Min
Typ
Max
Unit
Supply Voltage Range:
-0.5
4
V
VDDRX12, VDDA12, VDD12, VDDTX12
-0.5
1.45
V
Normal I/O Voltage Range
-0.5
4
V
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VDD33
TJ
Junction temperature
TS
Storage temperature
ESD
-40
125
°C
150
°C
Human Body Model
V
Machine Model
V
Charged Device Model
V
ESD Standard:
Human Body Mode: JESD22-A114-D
Machine Mode: JESD22-A115-A
Charged Device Mode: JESD22-C101-A
Pa
Latch-up Standard: JESD78; I-Test: +/- 200 mA; V-Test: 1.5X of Vcc
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
NORMAL OPERATING CONDITIONS
Parameter
Min
Typ
Max
Unit
VDD33
3.0
3.3
3.6
V
VDDRX12, VDDA12, VDD12, VDDTX12
1.14
1.2
1.26
V
Supply Voltage:
Operation Temperature:
0
70
°C
Tc - Case Temperature
0
85
°C
Pa
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Ta - Ambient Temperature
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
POWER CONSUMPTIONS
Parameter
Conditions
DP input 4lane/5.4Gbps, HDMI output 5.94Gbps
Typ
Max
Unit
Tested at
VDD33 = 3.3V
1.2V Normal Supply Current, IDD
Min
432.2
mA
18.5
mA
16.8
mA
16
mA
1.2V Normal Supply Current, IDD
0
uA
3.3V Normal Supply Current, IDD
70
uA
1.2V Normal Supply Current, IDD
0
uA
3.3V Normal Supply Current, IDD
30
uA
579.7
mW
73
mW
0.23
mW
0.1
mW
VDDRX12 = 1.2V
3.3V Normal Supply Current, IDD
VDDA12 =1.2V
Standby when DPCD600h = 02h
VDD12=1.2V
1.2V Normal Supply Current, IDD
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VDDTX12=1.2V
3.3V Normal Supply Current, IDD
Auto Power Down
Power down when PDB pin is asserted
DP input 4lane/5.4Gbps, HDMI output 5.94Gbps
Power consumption
Standby when DPCD600h = 02h
Power consumption
Auto Power Down
Power consumption
Power down when PDB pin is asserted
Pa
Power consumption
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19
PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
PACKAGE DISSIPATION RATINGS
48-pin QFN
Still air, 4-layer PCB
28.5 C/W
θJC - Junction to Case Thermal Resistance
12.1 C/W
Maximum Power Dissipation Rating, Ta = 70 °C
1930 mW
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θJA - Junction to Ambient Thermal Resistance
I/O DC CHARACTERISTICS
Parameter
Test Conditions
Min
Typ
Max
Unit
I2C pins:
CSCL/CSDA
VOH
High-level output voltage
External 1.5 kΩ pull-up to
VOL
Low-level output voltage
VDD33, IOL = 8 mA
VDD33
V
0.4
V
Control input pin: RESETB, PDB
VIH
Input High-level voltage
VIL
Input Low-level voltage
0.7VDD33
V
0.25VDD33
V
Status I/O pins: GPIOx (x= 1~4)
High-level output voltage
VOL
Low-level output voltage
0.8VDD33
V
0.15VDD33
V
Pa
VOH
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
I/O AC CHARACTERISTICS
Parameter
Test Conditions
Min
Typ2
Max
Unit
+10
ms
+10
ms
+10
ms
6
ns
6
ns
1.0
ms
Supply ramp up time:
(both supplies ramp at the same starting point)
t3.3
3.3V supply ramp up time
10% to 90% of the 3.3V
supply voltage
10% to 90% of the 1.2V
1.2V supply ramp up time
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t1.2
supply voltage
dt
VDD33 and VDD12 power ramp up separation
Time difference between
-10
the mid points of VDD33
and VDD12
Status output pins: GPIOx (x=1~4)
tr
Output rise time
tf
Output fall time
CL = 10 pF
Hot plug detection pin: DP_HPD
0.5
Pa
IRQ HPD pulse width (driven by sink device)
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
Fo ra
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POWER UP AND RESET TIMING SEQUENCE
Figure 4. Power Up and Reset Timing Sequence
Pa
Note: The de-assertion of the RESETB shall follow by the timing sequence as given in the above diagram.
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22
PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
DISPLAYPORT™ AUX CHANNEL CHARACTERISTICS
Symbol and Parameter
UI:
Test Conditions
Unit Interval for AUX channel
VAUX-DIFF-p-p: AUX differential peak-to-peak voltage at TP1
Min
Typ
Max
Unit
0.4
0.5
0.6
µs
400
900
mV
320
1360
mV
20
mA
200
nF
When AUX CH is driving the bus
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VAUX-DIFF-p-p: AUX differential peak-to-peak voltage at TP2
When AUX CH is receiving the bus
AUX channel short circuit current
CAUX:
AUX AC coupling capacitor
75
Pa
IAUX-SHORT:
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PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
DISPLAYPORT™ MAIN LINK RECEIVER CHARACTERISTICS
Symbol and Parameter
Test Conditions
Min
Spread spectrum clock, down-spreading by SOURCE
Modulation Frequency
VRX-DIFFp-p: Differential peak-to-peak input voltage at package pins
Typ
Max
0.5
Unit
%
30
33
kHz
100
1360
mV
9
dB
GND
V
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Maximum adaptive RX equalization level at 1.35GHz
VRX_DC_CM: RX input DC common mode voltage
RRX-DIFF:
Differential termination resistance
80
100
120
Ω
RRX-SE:
Single-ended termination resistance
40
50
60
Ω
IRX_SHORT:
Rx short circuit current limit
20
mA
50
ps
150
ps
300
ps
LRX_SKEW_INTRA_PAIR: Intra-pair skew at Rx package pins (HBR2)
RX intra-pair skew tolerance at HBR2
LRX_SKEW_INTRA_PAIR: Intra-pair skew at Rx package pins (HBR)
RX intra-pair skew tolerance at HBR
LRX_SKEW_INTRA_PAIR: Intra-pair skew at Rx package pins (RBR)
RX intra-pair skew tolerance at RBR
Receiver Jitter Tolerance for High Bit Rate 2 (HBR2)
Total jitter tolerance at 2MHz
1026
mUI
Total jitter tolerance at 10MHz
636
mUI
Total jitter tolerance at 20MHz
624
mUI
Total jitter tolerance at 100MHz
620
mUI
Total jitter tolerance at 2MHz
1227
mUI
Total jitter tolerance at 10MHz
548
mUI
Total jitter tolerance at 20MHz
505
mUI
Total jitter tolerance at 100MHz
491
mUI
Total jitter tolerance at 2MHz
1648
mUI
Total jitter tolerance at 10MHz
778
mUI
Total jitter tolerance at 20MHz
747
mUI
Pa
Receiver Jitter Tolerance for High Bit Rate (HBR)
Receiver Jitter Tolerance for Reduced Bit Rate (RBR)
Note: Jitter Tolerance Testing follows VESA DisplayPort™ PHY
Compliance Testing Specification, Version 1.2b.
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24
PS176 DisplayPortTM-to-HDMI 2.0 Protocol Converter
Parade Technologies Inc.
HDMI TRANSMITTER CHARACTERISTICS
Symbol and Parameter
Test Conditions
Min
Typ
Max
Unit
AVcc = 3.3V, RT = 50 Ω
800
1000
1200
mV
AVcc+10
mV
1.65GHz
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