FEMDNN008G-08A39

ys s g n al i t en d i nf o C Rev. 1.1 FEMDNN008G-08A39 FORESEE eMMC Lo FEMDNN008G-08A39 Datasheet ys s g n E-00692 Version: 1.1 gs n o L 2020.03.03 LONGSYS ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. al i t den nfi o C Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an “AS IS” basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Longsys Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other-wise. y s g n s Lo Longsys products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. al i t en fid n Co nfi o C For updates or additional information about Longsys products, contact your nearest Longsys office. All brand names, trademarks and registered trademarks belong to their respective owners. y s g n s Lo ⓒ 2020 Shenzhen Longsys Electronics Co., Ltd. All rights reserved. www.longsys.com ti n e d al i t den i f n Co Longsys Electronics a Revision History: al i t en d i nf o C Rev. 1.1 FEMDNN008G-08A39 Rev. Date Changes Remark 1.0 2019/12/12 Basic spec and architecture Preliminary 1.1 n Lo g s sy2020/03/03 Content modification gs n o L al i t den nfi o C y s g n s Lo al i t en fid n Co ti n e d nfi o C ys s g n y s g n s Lo www.longsys.com al i t den i f n Co Longsys Electronics a ys s g n al i t en d i nf o C CONTENTS Rev. 1.1 FEMDNN008G-08A39 1. Introduction .................................................................................................. 1 2. Product List ................................................................................................... 1 ys s g n .......................................................................................................1 3. Features Lo 4. Functional Description..................................................................................... 2 5. Product Specifications ..................................................................................... 3 5.1 Performance ............................................................................................. 3 5.2 Power Consumption ................................................................................... 3 6. Pin Assignments ............................................................................................. 4 6.1 Ball Array view .......................................................................................... 4 6.2 Ball Array view .......................................................................................... 5 7. Usage Overview ............................................................................................. 6 gs n o L 7.1 General description .................................................................................... 6 7.2 Partition Management ................................................................................ 6 al i t 7.3 Automatic Sleep Mode ................................................................................ 8 den i f n 7.4 Sleep (CMD5)............................................................................................ 8 Co 7.5 H/W Reset operation .................................................................................. 9 7.6 High-speed mode selection ......................................................................... 9 ys s g 7.7 Bus width selection .................................................................................... 9 n Lo 7.8 Partition configuration ................................................................................ 9 7.9 CID register .............................................................................................. 9 al i t en d i f 7.11 Extended n CSD register ........................................................................... 11 o ia C t n 7.12 OCR Register ......................................................................................... 22 de i f n 7.13 Field firmware update(FFU) ..................................................................... 22 Co 7.10 CSD register ......................................................................................... 10 7.14 S.M.A.R.T. Health Report ........................................................................ 24 8. Package Dimension ...................................................................................... 25 ys s g 9 Connection Guide .......................................................................................... 25 n Lo 9.1 Schematic Diagram .................................................................................. 25 10. Processing Guide ........................................................................................ 26 www.longsys.com al i t den i f n Co Longsys Electronics 1. Introduction al i t en d i nf o C Rev. 1.1 FEMDNN008G-08A39 FORESEE eMMC is an embedded storage solution designed in the BGA package. The FORESEE eMMC consists of NAND flash and eMMC controller. The controller could manage the interface protocols， ys s g FORESEE on eMMC has high performance at a competitive cost, high quality and low power consumption, and L eMMC is compatible with JEDEC standard eMMC 5.1 specifications. wear-leveling，bad block management and ECC. 2. Product List Density Part Number 8GB FEMDNN008G-08A39 Capacity Package Package (User Density) Size(mm) Type 7.2GB 11.5x13x1.0 153FBGA 3. Features  eMMC5.1 specification compatibility (Backward compatible to eMMC4.41/4.5/5.0)     Global-wear-leveling  Supported features. Bus mode HS400, HS200 - Data bus width: 1 bit (default), 4 bits, 8 bits - Partitioning, RPMB - Data transfer rate: up to 400MB/s (HS400) - Boot feature, boot partition - MMC I/F Clock frequency : 0~200MHz - HW Reset/SW Reset - Discard, Trim, Erase, Sanitize Operating voltage range - FFU - Sleep / awake - - Vccq(Controller) : 1.7 - 1.95V / 2.7 - 3.6V - Temperature - Storage without operation (-40℃ ~ +85℃)  Sudden-Power-Loss safeguard  Hardware ECC engine sys g on Unique firmware backup mechanism L  L al i t Background operations, en HPI d i f Enhanced reliable n write o S.M.A.R.T.C Health Report - Vcc(NAND) : 2.7 - 3.6V - Operation (-25℃ ~ +85℃)  gs n o - Others - Compliance with the RoHS Directive al i t en fid n Co ti n e d nfi o C ys s g n y s g n s Lo www.longsys.com al i t den i f n Co Page 1 Longsys Electronics a al i t Rev. 1.1 n e FEMDNN008G-08A39 d fi n o 4. Functional Description C FORESEE eMMC with powerful L2P (Logical to Physical) NAND Flash management algorithm provides unique functions:  Host independence from details of operating NAND flash  Internal ECC to correct defect in NAND flash  y n gs s LoSudden-Power-Loss safeguard To prevent from data loss, a mechanism named Sudden-Power-Loss safeguard is added in the eMMC. In the case of sudden power-failure, the eMMC would work properly after power cycling.  Global-wear-leveling To achieve the best stability and device endurance, this eMMC equips the Global Wear Leveling algorithm. It ensures that not only normal area, but also the frequently accessed area, such as FAT, would be programmed and erased evenly.  IDA(Initial Data Acceleration) The eMMC prevents the pre-burned data from data-loss with IDA, in case of our customer had pre-burned data to eMMC, before the eMMC being SMT.  gs n o Cache The eMMC enhanced the data written performance with Cache, with which our customer would get L more endurance and reliability. al i t den nfi o C y s g n s Lo al i t en fid n Co ti n e d nfi o C ys s g n y s g n s Lo www.longsys.com al i t den i f n Co Page 2 Longsys Electronics a al i t en d i nf o 5. Product Specifications C 5.1 Performance Rev. 1.1 FEMDNN008G-08A39 Density Write Read 8GB Up to 120MB/s Up to 160MB/s s y s • Test Condition: Bus width x8, 200MHz DDR, 512KB data transfer, w/o file system overhead, measured on ng o L board internal • Test tool: uBOOT (Without O/S) • Chunk size: 1MB, • Test area: 100MB/ Full-range of LBA. 5.2 Power Consumption 5.2.1 Active power consumption during operation Density Icc Iccq 8GB 130mA 150mA • Power Measurement conditions: Bus configuration =x8 @200MHz DDR, 25℃. gs n o • Vcc:3.3V & Vccq：1.8V. L • The measurement for max RMS current is the average RMS current consumption over a period of 100ms. 5.2.2 Low power mode (stand-by) Density Icc Iccq 8GB 30uA 160uA nfi o C • Power Measurement conditions: Bus configuration =x8 @200MHz DDR, 25℃. • Standby: Nand Vcc & Controller Vccq power supply is switched on. al i t den • The measurement for max RMS current is the average RMS current consumption over a period of 100ms. y s g Icc n 5.2.3 Low power mode (sleep) Density 8GB Lo s 0 Iccq 160uA • Power Measurement conditions: Bus configuration =x8 @200MHz DDR, 25℃. • Sleep: Nand Vcc power supply is switched off(Controller Vccq on) al i t en fid • The measurement for max RMS current is the average RMS current consumption over a period of 100ms. n Co ti n e d nfi o C ys s g n y s g n s Lo www.longsys.com al i t den i f n Co Page 3 Longsys Electronics a 6. Pin Assignments 6.1 Ball Array view Lo y n gs al i t en d i nf o C Rev. 1.1 FEMDNN008G-08A39 s gs n o L al i t den nfi o C FBGA153 - Ball Array (Top View through package) y s g n s Lo al i t en fid n Co ti n e d nfi o C ys s g n y s g n s Lo www.longsys.com al i t den i f n Co Page 4 Longsys Electronics a 6.2 Ball Array view Signal CLOCK ys s g n (CLK) Lo al i t en d i nf o C Rev. 1.1 FEMDNN008G-08A39 Description Each cycle of the clock directs a transfer on the command line and on the data lines. This signal is a bidirectional command channel used for device initialization and command transfer. COMMAND The CMD Signal has 2 operation modes: open drain, for initialization, and (CMD) push-pull, for command transfer. Commands are sent from the host to the device, and responses are sent from the device to the host. These are bidirectional data signal. The DAT signals operate in push-pull mode. By default, after power-up or RESET, only DAT0 is used for data transfer. The controller can configure a wider data bus for data transfer wither using DAT DATA (DAT0-DAT7) [3:0](4bit mode)or DAT[7:0](8bit mode). Includes internal pull-up resistors for data lines DAT[7:1].Immediately after gs n o entering the 4-bit mode, the device disconnects the internal pull-up resistors on the DAT1 and DAT2 lines.(The DAT3 line internal pull-up is left connected.)Upon L entering the 8bit mode, the device disconnects the internal pull-up on the DAT1, DAT2, and DAT[7:4]lines. Data Strobe (DS) RESET (RSTN) Vccq Vcc VDDi Newly assigned pin for HS400 mode. Data Strobe is generated from e.MMC to al i t n Data Strobe. In HS400 mode, read data and CRC response are synchronized dewith i f n Co Hardware Reset Input host. Vccq is the power supply line for host interface, have two power mode: High power s mode:2.7V~3.6V; Lower power mode:1.7V~1.95V y s g n Vcc is the power supply line for internal flash memory, its power voltage range is:2.7V~3.6V Lo VDDi is internal power node, not the power supply. Connect 1uF capacitor VDDi to ground al i t Note: en d i f NC: No Connect, n shall be connected to ground or left floating. o C for Future Use, must be left floating for future use. RFU: Reserved Vss,Vssq Ground lines. ti n e d nfi o C VSF: Vendor Specific Function, must be left floating. ys s g n y s g n s Lo www.longsys.com al i t den i f n Co Page 5 Longsys Electronics a ys s g n al i t en d i nf 7. Usage Overview Co 7.1 General description Rev. 1.1 FEMDNN008G-08A39 The eMMC can be operated in 1, 4, or 8-bit mode. NAND flash memory is managed by a controller inside, which manages ECC, wear leveling and bad block management. The eMMC provides easy integration with y n gs s the host process that all flash management hassles are invisible to the host. Lo gs n o L al i t n local memory The embedded device offers also the possibility of configuring by the host additional desplit i f n partitions with independent addressable space starting from logical addresso0x00000000 for different C 7.2 Partition Management usage models. Default size of each Boot Area Partition is 4096 KB and can be changed by Vendor Command as multiple of 128KB. Boot area partition size is calculated as ( 128KB * BOOT_SIZE_MULTI ) The size of Boot Area Partition 1 and 2 cannot be set independently and is set as same value Boot area partition which s  y s g Factory configuration supplies boot partitions. on L The RPMB partition is 4MB.  The host is free to configure one segment in the User Data Area to be implemented as enhanced is enhanced partition. Therefore memory block area scan is classified as follows:  storage media, and to specify its starting location and size in terms of Write Protect Groups. The al i t (one-time programmable). den i f onGeneral Purpose Area Partitions can be configured to store user data or sensitive data, or Up to four C for other host usage models. The size of these partitions is a multiple of the write protect group. Size attributes of this Enhanced User Data Area can be programmed only once during the device life-cycle  nfi o C and attributes can be programmed once in device life-cycle (one-time programmable). Each of the General Purpose Area Partitions can be implemented with enhanced technological features. y s g n s Lo www.longsys.com al i t den i f n Co Page 6 Longsys Electronics ti n e d a al i t en d i nf o C Lo y n gs Rev. 1.1 FEMDNN008G-08A39 s Partitions and user data area configuration (The size of RPMB area partition is 4MB) In boot operation mode, the master can read boot data from the slave (device) by keeping CMD line low or gs n o sending CMD0 with argument + 0xFFFFFFFA, before issuing CMD1. The data can be read from either boot area or user area depending on register setting. Timing Factor Value Boot ACK Time < 50 ms Boot Data Time