74LVC1G08GV

74LVC1G08 Single 2-input AND gate Rev. 14 — 24 February 2022 Product data sheet 1. General description The 74LVC1G08 is a single 2-input AND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • • Wide supply voltage range from 1.65 V to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power dissipation Direct interface with TTL levels Overvoltage tolerant inputs to 5.5 V IOFF circuitry provides partial Power-down mode operation Latch-up performance ≤ 250 mA Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • JESD36 (4.5 V to 5.5 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 74LVC1G08 Nexperia Single 2-input AND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G08GW -40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74LVC1G08GV -40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753 74LVC1G08GM -40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74LVC1G08GF -40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 74LVC1G08GN -40 °C to +125 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm SOT1115 74LVC1G08GS -40 °C to +125 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm SOT1202 74LVC1G08GX -40 °C to +125 °C X2SON5 plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 × 0.8 × 0.32 mm SOT1226-3 4. Marking Table 2. Marking Type number Marking code [1] 74LVC1G08GW VE 74LVC1G08GV V08 74LVC1G08GM VE 74LVC1G08GF VE 74LVC1G08GN VE 74LVC1G08GS VE 74LVC1G08GX VE [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 B 2 A Y 1 4 2 Logic symbol 74LVC1G08 Product data sheet 4 mna114 mna113 Fig. 1. A & Fig. 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 Y B Fig. 3. mna221 Logic diagram © Nexperia B.V. 2022. All rights reserved 2 / 17 74LVC1G08 Nexperia Single 2-input AND gate 6. Pinning information 6.1. Pinning 74LVC1G08 74LVC1G08 B 1 A 2 GND 3 5 4 B 1 6 VCC A 2 5 n.c. GND 3 4 Y VCC Y 001aab639 001aab638 Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) Transparent top view Fig. 5. Pin configuration SOT886 (XSON6) 74LVC1G08 74LVC1G08 B 1 A 2 GND 3 6 VCC 5 n.c. 4 Y B 5 VCC 4 Y 3 GND A 001aae978 Transparent top view Fig. 6. 1 2 aaa-003023 Pin configuration SOT891, SOT1115 and SOT1202 (XSON6) Transparent top view Fig. 7. Pin configuration SOT1226-3 (X2SON5) 6.2. Pin description Table 3. Pin description Symbol Pin Description TSSOP5, SC-74A and X2SON5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 3 / 17 74LVC1G08 Nexperia Single 2-input AND gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Output Input A B Y L L L L H L H L L H H H 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage Active mode [1] -0.5 Power-down mode; VCC = 0 V [1] -0.5 +6.5 V - ±50 mA VI < 0 V [1] VCC + 0.5 V IO output current ICC supply current - 100 mA IGND ground current -100 - mA Ptot total power dissipation - 250 mW Tstg storage temperature -65 +150 °C [1] [2] VO = 0 V to VCC mA Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT753 (SC-74A) package: Ptot derates linearly with 3.8 mW/K above 85 °C. For SOT886 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT891 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT1115 (XSON6) package: Ptot derates linearly with 3.2 mW/K above 71 °C. For SOT1202 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT1226-3 (X2SON5) package: Ptot derates linearly with 3.0 mW/K above 67 °C. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate 74LVC1G08 Product data sheet Conditions Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V Active mode 0 - VCC V Power-down mode; VCC = 0 V 0 - 5.5 V °C -40 - +125 VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 4 / 17 74LVC1G08 Nexperia Single 2-input AND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions -40 °C to +85 °C HIGH-level input VCC = 1.65 V to 1.95 V voltage VCC = 2.3 V to 2.7 V VIH VIL LOW-level input voltage VOH HIGH-level output voltage Unit Min Typ [1] Max Min Max 0.65VCC - - 0.65VCC - V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - VCC = 2.7 V to 3.6 V - - 0.8 VCC = 4.5 V to 5.5 V - - 0.3VCC VCC - 0.1 - IO = -4 mA; VCC = 1.65 V 1.2 IO = -8 mA; VCC = 2.3 V 1.9 IO = -12 mA; VCC = 2.7 V 0.35VCC V 0.7 V - 0.8 V - 0.3VCC V - VCC - 0.1 - V - - 0.95 - V - - 1.7 - V 2.2 - - 1.9 - V IO = -24 mA; VCC = 3.0 V 2.3 - - 2.0 - V IO = -32 mA; VCC = 4.5 V 3.8 - - 3.4 - V - - 0.10 - 0.10 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.30 - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.40 - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 5.5 V LOW-level output VI = VIH or VIL voltage IO = 100 μA; VCC = 1.65 V to 5.5 V VOL -40 °C to +125 °C II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - ±0.1 ±1 - ±1 μA IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - ±0.1 ±2 - ±2 μA ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 4 - 4 μA ΔICC additional supply per pin; VCC = 2.3 V to 5.5 V; current VI = VCC - 0.6 V; IO = 0 A - 5 500 - 500 μA CI input capacitance - 5 - - - pF [1] VCC = 3.3 V; VI = GND to VCC All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 5 / 17 74LVC1G08 Nexperia Single 2-input AND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 9. Symbol Parameter tpd propagation delay CPD [1] [2] [3] Conditions power dissipation capacitance -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max VCC = 1.65 V to 1.95 V 1.0 3.4 8.0 1.0 10.5 ns VCC = 2.3 V to 2.7 V 0.5 2.2 5.5 0.5 7.0 ns VCC = 2.7 V 0.5 2.5 5.5 0.5 7.0 ns VCC = 3.0 V to 3.6 V 0.5 2.1 4.5 0.5 6.0 ns VCC = 4.5 V to 5.5 V 0.5 1.7 4.0 0.5 5.5 ns - 16 - - - pF A, B to Y; see Fig. 8 [2] VI = GND to VCC; VCC = 3.3 V [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLZ and tPZL. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 11.1. Waveforms and test circuit VI VM A, B input GND t PHL t PLH VOH VM Y output VOL mna614 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. The input A, B to output Y propagation delays Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5VCC 0.5VCC 2.3 V to 2.7 V 0.5VCC 0.5VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5VCC 0.5VCC 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 6 / 17 74LVC1G08 Nexperia Single 2-input AND gate VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to the output impedance Zo of the pulse generator; VEXT = External voltage for measuring switching times. Fig. 9. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VCC VI tr = tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open 74LVC1G08 Product data sheet VEXT Load All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 7 / 17 74LVC1G08 Nexperia Single 2-input AND gate 12. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm D SOT353-1 E B A X c (5x) y HE v M A e1 5 4 pin 1 index A 1 2 A1 3 A3 θ Lp w M B bp (5x) e A2 detail X e 0 3 mm scale Dimensions (mm are the original dimensions) Unit mm max min A A1 A2 A3 1.1 0.8 0.1 0 1.0 0.8 0.15 bp c 0.30 0.25 0.15 0.08 D(1) E(1) 2.2 1.8 1.35 0.65 1.15 e e1 HE Lp v w y θ 1.3 2.4 1.8 0.46 0.26 0.3 0.1 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version SOT353-1 References IEC JEDEC JEITA MO-203 SC-88A sot353-1_po European projection Issue date 21-12-15 21-12-16 Fig. 10. Package outline SOT353-1 (TSSOP5) 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 8 / 17 74LVC1G08 Nexperia Single 2-input AND gate Plastic surface-mounted package; 5 leads SOT753 D B E y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT753 JEITA EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 SC-74A Fig. 11. Package outline SOT753 (SC-74A) 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 9 / 17 74LVC1G08 Nexperia Single 2-input AND gate SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Fig. 12. Package outline SOT886 (XSON6) 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 10 / 17 74LVC1G08 Nexperia Single 2-input AND gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 4 e1 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig. 13. Package outline SOT891 (XSON6) 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 11 / 17 74LVC1G08 Nexperia Single 2-input AND gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 e1 L L1 0.35 0.40 0.30 0.35 0.27 0.32 0.3 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1115_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1115 Fig. 14. Package outline SOT1115 (XSON6) 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 12 / 17 74LVC1G08 Nexperia Single 2-input AND gate XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig. 15. Package outline SOT1202 (XSON6) 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 13 / 17 74LVC1G08 Nexperia Single 2-input AND gate X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0.8 x 0.32 mm SOT1226-3 C Seating Plane X 5x y C D A B E A A3 pin 1 index area A1 pin 1 index area e 1 2 b (4x) v w y1 C C A B C L (4x) 3 k D h (6x) x) (4 5 4 0 1 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 A3 D Dh E b e K L max 0.35 0.04 0.85 0.30 0.85 0.25 0.27 0.10 0.80 0.25 0.80 0.20 0.50 0.22 nom 0.32 0.02 (Typ.) min 0.30 0.00 0.75 0.20 0.75 0.15 0.20 0.17 v 0.1 w y y1 0.05 0.05 0.05 sot1226-3_po Outline version SOT1226-3 References IEC JEDEC EIAJ European projection Issue date 19-11-06 19-11-07 --- Fig. 16. Package outline SOT1226-3 (X2SON5) 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 14 / 17 74LVC1G08 Nexperia Single 2-input AND gate 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G08 v.14 20220224 Product data sheet - Modifications: • 74LVC1G08 v.13 20220209 Modifications: • • • 74LVC1G08 v.12 20180116 Modifications: • • • 74LVC1G08 v.13 Package SOT1226 (X2SON5) changed to SOT1226-3 (X2SON5). Product data sheet - 74LVC1G08 v.12 Section 1 and Section 2 updated. Table 5: Derating values for Ptot total power dissipation updated. Fig. 10: Package outline drawing for SOT353-1 (TSSOP5) has changed. Product data sheet - 74LVC1G08 v.11 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Pin configuration drawing of SOT1226 modified. 74LVC1G08 v.11 20161128 Modifications: • 74LVC1G08 v.10 20120629 Modifications: • • 74LVC1G08 v.9 20111209 Modifications: • 74LVC1G08 v.8 20101019 74LVC1G08 v.7 Product data sheet - 74LVC1G08 v.10 Table 7: The maximum limits for leakage current and supply current have changed. Product data sheet - 74LVC1G08 v.9 Added type number 74LVC1G08GX (SOT1226) Package outline drawing of SOT886 (Fig. 12) modified. - 74LVC1G08 v.8 Product data sheet - 74LVC1G08 v.7 20070717 Product data sheet - 74LVC1G08 v.6 74LVC1G08 v.6 20060619 Product data sheet - 74LVC1G08 v.5 74LVC1G08 v.5 20040915 Product specification - 74LVC1G08 v.4 74LVC1G08 v.4 20021002 Product specification - 74LVC1G08 v.3 74LVC1G08 v.3 20020517 Product specification - 74LVC1G08 v.2 74LVC1G08 v.2 20010406 Product specification - 74LVC1G08 v.1 74LVC1G08 v.1 20001121 Product specification - - 74LVC1G08 Product data sheet Product data sheet Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 15 / 17 74LVC1G08 Nexperia Single 2-input AND gate 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 16 / 17 74LVC1G08 Nexperia Single 2-input AND gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 4 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 6 12. Package outline.......................................................... 8 13. Abbreviations............................................................ 15 14. Revision history........................................................15 15. Legal information......................................................16 © Nexperia B.V. 2022. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 24 February 2022 74LVC1G08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 24 February 2022 © Nexperia B.V. 2022. All rights reserved 17 / 17