AT24C256M/TR

AT24C256 Two-Wire Serial EEPROM 256K (8-bit wide) FEATURES  Low voltage and low power operations:   AT24C256 : VCC = 1.8V to 5.5V 64 bytes page write mode. Partial page write operation allowed. Internally organized: 32,768 ×8 (256K). Standard 2-wire bi-directional serial interface. Schmitt trigger, filtered inputs for noise protection. Self-timed write cycle (5ms maximum). 1 MHz (2.5V-5V), 400 kHz (1.8V) Compatibility. Automatic erase before write operation. Write protect pin for hardware data protection. High reliability: typically 1,000,000 cycles endurance. 100 years data retention.  Industrial temperature range (-40℃ to 85℃).  Standard 8-lead DIP/SOP/MSOP/TSSOP/UDFN Pb-free packages.           DESCRIPTION The AT24C256 series are 262,144 bits of serial Electrical Erasable and Programmable Read Only Memory, commonly known as EEPROM. They are organized as 32,768 words of 8 bits (one byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP,8-lead TSSOP and 8-lead UDFN packages. A standard 2-wire serial interface is used to address all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications. PIN CONFIGURATION Pin Name A2, A1, A0 SDA SCL WP NC Pin Function Device Address Inputs Serial Data Input / Open Drain Output Serial Clock Input Write Protect No-Connect http://www.hgsemi.com.cn 1 2020 MAR AT24C256 All these packaging types come in Pb-free certified. AT24C256 A0 A1 A2 GND 1 8 2 7 3 6 4 5 8L 8L 8L 8L 8L VCC WP SCL SDA DIP SOP MSOP TSSOP UDFN ABSOLUTE MAXIMUM RATINGS Industrial operating temperature: -40℃ to 85℃ Storage temperature: -50℃ to 125℃ Input voltage on any pin relative to ground: Maximum voltage: ESD Protection on all pins: -0.3V to VCC + 0.3V 8V >2000V * Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality. http://www.hgsemi.com.cn 2 2020 MAR AT24C256 PIN DESCRIPTIONS (A) SERIAL CLOCK (SCL) The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. (B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0) These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL. (C) SERIAL DATA LINE (SDA) SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices. (D) WRITE PROTECT (WP) The AT24C256 devices have a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not affected by the WP pin’s input level. MEMORY ORGANIZATION The AT24C256 devices have 512 pages. Since each page has 64 bytes, random word addressing to AT24C256 will require 15 bits data word addresses. DEVICE OPERATION (A) SERIAL CLOCK AND DATA TRANSITIONS The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITION With SCL VIH, a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition. (C) STOP CONDITION With SCL VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-timed internal programming finish (see Figure 1). (D) ACKNOWLEDGE The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. http://www.hgsemi.com.cn 3 2020 MAR AT24C256 (E) STANDBY MODE The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read mode, or after completing a self-time internal programming operation. Figure 1: Timing diagram for START and STOP conditions SCL SDA START Condition Data Valid Data Transition STOP Condition Figure 2: Timing diagram for output ACKNOWLEDGE START Condition SCL Data in ACK Data out DEVICE ADDRESSING The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke a valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These three device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all device address bits (5th, 6th and 7th) as noted below. The last or 8th bit is a read/write command bit. If the 8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming mode. http://www.hgsemi.com.cn 4 2020 MAR AT24C256 WRITE OPERATIONS (A) BYTE WRITE A write operation requires two 8-bit data word address following the device address word and ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a STOP condition. At this time the EEPROM enters into an internally-timed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not respond until the writing is completed (figure 3). (B) PAGE WRITE The 256K EEPROM are capable of 64-byte page write. A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP condition after the first data word is clocked in. The microcontroller can transmit up to 63 more data words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word is received. The microcontroller must terminate the page write sequence with a STOP condition (see Figure 4). The lower six bits of the data word address are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and the previous data will be overwritten. (C) ACKNOWLEDGE POLLING ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9th clock cycle. READ OPERATIONS The read command is similar to the write command except the 8th read/write bit in address word is set to “1”. The three read operation modes are described as follows: (A) CURRENT ADDRESS READ The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the microcontroller issues a START bit and a valid device address word with the read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. The internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode (see Figure 5). (B) SEQUENTIAL READ The sequential read is very similar to current address read. The micro-controller issues a START bit and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. http://www.hgsemi.com.cn 5 2020 MAR AT24C256 Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to current address read, the microcontroller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead (figure 6). (C) RANDOM READ Random read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read. To initialize the internal address counter with a target read address, the micro-controller issues a START bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM will then acknowledge. The micro-controller will then send two address words. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address (figure 7). Figure 3: Byte Write S T A R T DEVICE ADDRESS W R I T E SDA LINE FIRST WORD ADDRESS SECOND WORD ADDRESS S T O P DATA * M S B LRA S / C B WK M S B A C K LA SC BK A C K Figure 4: Page Write S T A R T DEVICE ADDRESS W R I T E SECOND WORD ADDRESS(N) FIRST WORD ADDRESS(N) S T O DATA(N+X) P DATA(N) ... * SDA LINE M S B http://www.hgsemi.com.cn LRA S / C B WK M S B LA SC BK A C K 6 A C K A C K 2020 MAR AT24C256 Figure 5: Current Address Read S T A R T DEVICE ADDRESS R E A D S T O P DATA SDA LINE N O L RA S / C B WK M S B A C K Figure 6: Sequential Read R E A D DEVICE ADDRESS DATA (N) DATA (N+1) DATA (N+2) S T O P DATA (N+3) SDA LINE RA / C WK N O A C K A C K A C K A C K Figure 7: Random Read S T A R T W R I T E DEVICE ADDRESS SECOND WORD ADDRESS(N) FIRST WORD ADDRESS(N) S T A R T DEVICE ADDRESS R E A D S T O P DATA (N) * SDA LINE M S B LRA S / C B WK M S B L A S C B K A C K M S B LRA S / C B WK N O A C K Notes: 1) * = Don’t Care bits http://www.hgsemi.com.cn 7 2020 MAR AT24C256 Figure 8: SCL and SDA Bus Timing tF t HIGH tR tLOW tLOW SCL t SU,STA t HD.STA t HD.DAT t SU.DAT t SU.STO SDA IN t AA t DH t BUF SDA OUT Electrical Specifications (A)Power-Up Requirements During a power-up sequence, the VCC supplied to the device should monotonically rise from GND to the minimum VCC level, with a slew rate no faster than 0.05 V/μs and no slower then 0.1 V/ms. A decoupling cap should be connected to the VCC PAD which is no smaller than 10nF. (B)Device Reset To prevent inadvertent write operations or any other spurious events from occurring during a powerup sequence, this device includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into Standby mode. The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a stable value greater than or equal to the minimum VCC level. t POFF VCC 0 t PWR,R t PUP 0 0 SCL SDA Figure 11: Power on and Power down If an event occurs in the system where the VCC level supplied to the device drops below the maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up sequence in compliance with the requirements defined in this section. http://www.hgsemi.com.cn 8 2020 MAR AT24C256 AC CHARACTERISTICS Symbol 1.8V Parameter Min fSCL tLOW Clock frequency, SCL tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tPWR,R Endurance ) 1000 kHz µs 0.6 0.4 µs START set-up time Input fall time (1 400 Unit Max 0.4 Input rise time tWR Min 1.3 Data in set-up time tPOFF Max Clock pulse width low Clock pulse width high Noise suppression time(1) Clock low to data out valid Time the bus must be free before a new transmission can start(1) START hold time Data in hold time tPUP 2.5-5.0 V 100 50 ns 0.9 0.55 µs 1.3 0.5 µs 0.6 0.25 µs 0.6 0.25 µs 0 0 µs 100 100 ns (1) (1) 0.3 0.3 µs 300 100 ns STOP set-up time 0.6 0.25 µs Date out hold time Vcc slew rate at power up Time required after VCC is stable before the device can accept commands Minimum time at Vcc=0V between power cycles Write cycle time 25oC, Page Mode, 3.3V 50 50 ns 0.1 50 0.1 50 V/ms 100 100 µs 500 500 ms 5 1,000,000 5 ms Write Cycles Notes: 1. This Parameter is expected by characterization but are not fully screened by test. 2. AC Measurement conditions: RL (Connects to Vcc): 1.3KΩ Input Pulse Voltages: 0.3Vcc to 0.7Vcc Input and output timing reference Voltages: 0.5Vcc http://www.hgsemi.com.cn 9 2020 MAR AT24C256 DC CHARACTERISTICS Symbol Parameter Test Conditions Min Typical Units 5.5 V VCC1 24C256 supply V CC ICC1 Supply read current VCC @ 5.0V SCL = 100 kHz 0.4 1.0 mA ICC2 Supply write current VCC @ 5.0V SCL = 100 kHz 2.0 3.0 mA ISB1 Supply current VCC @ 1.8V, VIN = VCC or VSS < 1.0 µA ISB2 Supply current VCC @ 2.5V, VIN = VCC or VSS < 1.0 µA ISB3 Supply current VCC @ 5.0V, VIN = VCC or VSS < 1.0 µA IIL VIN = VCC or VSS 3.0 µA VIN = VCC or VSS 3.0 µA VIL Input leakage current Output leakage current Input low level VIH Input high level VOL2 Output low level VOL1 Output low level ILO http://www.hgsemi.com.cn 1.8 Max -0.6 VCC×0.3 V VCC + 0.5 V VCC @ 3.0V, IOL = 2.1 mA 0.4 V VCC @ 1.8V, IOL = 0.15 mA 0.4 V VCC× 0.7 10 2020 MAR AT24C256 Important statement: Huaguan Semiconductor Co,Ltd. reserves the right to change the products and services provided without notice. Customers should obtain the latest relevant information before ordering, and verify the timeliness and accuracy of this information. Customers are responsible for complying with safety standards and taking safety measures when using our products for system design and machine manufacturing to avoid potential risks that may result in personal injury or property damage. Our products are not licensed for applications in life support, military, aerospace, etc., so we do not bear the consequences of the application of these products in these fields. Our documentation is only permitted to be copied without any tampering with the content, so we do not accept any responsibility or liability for the altered documents. http://www.hgsemi.com.cn 11 2020 MAR