TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Features
Description
◼
Typical 1.4 µA Ultra-low Quiescent Current
The TPL720 series products are CMOS process low Iq linear
◼
Input Voltage Range: 2.4 V to 6 V
regulators with enable control function. The TPL720 series
◼
Output Voltage Options:
products support maximum 400mA output current, with typically
◆
Fixed: 1 V, 1.2 V, 1.8 V, 2.5 V, 2.8 V, 3 V, 3.3 V, 3.6 V
only 1.4 µA ultra-low quiescent current. TPL720 series products
◼
±1% Output Voltage Accuracy under Room Temperature
are stable with low-ESR small ceramic output capacitors from
◼
Maximum Output Current: 400 mA
2.2 μF to 10 μF.
◼
Low Shutdown Current
◼
Low Dropout Voltage: 350 mV at 400 mA
The TPL720 series products have fast response performance
◼
Current Limit and Thermal Protection
when load dynamic drop or raise, especially for the load
◼
Stable with 2.2 μF Ceramic Capacitor
dynamic from with some load. The TPL720 series products have
◼
Active Output Discharge While Disable
current limit and thermal protection, which improves TPL720
◼
Soft-start Limits Input Current Surge During Enable
series products with high reliability.
◼
Operating Temperature Range: −40°C to +85°C
◼
Packages: SOT23-3, SOT23-5, SOT89-3, 1×1 DFN-4
The TPL720 series products have a fixed output voltage range
from 1 V to 3.6 V with ±1% output voltage accuracy, line
Applications
regulation and load regulation under room temperature. The
◼
Handheld Devices with Battery Power Supply
◼
Portable Devices with Battery Power Supply
◼
Wearable Application, Bluetooth Headsets
◼
Wireless and IoT modules
◼
Personal Electronics, Personal Healthcare
TPL720 series products are guaranteed over the operating
temperature range of −40°C to +85°C. The TPL720 series
products are available in SOT23-3 package, SOT23-5 package,
SOT89-3 package, and 1×1 DFN-4 package.
Typical Application Schematic
Input
VOUT
VIN
CIN
Input
Output
CIN
COUT
COUT
TPL720
Series
TPL720
Series
Off On
GND
TPL720 Series without Enable Pin
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Output
VOUT
VIN
EN
GND
TPL720 Series with Enable Pin
1 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Product Family Table
Transport Media,
Output Voltage
Order Number
Package
TPL720F10
Fixed 1.0 V
TPL720F10-3TR
SOT23-3
Tape and Reel, 3,000
L3
L7C
TPL720F12
Fixed 1.2 V
TPL720F12-3TR
SOT23-3
Tape and Reel, 3,000
L3
L7D
TPL720F18
Fixed 1.8 V
TPL720F18-3TR
SOT23-3
Tape and Reel, 3,000
L3
L7F
TPL720F25
Fixed 2.5 V
TPL720F25-3TR
SOT23-3
Tape and Reel, 3,000
L3
L7G
TPL720F28
Fixed 2.8 V
TPL720F28-3TR
SOT23-3
Tape and Reel, 3,000
L3
L7H
TPL720F30
Fixed 3.0 V
TPL720F30-3TR
SOT23-3
Tape and Reel, 3,000
L3
L7I
TPL720F33
Fixed 3.3 V
TPL720F33-3TR
SOT23-3
Tape and Reel, 3,000
L3
L7J
TPL720F36
Fixed 3.6 V
TPL720F36-3TR
SOT23-3
Tape and Reel, 3,000
L3
L7K
TPL720F10
Fixed 1.0 V
TPL720F10-5TR
SOT23-5
Tape and Reel, 3,000
L3
L7C
TPL720F12
Fixed 1.2 V
TPL720F12-5TR
SOT23-5
Tape and Reel, 3,000
L3
L7D
TPL720F18
Fixed 1.8 V
TPL720F18-5TR
SOT23-5
Tape and Reel, 3,000
L3
L7F
TPL720F25
Fixed 2.5 V
TPL720F25-5TR
SOT23-5
Tape and Reel, 3,000
L3
L7G
TPL720F28
Fixed 2.8 V
TPL720F28-5TR
SOT23-5
Tape and Reel, 3,000
L3
L7H
TPL720F30
Fixed 3.0 V
TPL720F30-5TR
SOT23-5
Tape and Reel, 3,000
L3
L7I
TPL720F33
Fixed 3.3 V
TPL720F33-5TR
SOT23-5
Tape and Reel, 3,000
L3
L7J
TPL720F36
Fixed 3.6 V
TPL720F36-5TR
SOT23-5
Tape and Reel, 3,000
L3
L7K
TPL720F10
Fixed 1.0 V
TPL720F10-89TR
SOT89-3
Tape and Reel, 4,000
L3
L7C
TPL720F12
Fixed 1.2 V
TPL720F12-89TR
SOT89-3
Tape and Reel, 4,000
L3
L7D
TPL720F18
Fixed 1.8 V
TPL720F18-89TR
SOT89-3
Tape and Reel, 4,000
L3
L7F
TPL720F25
Fixed 2.5 V
TPL720F25-89TR
SOT89-3
Tape and Reel, 4,000
L3
L7G
TPL720F28
Fixed 2.8 V
TPL720F28-89TR
SOT89-3
Tape and Reel, 4,000
L3
L7H
TPL720F30
Fixed 3.0 V
TPL720F30-89TR
SOT89-3
Tape and Reel, 4,000
L3
L7I
TPL720F33
Fixed 3.3 V
TPL720F33-89TR
SOT89-3
Tape and Reel, 4,000
L3
L7J
TPL720F36
Fixed 3.6 V
TPL720F36-89TR
SOT89-3
Tape and Reel, 4,000
L3
L7K
TPL720F10
Fixed 1.0 V
TPL720F10-FR
1×1 DFN-4
Tape and Reel, 12,000
L3
L7C
TPL720F12
Fixed 1.2 V
TPL720F12-FR
1×1 DFN-4
Tape and Reel, 12,000
L3
L7D
TPL720F18
Fixed 1.8 V
TPL720F18-FR
1×1 DFN-4
Tape and Reel, 12,000
L3
L7F
TPL720F25
Fixed 2.5 V
TPL720F25-FR
1×1 DFN-4
Tape and Reel, 12,000
L3
L7G
TPL720F28
Fixed 2.8 V
TPL720F28-FR
1×1 DFN-4
Tape and Reel, 12,000
L3
L7H
TPL720F30
Fixed 3.0 V
TPL720F30-FR
1×1 DFN-4
Tape and Reel, 12,000
L3
L7I
TPL720F33
Fixed 3.3 V
TPL720F33-FR
1×1 DFN-4
Tape and Reel, 12,000
L3
L7J
TPL720F36
Fixed 3.6 V
TPL720F36-FR
1×1 DFN-4
Tape and Reel, 12,000
L3
L7K
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2 / 18
Quantity
MSL
Marking
Part Number
Information
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Table of Contents
Features ........................................................................................................................................................................... 1
Applications ..................................................................................................................................................................... 1
Description....................................................................................................................................................................... 1
Typical Application Schematic....................................................................................................................................... 1
Product Family Table ...................................................................................................................................................... 2
Table of Contents ............................................................................................................................................................ 3
Revision History .............................................................................................................................................................. 4
Pin Configuration and Functions .................................................................................................................................. 5
Specifications .................................................................................................................................................................. 6
Absolute Maximum Ratings .......................................................................................................................................................... 6
ESD, Electrostatic Discharge Protection ...................................................................................................................................... 6
Recommended Operating Conditions .......................................................................................................................................... 6
Thermal Information ..................................................................................................................................................................... 6
Electrical Characteristics .............................................................................................................................................................. 7
Typical Performance Characteristics ............................................................................................................................................ 8
Detailed Description ..................................................................................................................................................... 10
Overview .................................................................................................................................................................................... 10
Functional Block Diagram .......................................................................................................................................................... 10
Feature Description .....................................................................................................................................................................11
Application and Implementation.................................................................................................................................. 12
Application Information ............................................................................................................................................................... 12
Typical Application ...................................................................................................................................................................... 12
Layout Requirements ................................................................................................................................................................. 13
Tape and Reel Information ........................................................................................................................................... 14
Package Outline Dimensions ....................................................................................................................................... 15
SOT23-3..................................................................................................................................................................................... 15
SOT23-5..................................................................................................................................................................................... 16
SOT89-3..................................................................................................................................................................................... 17
1×1 DFN-4.................................................................................................................................................................................. 18
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3 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Revision History
Date
Revision
2018/09/08
Rev.Pre
Preliminary Version
2019/01/10
Rev.A.0
Initial Release
2019/08/30
Rev.A.1
Add 3.6V Output Voltage Option
2021/03/29
Rev.A.2
www.3peakic.com.cn
Notes
1. Change the Pin 1 Orientation of SOT23-3 package in Page 5
2. Add Tape and Reel Information in Page 14
4 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Pin Configuration and Functions
GND
TPL720 Series
TPL720 Series
3-Pin SOT23 Package
3-Pin SOT89 Package
1
3
OUT
IN
IN
2
3
OUT
2
IN
1
GND
TPL720 Series
TPL720 Series
5-Pin SOT23 Package
4-Pin DFN Package
IN
IN
1
GND
2
EN
3
5
OUT
EN
4
3
Thermal
Pad
4
1
NC
OUT
2
GND
Pin Functions
Pin Number
Name
I/O
Description
SOT23-
SOT23-
SOT89-
DFN-
3
5
3
4
EN
−
3
−
3
I
GND
1
2
1
2
−
Ground reference pin. Connect GND pin to PCB ground plane directly.
IN
3
1
2
4
I
Input voltage pin. Bypass IN to GND with a 1 μF or greater capacitor.
NC
−
4
−
−
−
No connection.
OUT
2
5
3
1
O
Regulator enable pin. Drive EN high to turn on the regulator; drive EN low to turn off
the regulator. For automatic startup, connect EN to IN directly.
Regulated output voltage pin. Bypass OUT to GND with a 2.2 μF or greater
capacitor.
Note: Thermal pad must be connected to PCB ground plane to maximum the thermal performance.
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5 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Specifications
Absolute Maximum Ratings
Parameters
Min
Max
Unit
VIN, VEN
Input Voltage
−0.3
6.5
V
VOUT
Output Voltage
−0.3
6.5
V
TJ
Junction Temperature Range
−40
150
°C
TSTG
Storage Temperature Range
−65
150
°C
TL
Lead Temperature (Soldering 10 sec)
260
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
(2) All voltage values are with respect to GND.
ESD, Electrostatic Discharge Protection
Symbol
Parameter
Condition
Minimum Level
Unit
HBM
Human Body Model ESD
ANSI/ESDA/JEDEC JS-001
±4
kV
CDM
Charged Device Model ESD
ANSI/ESDA/JEDEC JS-002
±1
kV
Recommended Operating Conditions
Parameters
Min
Max
Unit
2.4
6
V
VIN
Input Voltage
VEN
Enable Voltage
0
VIN
V
VOUT
Output Voltage
0
5
V
IOUT
Output Current
0
400
mA
TJ
Operating Junction Temperature Range
−40
125
°C
TA
Operating Ambient Temperature Range
−40
85
°C
Thermal Information
θJA
θJC
Unit
SOT23-3
280
62
°C/W
SOT23-5
280
62
°C/W
SOT89-3
55
88
°C/W
1×1 DFN-4
210
110
°C/W
Package Type
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6 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Electrical Characteristics
All test condition: VIN = VOUT(NOM) + 2 V or 2.4 V, whichever is greater; COUT = 2.2 µF, TA = +25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
6
V
Supply Input Voltage and Current
VIN
Input voltage range
IGND
Ground pin current
ISHDN
Shutdown current
UVLO
VIN under-voltage lock-out
2.4
IOUT = 0 mA
1.4
µA
IOUT = 1 mA
2.8
µA
EN = GND (4-/5-Pin Package Only)
0.1
µA
VIN rising
1.8
V
Hysteresis
200
mV
Enable Input Voltage and Current (4-/5-Pin Package Only)
VIH(EN)
EN logic-input high level (enable)
1.2
VIN
V
VIL(EN)
EN logic-input low level (disable)
0
0.4
V
IEN
EN pin leakage current
EN = VIN
20
IOUT = 30 mA, TJ = +25°C
1%
nA
Regulated Output Voltage and Current
VOUT
ΔVOUT
Output voltage accuracy
Line regulation
Load regulation
VDO (1)
Dropout voltage
IOUT = 30 mA, –40°C ≤ TJ ≤ +125°C
−3%
VIN = VOUT(NOM) + 2 V to 6 V, or VIN ≥
3%
3
mV
IOUT = 1 mA to 400 mA
40
mV
VIN = 0.98 × VOUT(NOM), IOUT = 100 mA
80
mV
VIN = 0.98 × VOUT(NOM), IOUT = 200 mA
170
mV
VIN = 0.98 × VOUT(NOM), IOUT = 400 mA
350
mV
2.4V,IOUT = 1 mA
IOUT
Output current
VOUT in regulation
ICL
Output current limit
VOUT = 0.9 × VOUT(NOM)
RDIS
Output discharge resistance
VIN = VOUT(NOM) + 2 V, EN = GND
190
Ω
IOUT = 10 mA, f = 100 Hz, COUT = 2.2 µF
55
dB
IOUT = 10 mA, f = 1 kHz, COUT = 2.2 µF
54
dB
IOUT = 10 mA, f = 10 kHz, COUT = 2.2 µF
50
dB
IOUT = 10 mA, f = 1 MHz, COUT = 2.2 µF
53
dB
IOUT = 10 mA, BW = 10Hz to 100 kHz
90
μVRMS
IOUT = 200 mA, COUT = 2.2 μF
680
μs
Thermal shutdown temperature
165
ºC
Thermal shutdown hysteresis
15
ºC
PSRR
VN
tSTR
Power supply rejection ratio
Output noise voltage
Start-up time from EN assertion to 0.98
× VOUT(NOM)
0
410
560
400
mA
800
mA
Temperature Range
TSD
*Note: (1). Dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output
current. In dropout, the output voltage will be equal to: VIN – VDROPOUT.
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7 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Typical Performance Characteristics
All test condition: VIN = VOUT(NOM) + 2 V or 2.4 V, whichever is greater; COUT = 2.2 µF, TA = +25°C, unless otherwise noted.
1000
5
–40°C
800
Ground Current (µA)
Ground Current (µA)
–40°C
25°C
85°C
600
400
200
0
4
25°C
85°C
3
2
1
0
0
100
200
300
400
3
4
Load Current (mA)
VOUT = 3.3V
7
Figure 2 Quiescent Current vs Input Voltage
2
0.6
1.8
VIN = 2.1V
VIN = 2.5V
1.6
VIN = 3V
VIN = 3.3V
1.4
VIN = 5V
VIN = 5.5V
1.2
VIN = 6V
Dropout Voltage (V)
Shutdown Current(uA)
6
VOUT = 3.3V
Figure 1 Ground Current vs Output Current
1
0.8
0.6
0.4
0.2
–40°C
0.5
25°C
0.4
85°C
0.3
0.2
0.1
0
0
-40
-15
10
35
60
0
85
100
200
300
400
Load Current (mA)
Temperature(℃)
With Enable Pin
VOUT = 3.3V
Figure 3 Shutdown Current vs Ambient Temperature
Figure 4 Dropout Voltage vs Output Current
4.0
Output Voltage (V)
3.4
Output Voltage (V)
5
Supply Voltage (V)
3.35
3.3
3.25
3.2
3.0
2.0
1.0
0.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
Ambient Temperature (°C)
2
3
4
5
6
Supply Voltage (V)
VOUT = 3.3V
VOUT = 3.3V
Figure 5 Output Accuracy vs Ambient Temperature
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1
Figure 6 Output Voltage vs Input Voltage
8 / 18
Rev.A.2
7
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Typical Performance Characteristics (continued)
Test condition: VIN = VOUT(NOM) + 2 V or 2.4 V, whichever is greater; COUT = 2.2 µF, TA = +25°C, unless otherwise noted.
3.40
Output Voltage (V)
Output Voltage (V)
3.40
3.35
3.30
–40°C
3.25
25°C
3.35
3.30
–40°C
3.25
25°C
85°C
85°C
3.20
3.20
3
4
5
6
7
0
100
Supply Voltage (V)
200
300
400
Load Current (mA)
VOUT = 3.3V
VOUT = 3.3V
Figure 7. Line Regulation
Figure 8. Load Regulation
4.0
80
3.0
60
PSRR (dB)
Output Voltage (V)
70
2.0
1.0
50
40
30
20
10
0.0
0
0
200
400
600
800
10
Load Current (mA)
1K
10K
100K
1M
Frequency (Hz)
VOUT = 3.3V
VOUT = 3.3V
Figure 9. Current Limit
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100
IOUT = 10 mA
COUT = 2.2 µF
Figure 10. PSRR
9 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Detailed Description
Overview
The TPL720 series products are CMOS process low Iq linear regulators with ultra-low quiescent power consumption. The TPL720
series products support maximum 400mA output current, with typically only 1.4 µA quiescent current. TPL720 series products are
stable with low-ESR small ceramic output capacitor from 2.2μF to 10μF. The TPL720 series products are available in fixed voltage
versions of 1V, 1.2 V, 1.8 V, 2.5 V, 2.8 V, 3 V, 3.3 V and 3.6 V.
Functional Block Diagram
IN
OUT
UVLO
Ban dgap
Regula tor
Control
+
–
VBG
GND
Thermal
Shu tdo wn
Curren t
Limit
TPL720 Series without Enable Pin
IN
OUT
UVLO
Ban dgap
Regula tor
Control
+
–
VBG
Thermal
Shu tdo wn
EN
GND
Curren t
Limit
TPL720 Series with Enable Pin
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10 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Feature Description
Enable (4-/5-Pin Package Only)
The enable pin (EN) is active high. Connect this pin to the GPIO of an external processor or digital logic control circuit to enable and
disable the device. Or connect this pin to the IN pin for self-bias applications.
Under-voltage Lockout (UVLO)
The TPL720 series use an under-voltage lockout circuit (UVLO = 1.8 V) to keep the output shut off until the internal circuitry operates
properly.
Regulated Output Voltage
The TPL720 series are available in fixed voltage versions of 1V, 1.2 V, 1.8 V, 2.5 V, 2.8 V, 3 V, 3.3 V and 3.6 V. When the input voltage
is higher than VOUT(NOM) + VDO or 2.4V, output pin is the regulated output based on the selected voltage version. When the input
voltage falls below VOUT(NOM) + VDO or 2.4V, output pin tracks the input voltage minus the dropout voltage based on the load current.
When the input voltage drops below UVLO threshold, the output keeps shut off.
Current Limit
The TPL720 series integrate an internal current limit that helps to protect the regulator during fault conditions. When the output is
overloaded or shorted to ground, the LDO supplies output current with limited value to prevent the regulator from damage. Output
voltage is not regulated when the device is in current limit mode, and the value is VOUT = ICL × RLOAD.
Thermal Shutdown
During normal operation, LDO junction temperature should not exceed 125°C. When the junction temperature exceeds the thermal
shutdown threshold, the LDO shut down the output immediately. Until when the junction temperature falls below the thermal shutdown
threshold minus thermal shutdown hysteresis, the output turns on again.
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11 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Application and Implementation
NOTE
Information in the following applications sections is not part of the 3PEAK’s component specification and 3PEAK does
not warrant its accuracy or completeness. 3PEAK’s customers are responsible for determining suitability of
components for their purposes. Customers should validate and test their design implementation to confirm system
functionality.
Application Information
The TPL720 devices are a series of 400 mA high PSRR, low-dropout linear regulator with low quiescent current. The following
application schematic shows a typical usage of the TPL720 series.
Typical Application
Figure 11 shows the typical application schematic of the TPL720 series.
Input
VOUT
VIN
CIN
Output
COUT
TPL720
Series
Off On
(1)
EN(1)
GND
EN pin is only available in 4-/5-pin package
Figure 11 TPL720 Series Application Schematic
Input Capacitor and Output Capacitor
3PEAK recommends adding a 1 μF or greater capacitor with a 0.1 μF bypass capacitor in parallel at IN pin to keep the input voltage
stable. The voltage rating of the capacitors must be greater than the maximum input voltage.
To ensure loop stability, the TPL720 series requires an output capacitor with a minimum effective capacitance value of 2.2 μF. 3PEAK
recommends selecting a X5R- or X7R-type 4.7 μF or larger ceramic capacitor with low ESR over temperature.
Both input capacitors and output capacitors must be placed as close to the device pins as possible.
Power Dissipation
During normal operation, LDO junction temperature should not exceed 125°C. Using below equations to calculate the power
dissipation and estimate the junction temperature.
The power dissipation can be calculated using Equation 1.
PD = ( VIN − VOUT ) IOUT + VIN IGND
(1)
The junction temperature can be estimated using Equation 2. θJA is the junction-to-ambient thermal resistance (See Section Thermal
Information).
TJ = TA + PD JA
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(2)
12 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Layout Requirements
•
Both input capacitors and output capacitors must be placed as close to the device pins as possible.
•
It is recommended to bypass the input pin to ground with a 0.1 μF bypass capacitor. The loop area formed by the bypass
capacitor connection, IN pin and the GND pin of the system must be as small as possible.
•
It is recommended to use wide trace lengths or thick copper weight to minimize I×R drop and heat dissipation.
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13 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Tape and Reel Information
Order Number
Package
D1
W1
A0
B0
K0
P0
W0
Pin1 Quadrant
TPL720Fxx-3TR
SOT23-3
180
13.1
3.18
3.28
1.32
4
8
Q3
TPL720Fxx-5TR
SOT23-5
180
13.1
3.2
3.2
1.4
4
8
Q3
TPL720Fxx-89TR
SOT89-3
330
17.6
4.8
4.4
1.8
8
12
Q3
TPL720Fxx-FR
1×1 DFN-4
180
12.3
1.16
1.16
0.5
4
8
TBD
(1) Output voltage value, xx = 10 to 36. e.g. 33 means 3.3 V output voltage.
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14 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
Package Outline Dimensions
SOT23-3
www.3peakic.com.cn
15 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
SOT23-5
www.3peakic.com.cn
16 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
SOT89-3
www.3peakic.com.cn
17 / 18
Rev.A.2
TPL720 Series
400 mA output, 1 µA Ultra-Low Quiescent Current LDO
1×1 DFN-4
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other trademarks are the property of their respective owners.
www.3peakic.com.cn
18 / 18
Rev.A.2