PSMN1R4-40YLDX

PSMN1R4-40YLD N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology 14 March 2019 Product data sheet 1. General description 240 Amp, logic level gate drive N-channel enhancement mode MOSFET in 175 °C LFPAK56 package using advanced TrenchMOS Superjunction technology. This product has been designed and qualified for high performance power switching applications. 2. Features and benefits • • • • • • • • • 240 A capability Avalanche rated, 100% tested at IAS = 190 A NextPower-S3 technology delivers 'superfast switching with soft recovery' Low QRR, QG and QGD for high system efficiency and low EMI designs Schottky-Plus body-diode, gives soft switching without the associated high IDSS leakage Optimised for 4.5 V gate drive utilising NextPower-S3 Superjunction technology High reliability LFPAK (Power SO8) package, copper-clip, solder die attach and qualified to 175 °C Exposed leads can be wave soldered, visual solder joint inspection and high quality solder joints Low parasitic inductance and resistance 3. Applications • • • • • Synchronous rectification DC-to-DC converters High performance & high efficiency server power supply Motor control Power OR-ing 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 40 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - - 240 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 238 W Tj junction temperature -55 - 175 °C VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 1.38 1.85 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 1.12 1.4 mΩ [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology Symbol Parameter Conditions Min Typ Max Unit QGD gate-drain charge - 13 26 nC QG(tot) total gate charge ID = 25 A; VDS = 20 V; VGS = 4.5 V; Fig. 12; Fig. 13 - 45 65 nC [1] 240A continuous current has been successfully demonstrated during application test. Practically, the current will be limited by PCB, thermal design and operating temperature. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 1 2 3 4 LFPAK56; PowerSO8 (SOT669) 6. Ordering information Table 3. Ordering information Type number Package PSMN1R4-40YLD Name Description Version LFPAK56; Power-SO8 Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads SOT669 7. Marking Table 4. Marking codes Type number Marking code PSMN1R4-40YLD 1D440L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 40 V VDSM peak drain-source voltage tp ≤ 20 ns; f ≤ 500 kHz; EDS(AL) ≤ 200 nJ; pulsed - 45 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 40 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 238 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 IDM peak drain current Tstg storage temperature PSMN1R4-40YLD Product data sheet - 240 A VGS = 10 V; Tmb = 100 °C; Fig. 2 - 214 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 1201 A -55 175 °C All information provided in this document is subject to legal disclaimers. 14 March 2019 [1] © Nexperia B.V. 2019. All rights reserved 2 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology Symbol Parameter Tj Conditions Min Max Unit junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage HBM 2 - kV Source-drain diode IS source current Tmb = 25 °C - 198.6 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 1201 A Avalanche ruggedness EDS(AL)S IAS [1] [2] ID = 74 A; Vsup ≤ 40 V; RGS = 50 Ω; non-repetitive drainsource avalanche energy VGS = 10 V; Tj(init) = 25 °C; unclamped; tp = 0.23 ms [2] - 446 mJ ID = 25 A; Vsup ≤ 40 V; RGS = 50 Ω; VGS = 10 V; Tj(init) = 25 °C; unclamped; tp = 2.52 ms [2] - 1641 mJ [2] - 190 A non-repetitive avalanche Vsup ≤ 40 V; VGS = 10 V; Tj(init) = 25 °C; current RGS = 50 Ω 240A continuous current has been successfully demonstrated during application test. Practically, the current will be limited by PCB, thermal design and operating temperature. Protected by 100% test 03aa16 120 Pder (%) aaa-013028 320 ID (A) 240 (1) 80 160 40 80 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 Fig. 2. Product data sheet 25 50 75 100 125 150 175 Tmb (°C) 200 (1) 240A Continuous current has been successfully demonstrate during application tests. Practically the current will be limited by PCB, thermal design and operation temperature. VGS ≥ 10 V Normalized total power dissipation as a function of mounting base temperature PSMN1R4-40YLD 0 Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 3 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology ID (A) aaa-013030 104 Limit RDSon = VDS / ID 103 tp = 10 µs 102 100 µs 10 DC 1 ms 10 ms 100 ms 1 10-1 10-1 Fig. 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from Fig. 4 junction to mounting base - 0.56 0.63 K/W Rth(j-a) thermal resistance from Fig. 5 junction to ambient Fig. 6 - 50 - K/W - 125 - K/W 1 Zth(j-mb) (K/W) 10-1 aaa-009500 δ = 0.5 0.2 0.1 0.05 0.02 10-2 single shot P δ= Fig. 4. 10-5 10-4 10-3 10-2 T t tp 10-3 10-6 tp T 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN1R4-40YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 4 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology aaa-005751 aaa-005750 Fig. 5. PCB layout for thermal resistance junction to ambient 1” square pad; FR4 Board; 2oz copper Fig. 6. PCB layout for thermal resistance junction to ambient minimum footprint;FR4 board; 2oz copper 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C 1.05 1.7 2.2 V ΔVGS(th)/ΔT gate-source threshold voltage variation with temperature 25 °C ≤ Tj ≤ 150 °C - -4.8 - mV/K IDSS drain leakage current VDS = 32 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 32 V; VGS = 0 V; Tj = 125 °C - 12 - µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 1.12 1.4 mΩ VGS = 10 V; ID = 25 A; Tj = 175 °C; Fig. 10; Fig. 11 - - 2.65 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 1.38 1.85 mΩ VGS = 4.5 V; ID = 25 A; Tj = 175 °C; Fig. 10; Fig. 11 - - 3.4 mΩ f = 1 MHz - 1.1 3.43 Ω ID = 25 A; VDS = 20 V; VGS = 10 V; Fig. 12; Fig. 13 - 96 143 nC ID = 25 A; VDS = 20 V; VGS = 4.5 V; Fig. 12; Fig. 13 - 45 65 nC ID = 0 A; VDS = 0 V; VGS = 10 V - 85 - nC ID = 25 A; VDS = 20 V; VGS = 4.5 V; Fig. 12; Fig. 13 - 15 25 nC - 9 - nC Static characteristics V(BR)DSS IGSS RDSon RG gate leakage current drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gatesource charge PSMN1R4-40YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 5 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology Symbol Parameter Conditions Min Typ Max Unit QGS(th-pl) post-threshold gatesource charge - 6 - nC QGD gate-drain charge VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 20 V; Fig. 12; Fig. 13 - 13 26 nC - 2.7 - V Ciss input capacitance Coss output capacitance VDS = 20 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 14 - 6661 10413 pF Crss reverse transfer capacitance - 1543 2309 pF - 299 658 pF td(on) turn-on delay time - 39 - ns tr rise time - 49 - ns td(off) tf turn-off delay time - 47 - ns fall time - 30 - ns Qoss output charge VGS = 0 V; VDS = 20 V; f = 1 MHz; Tj = 25 °C - 50 - nC VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V; RG(ext) = 5 Ω Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.78 1.2 V trr reverse recovery time - 47 - ns Qr recovered charge IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V; Fig. 16 [1] - 61 - nC ta reverse recovery rise time - 25.4 - ns tb reverse recovery fall time - 21.7 - ns [1] includes capacitive recovery 300 ID (A) 250 aaa-013032 10 V RDSon (mΩ) 3.5 V 4.5 V aaa-013033 4 3 200 150 2 100 VGS = 3 V 1 50 2.8 V 2.6 V 0 0 1 2 3 4 VDS (V) 0 5 0 2 4 6 8 10 12 14 VGS (V) 16 Tj = 25 °C Fig. 7. Output characteristics; drain current as a Fig. 8. function of drain-source voltage; typical values PSMN1R4-40YLD Product data sheet Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 6 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology aaa-013035 300 ID (A) 250 aaa-013038 10 RDSon (mΩ) 2.8 V 3V 8 200 3.5 V 6 150 4 100 175°C 50 Tj = 25°C 4.5 V 2 10 V 0 0 0.5 1 1.5 2 2.5 3 3.5 VGS (V) 0 4 0 60 120 180 240 ID (A) 300 Tj = 25 °C Fig. 9. a Transfer characteristics; drain current as a function of gate-source voltage; typical values Fig. 10. Drain-source on-state resistance as a function of drain current; typical values aaa-013039 2 VDS 10 V 1.6 ID VGS = 4.5 V VGS(pl) 1.2 VGS(th) VGS 0.8 QGS1 0.4 0 -60 QGS2 -30 0 30 60 90 120 150 Tj (°C) QGS QGD QG(tot) 003aaa508 Fig. 12. Gate charge waveform definitions 180 Fig. 11. Normalized drain-source on-state resistance factor as a function of junction temperature PSMN1R4-40YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 7 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology VGS (V) aaa-013040 10 aaa-013041 104 C (pF) Ciss 8 103 Coss 6 32 V 20 V 4 Crss 102 VDS = 8 V 2 0 0 20 40 60 80 QG (nC) 10 10-1 100 10 VDS (V) 003aal160 aaa-013042 103 102 Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values Fig. 13. Gate-source voltage as a function of gate charge; typical values IS (A) 1 ID (A) trr 102 ta tb 0 10 0.25 IRM 175°C 1 0 0.2 0.4 Tj = 25°C 0.6 0.8 1 VSD (V) IRM t (s) 1.2 Fig. 16. Reverse recovery timing definition Fig. 15. Source current as a function of source-drain voltage; typical values PSMN1R4-40YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 8 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology 11. Package outline Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w b A X c 1/2 e A (A3) A1 C q L detail X 0 y C θ 5 mm 8° scale 0° Dimensions (mm are the original dimensions) Unit(1) mm A A1 A2 A3 b b2 max 1.20 0.15 1.10 0.50 4.41 nom 0.25 min 1.01 0.00 0.95 0.35 3.62 c c2 D(1) D1(1) E(1) E1(1) b3 b4 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 2.0 0.7 0.19 0.24 3.80 4.8 3.1 e 1.27 H L L1 L2 6.2 0.85 1.3 1.3 5.8 0.40 0.8 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. Outline version SOT669 References IEC JEDEC JEITA w y 0.25 0.1 sot669_po European projection Issue date 11-03-25 13-02-27 MO-235 Fig. 17. Package outline LFPAK56; Power-SO8 (SOT669) PSMN1R4-40YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 9 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology 12. Soldering Footprint information for reflow soldering SOT669 4.7 4.2 0.9 (3×) 0.25 (2×) 0.25 (2×) 0.6 (4×) 3.45 0.6 (3×) 2 3.5 2.55 0.25 (2×) SR opening = Cu + 0.075 1.1 2.15 3.3 SP opening = Cu - 0.050 0.7 (4×) 1.27 3.81 solder lands solder paste 125 µm stencil solder resist occupied area Dimensions in mm sot669_fr Fig. 18. Reflow soldering footprint for LFPAK56; Power-SO8 (SOT669) PSMN1R4-40YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 10 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology Wave soldering footprint information for LFPAK56 package SOT669 4.826 1.78 1.72 2.1 1.4 0.6 (x4) 1.27 0.635 solder lands Dimensions in mm Issue date 15-04-13 15-04-16 sot669_fw Fig. 19. Wave soldering footprint for LFPAK56; Power-SO8 (SOT669) PSMN1R4-40YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 11 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology 13. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 12 / 13 PSMN1R4-40YLD Nexperia N-channel 40 V, 1.4 mΩ, 240 A logic level MOSFET in LFPAK56 using NextPower-S3 technology Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 2 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 5 11. Package outline.......................................................... 9 12. Soldering................................................................... 10 13. Legal information......................................................12 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 14 March 2019 PSMN1R4-40YLD Product data sheet All information provided in this document is subject to legal disclaimers. 14 March 2019 © Nexperia B.V. 2019. All rights reserved 13 / 13