74LVC377D,118

74LVC377 Octal D-type flip-flop with data enable; positive-edge trigger Rev. 7 — 27 August 2021 Product data sheet 1. General description The 74LVC377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. 2. Features and benefits • • • • • • • • Wide supply voltage range from 1.2 V to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power consumption Direct interface with TTL levels Output drive capability 50 Ω transmission lines at 125 °C Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V • CDM JESD22-C101E exceeds 1000 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC377D -40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LVC377PW -40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger 4. Functional diagram 11 1 11 3 4 7 8 13 14 17 18 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 E 1 Fig. 1. 3 CP 2 1C2 G1 2 2D 4 5 6 7 6 9 8 9 12 13 12 14 15 17 16 18 19 5 15 16 19 mna919 mna918 Logic symbol Fig. 2. IEC logic symbol 5. Pinning information 5.1. Pinning 74LVC377 E 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP mna917 Fig. 3. Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20) 5.2. Pin description Table 2. Pin description Symbol Pin Description E 1 data enable input (active LOW) CP 11 clock input (LOW to HIGH; edge-triggered) D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 flip-flop output GND 10 ground (0 V) VCC 20 power supply 74LVC377 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 2 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition ↑ = LOW to HIGH CP transition; NC = no change; X = don’t care Input Output CP E Dn Qn Load 1 ↑ I h H Load 0 ↑ I I L Hold ↑ h X NC Do nothing X H X NC Operating mode Control 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +6.5 V VI input voltage [1] -0.5 +5.5 V VO output voltage [2] -0.5 VCC + 0.5 V IIK input clamping current VI < 0 V -50 - mA IO output current VO = 0 V to VCC - ±50 mA IOK output clamping current VO > VCC or VO < 0 V - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] [3] Tamb = -40 °C to +125 °C [3] The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. For SOT163-1 (SO20) package: Ptot derates linearly with 12.3 mW/K above 109 °C. For SOT360-1 (TSSOP20) package: Ptot derates linearly with 10.0 mW/K above 100 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC 1.65 - 3.6 V 1.2 - - V supply voltage functional VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature in free air -40 - +125 °C Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 74LVC377 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 3 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage VOH Conditions -40 °C to +85 °C VCC = 1.2 V VCC = 1.65 V to 1.95 V Unit Min Typ [1] Max Min Max 1.08 - - 1.08 - V 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC - 0.2 - - VCC - 0.3 - V IO = -4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = -8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V VI = VIH or VIL HIGH-level output voltage IO = -100 μA; VCC = 1.65 V to 3.6 V VI = VIH or VIL LOW-level output voltage IO = 100 μA; VCC = 1.65 V to 3.6 V VOL -40 °C to +125 °C 0.35VCC V II input leakage VCC = 3.6 V; VI = 5.5 V or GND current - ±0.1 ±5 - ±20 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 μA ΔICC additional per input pin; VCC = 2.7 V to 3.6 V; supply current VI = VCC - 0.6 V; IO = 0 A - 5 500 - 5000 μA CI input capacitance - 5.0 - - - pF [1] VCC = 0 V to 3.6 V; VI = GND to VCC All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 74LVC377 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 4 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 6. Symbol Parameter Conditions -40 °C to +85 °C Min tpd propagation delay CP to Qn; see Fig. 4 tsu pulse width set-up time Max Min Unit Max [2] VCC= 1.2 V tW Typ [1] -40 °C to +125 °C - 15 - - - ns VCC= 1.65 V to 1.95 V 2.5 7.4 14.5 2.5 15.5 ns VCC= 2.3 V to 2.7 V 1.8 4.4 8.5 1.8 9.1 ns VCC = 2.7 V 1.5 4.3 7.9 1.5 10.0 ns VCC = 3.0 V to 3.6 V 1.5 4.0 7.6 1.5 9.5 ns VCC = 1.65 V to 1.95 V 6.0 - - 6.0 - ns VCC = 2.3 V to 2.7 V 5.0 - - 5.0 - ns VCC = 2.7 V 5.0 1.6 - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 1.0 - 4.0 - ns VCC = 1.65 V to 1.95 V 5.5 - - 5.5 - ns VCC = 2.3 V to 2.7 V 4.5 - - 4.5 - ns VCC = 2.7 V 4.0 0.6 - 4.0 - ns VCC = 3.0 V to 3.6 V 3.0 0.2 - 3.0 - ns VCC = 1.65 V to 1.95 V 5.5 - - 5.5 - ns VCC = 2.3 V to 2.7 V 4.5 - - 4.5 - ns VCC = 2.7 V 3.0 1.0 - 3.0 - ns VCC = 3.0 V to 3.6 V 2.0 0.7 - 2.0 - ns VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns VCC = 2.3 V to 2.7 V 0.5 - - 0.5 - ns VCC = 2.7 V 0.0 -1.0 - 0.0 - ns VCC = 3.0 V to 3.6 V 1.0 0 - 1.0 - ns VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns VCC = 2.3 V to 2.7 V 0.5 - - 0.5 - ns VCC = 2.7 V 0.0 -1.1 - 0.0 - ns VCC = 3.0 V to 3.6 V 0.0 -1.0 - 0.0 - ns VCC = 1.65 V to 1.95 V 80 - - 64 - MHz VCC = 2.3 V to 2.7 V 100 - - 80 - MHz VCC = 2.7 V 150 - - 120 - MHz VCC = 3.0 V to 3.6 V 150 330 - 120 - MHz - - 1.0 - 1.5 clock HIGH or LOW; see Fig. 4 E to CP; see Fig. 5 Dn to CP; see Fig. 5 th hold time E to CP; see Fig. 5 Dn to CP; see Fig. 5 fmax tsk(o) maximum frequency output skew time 74LVC377 Product data sheet see Fig. 4 VCC = 3.0 V to 3.6 V [3] All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © ns Nexperia B.V. 2021. All rights reserved 5 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger Symbol Parameter -40 °C to +85 °C power dissipation per flip-flop; VI = GND to VCC capacitance VCC = 1.65 V to 1.95 V CPD [1] [2] [3] [4] Conditions -40 °C to +125 °C Min Typ [1] Max Min Max Unit [4] - 12.1 - - - pF VCC = 2.3 V to 2.7 V - 15.8 - - - pF VCC = 3.0 V to 3.6 V - 19.0 - - - pF Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. tpd is the same as tPLH and tPHL. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching 2 Σ(CL × VCC × fo) = sum of the outputs 10.1. Waveforms and test circuit 1/f max VI CP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna894 Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig. 4. Propagation delay clock (CP) to output (Qn), pulse width clock (CP), and maximum frequency tW VCC VM CP input GND tsu VCC tsu tsu VM E input GND th th VCC VM Dn input GND mna921 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 5. Data set-up and hold times of data input (Dn) and enable input (E) and pulse width of enable input (E) 74LVC377 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 6 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger Table 8. Measurement points Supply voltage Input Output VCC VM VM 1.2 V 0.5 × VCC 0.5 × VCC 1.65 V to 1.95V 0.5 × VCC 0.5 × VCC 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr VI tf 90 % positive pulse VM VM 10 % 0V tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig. 6. Test circuit for switching times Table 9. Test data Supply voltage Input Load VI tr, tf CL RL 1.2 V VCC ≤ 2 ns 30 pF 1 kΩ 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω 74LVC377 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 7 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger 11. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE v M A Z 20 11 Q A2 A (A 3 ) A1 pin 1 index θ Lp L 1 10 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 7. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT163-1 (SO20) 74LVC377 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 8 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm D SOT360-1 E A X c HE y v M A Z 11 20 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 Fig. 8. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Package outline SOT360-1 (TSSOP20) 74LVC377 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 9 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC377 v.7 20210827 Product data sheet - Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 updated. Type number 74LVC377DB (SOT339-1/SSOP20) removed. Section 7: Derating values for Ptot total power dissipation updated. 74LVC377 v.6 20121120 Modifications: • • • 74LVC377 v.6 Product data sheet - 74LVC377 v.5 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7, Table 8, and Table 9: values added for lower voltage ranges. 74LVC377 v.5 20050221 Product specification - 74LVC377 v.4 74LVC377 v.4 20040528 Product specification - 74LVC377 v.3 74LVC377 v.3 20021023 Product specification - 74LVC377 v.2 74LVC377 v.2 19980729 Product specification - 74LVC377 v.1 74LVC377 v.1 19990606 Product specification - - 74LVC377 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 10 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. 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Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 11 / 12 74LVC377 Nexperia Octal D-type flip-flop with data enable; positive-edge trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description............................................................. 2 6. Functional description................................................. 3 7. Limiting values............................................................. 3 8. Recommended operating conditions..........................3 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 5 10.1. Waveforms and test circuit........................................ 6 11. Package outline.......................................................... 8 12. Abbreviations............................................................ 10 13. Revision history........................................................10 14. Legal information......................................................11 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 27 August 2021 74LVC377 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 12 / 12