74AHCT574D,112

74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02 — 24 January 2008 Product data sheet 1. General description The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC574; 74AHCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74AHC574; 74AHCT574 is functionally identical to the 74AHC564; 74AHCT564, but has non-inverting outputs. The 74AHC574; 74AHCT574 is functionally identical to the 74AHC374; 74AHCT374, but has a different pinning. 2. Features n n n n n n n n n Balanced propagation delays All inputs have a Schmitt-trigger action 3-state non-inverting outputs for bus orientated applications 8-bit positive, edge-triggered register Independent register and 3-state buffer operation Common 3-state output enable input For 74AHC574 only: operates with CMOS input levels For 74AHCT574 only: operates with TTL input levels ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74AHC574D Temperature range Name Description Version −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm 74AHCT574D 74AHC574PW 74AHCT574PW 74AHC574BQ 74AHCT574BQ 4. Functional diagram 2 D0 Q0 19 3 D1 Q1 18 4 D2 5 D3 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 Q2 17 FF1 to FF8 Q3 16 3-STATE OUTPUTS Q4 15 11 CP 1 OE mna800 Fig 1. Functional diagram D0 D1 D Q D2 D CP Q D CP FF1 D3 Q D CP FF2 D4 Q D CP FF3 D5 Q D CP FF4 D6 Q D CP FF5 D7 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aah077 Fig 2. Logic diagram © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 2 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 11 1 C1 EN 11 2 3 4 5 6 7 8 9 2 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 19 3 18 17 4 17 16 5 16 15 6 15 7 14 8 13 9 12 18 14 13 12 OE 1 Fig 3. Logic symbol mna446 mna798 Fig 4. IEC logic symbol © 74AHC_AHCT574_2 Product data sheet 19 1D Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 3 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 5. Pinning information 5.1 Pinning 1 74AHC574 74AHCT574 OE 1 OE terminal 1 index area 20 VCC 20 VCC 74AHC574 74AHCT574 D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D0 2 19 Q0 D1 3 18 Q1 D3 5 16 Q3 D2 4 17 Q2 D4 6 15 Q4 D3 5 16 Q3 D5 7 14 Q5 D4 6 15 Q4 D6 8 D5 7 14 Q5 D7 9 13 Q6 D7 9 12 Q7 GND 10 11 CP 13 Q6 12 Q7 CP 11 8 GND 10 D6 GND(1) 001aah666 Transparent top view 001aah037 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO20, TSSOP20 Fig 6. Pin configuration DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 3-state output enable input (active LOW) D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) CP 11 clock input (LOW-to-HIGH, edge triggered) Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output VCC 20 supply voltage © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 4 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 6. Functional description Table 3. Function table[1] Operating mode OE CP Dn Internal flip-flop Load and read register L ↑ l L L L ↑ h H H Load register and disable output H ↑ l L Z H ↑ h H Z [1] Input Output Qn H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI Conditions Min Max Unit supply voltage −0.5 +7.0 V input voltage −0.5 +7.0 V −20 - mA - ±20 mA input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to (VCC + 0.5 V) - ±25 mA ICC supply current - 75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation IIK Tamb = −40 °C to +125 °C SO20 package [2] - 500 mW TSSOP20 package [3] - 500 mW DHVQFN20 package [4] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 °C. [3] Ptot derates linearly with 5.5 mW/K above 60 °C. [4] Ptot derates linearly with 4.5 mW/K above 60 °C. © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 5 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC574 Min Typ 74AHCT574 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V VI input voltage 0 - 5.5 0 - 5.5 V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.3 V ± 0.3 V - - 100 - - - ns/V VCC = 5.0 V ± 0.5 V - - 20 - - 20 ns/V 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = −8.0 mA; VCC = 4.5 V For type 74AHC574 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage 3.94 - - 3.8 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V - - ±0.25 - ±2.5 - ±10.0 µA II input leakage current - - 0.1 - 1.0 - 2.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA VI = 5.5 V or GND; VCC = 0 V to 5.5 V © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 6 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max CI input capacitance - 3.0 10 - 10 - 10 pF CO output capacitance - 4.0 - - - - - pF For type 74AHCT574 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.8 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V IO = −8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA IOZ OFF-state per input pin; VI = VIH or VIL; output current VCC = 5.5 V; IO = 0 A; VO = VCC or GND; other pins at VCC or GND - - ±0.25 - ±2.5 - ±10.0 µA II input leakage current - - 0.1 - 1.0 - 2.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA ∆ICC additional per input pin; supply current VI = VCC − 2.1 V; IO = 0 A; other pins at VCC or GND; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4.0 - - - - - pF VI = 5.5 V or GND; VCC = 0 V to 5.5 V © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 7 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. For test circuit see Figure 10. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 6.5 13.2 1.0 15.5 1.0 16.5 ns CL = 50 pF - 9.3 16.7 1.0 19.0 1.0 21.0 ns - 4.4 8.6 1.0 10.0 1.0 11.0 ns 6.2 10.6 1.0 12.0 1.0 13.5 ns For type 74AHC574 tpd propagation delay CP to Qn; see Figure 7 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF ten enable time OE to Qn; see Figure 9 [1] VCC = 3.0 V to 3.6 V CL = 15 pF - 5.7 12.8 1.0 15.0 1.0 16.0 ns CL = 50 pF - 8.2 16.3 1.0 18.5 1.0 20.5 ns - 4.2 9.0 1.0 10.5 1.0 11.5 ns - 5.9 11.0 1.0 12.5 1.0 14.0 ns CL = 15 pF - 6.3 13.0 1.0 15.0 1.0 16.5 ns CL = 50 pF - 9.1 15.0 1.0 17.0 1.0 19.0 ns CL = 15 pF - 4.3 9.0 1.0 10.5 1.0 11.5 ns CL = 50 pF - 6.9 10.1 1.0 11.5 1.0 13.0 ns CL = 15 pF 80 125 - 65 - 65 - MHz CL = 50 pF 50 75 - 45 - 45 - MHz CL = 15 pF 130 180 - 110 - 110 - MHz CL = 50 pF 85 115 - 75 - 75 - MHz VCC = 3.0 V to 3.6 V; CL = 50 pF 5.0 - - 5.0 - 5.0 - ns VCC = 4.5 V to 5.5 V; CL = 50 pF 5.0 - - 5.0 - 5.0 - ns VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tdis disable time OE to Qn; see Figure 9 [2] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum frequency CP; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW pulse width CP; HIGH or LOW; see Figure 7 © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 8 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Table 7. Dynamic characteristics …continued GND = 0 V. For test circuit see Figure 10. Symbol Parameter tsu th CPD set-up time hold time 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max VCC = 3.0 V to 3.6 V; CL = 50 pF 3.5 - - 3.5 - 3.5 - ns VCC = 4.5 V to 5.5 V; CL = 50 pF 3.0 - - 3.0 - 3.0 - ns VCC = 3.0 V to 3.6 V; CL = 50 pF 1.5 - - 1.5 - 1.5 - ns VCC = 4.5 V to 5.5 V; CL = 50 pF 1.5 - - 1.5 - 1.5 - ns - 10 - - - - - pF CL = 15 pF - 4.4 8.6 1.0 10.0 1.0 11.0 ns CL = 50 pF - 6.3 10.6 1.0 12.0 1.0 13.5 ns - 4.3 9.0 1.0 10.5 1.0 11.5 ns - 6.1 11.0 1.0 12.5 1.0 14.0 ns CL = 15 pF - 4.3 9.0 1.0 10.5 1.0 11.5 ns CL = 50 pF - 6.2 10.1 1.0 11.5 1.0 13.0 ns CL = 15 pF 130 180 - 110 - 110 - MHz CL = 50 pF 85 115 - 75 - 75 - MHz 5.0 - - 5.5 - 5.5 - ns 3.0 - - 3.5 - 3.5 - ns Dn to CP; see Figure 8 Dn to CP; see Figure 8 CL = 50 pF; fi = 1 MHz; power dissipation VI = GND to VCC capacitance [3] For type 74AHCT574 tpd ten propagation delay enable time CP to Qn; see Figure 7 [2] VCC = 4.5 V to 5.5 V OE to Qn; see Figure 9 VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF tdis disable time OE to Qn; see Figure 9 [2] VCC = 4.5 V to 5.5 V fmax tW maximum frequency pulse width CP; see Figure 7 VCC = 4.5 V to 5.5 V CP; HIGH or LOW; see Figure 7 VCC = 4.5 V to 5.5 V; CL = 50 pF tsu set-up time Dn to CP; see Figure 8 VCC = 4.5 V to 5.5 V; CL = 50 pF © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 9 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Table 7. Dynamic characteristics …continued GND = 0 V. For test circuit see Figure 10. Symbol Parameter th hold time 25 °C Conditions Min Max Min Max Min Max 1.5 - - 1.5 - 1.5 - ns - 12 - - - - - pF Dn to CP; see Figure 8 VCC = 4.5 V to 5.5 V; CL = 50 pF power per buffer; dissipation CL = 50 pF; f = 1 MHz; capacitance VI = GND to VCC CPD −40 °C to +85 °C −40 °C to +125 °C Unit Typ[1] [3] [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] CPD is used to determine the dynamic power dissipation PD (µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V. 10.1 Waveforms 1/fmax VI CP input VM GND tW t PHL t PLH VOH VM Qn output mna802 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay input (CP) to output (Qn), clock input (CP) pulse width and the maximum frequency (CP) © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 10 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state VI VM CP input GND t su t su th th VI VM Dn input GND VOH VM Qn output VOL mna803 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 8. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times VI OE input VM GND tPLZ tPZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY Qn output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled 001aah078 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Enable and disable times Table 8. Measurement points Type Input Output VM VM VX VY 74AHC574 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V 74AHCT574 1.5 V 0.5VCC VOL + 0.3 V VOH − 0.3 V © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 11 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC VI PULSE GENERATOR VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 10. Load circuitry for switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC574 VCC 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHCT574 3.0 V 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 12 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 11. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT163-1 (SO20) © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 13 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 12. Package outline SOT360-1 (TSSOP20) © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 14 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT764-1 (DHVQFN20) © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 15 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged-Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT574_2 20080124 Product data sheet - 74AHC_AHCT574_1 Modifications: 74AHC_AHCT574_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN20 package added. Section 7: derating values added for DHVQFN20 package. Section 11: outline drawing added for DHVQFN20 package. 19990616 Product specification - © 74AHC_AHCT574_2 Product data sheet - Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 16 of 18 74AHC574; 74AHCT574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Nexperia. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com © 74AHC_AHCT574_2 Product data sheet Rev. 02 — 24 January 2008 Nexperia B.V. 2017. All rights reserved 17 of 18 Nexperia 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state 16. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 14.1 14.2 14.3 14.4 15 16 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 24 January 2008