Product
Document
Published by
ams OSRAM Group
AS5043
Programmable 360° Magnetic Angle
Encoder with Absolute SSI and Analog
Outputs
General Description
The AS5043 is a contactless magnetic angle encoder for
accurate measurement up to 360°.
It is a system-on-chip, combining integrated Hall elements,
analog front end and digital signal processing in a single device.
The AS5043 provides a digital 10-bit as well as a programmable
analog output that is directly proportional to the angle of a
magnet, rotating over the chip.
The analog output can be configured in many ways, including
user programmable angular range, adjustable output voltage
range, voltage or current output, etc...
An internal voltage regulator allows operation of the AS5043
from 3.3V or 5.0V supplies.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS5043, Programmable 360°
Magnetic Angle Encoder with Absolute SSI and Analog Outputs
are listed below:
Figure 1:
Added Value of Using AS5043
Benefits
Features
• Highest reliability and durability
• Contactless high resolution rotational position
encoding over a full turn of 360 degrees
• Simple programming
• Simple user-programmable zero position
• Multiple interfaces
• Serial communication interface (SSI)
• Programmable 10-bit analog output
• Ideal for robotic and motor applications
• Input mode for optimizing noise vs. speed
• Failure diagnostics
• Failure detection mode for magnet placement
monitoring and loss of power supply
• Easy setup
• Serial read-out of multiple interconnected AS5043
devices using Daisy Chain mode
• Small form factor
• SSOP 16 (5.3mm x 6.2mm)
• Robust environmental tolerance
• Wide temperature range: -40°C to 125°C
ams Datasheet
[v1-83] 2017-Jul-18
Page 1
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AS5043 − General Description
Applications
AS5043, Programmable 360° Magnetic Angle Encoder with
Absolute SSI and Analog Outputs is ideal for applications with
an angular travel range from a few degrees up to a full turn of
360°, such as:
• Industrial applications:
• Contactless rotary position sensing
• Robotics
• Valve controls
• Automotive applications:
• Throttle position sensors
• Gas/brake pedal position sensing
• Headlight position control
• Front panel rotary switches
• Replacement of potentiometers
Figure 2:
Typical Arrangement of AS5043 and Magnet
Page 2
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ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 3:
AS5043 Block Diagram
MagRNGn
Mode
Sin
DSP
Hall Array
&
Frontend
Amplifier
Cos
DO
Absolute
Interface
(SSI)
CSn
CLK
OTP
Register
DACref
FB
10
Programming
Parameters
Vout
10bit
DAC
+
DACout
Prog_DI
ams Datasheet
[v1-83] 2017-Jul-18
Page 3
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AS5043 − Pin Assignment
Pin Assignment
Figure 4:
AS5043 Pin Configuration SSOP16
MagRngn
1
16
VDD5V
Mode
2
15
VDD3V3
CSn
3
14
NC
CLK
4
13
NC
NC
5
12
Vout
DO
6
11
FB
VSS
7
10
DACout
Prog_DI
8
9
DACref
Package = SSOP16 (16 lead Shrink Small Outline Package)
Figure 5:
Pin Description SSOP16
Pin
Symbol
Type
1
MagRngn
DO_OD
Magnet Field Magnitude RaNGe warning; active low, indicates
that the magnetic field strength is outside of the recommended
limits.
2
Mode
DI_PD, ST
Mode input. Select between low noise (low, connect to VSS) and
high speed (high, connect to VDD5V) mode at power up. Internal
pull-down resistor.
3
CSn
DI_PU, ST
Chip Select, active low; Schmitt-Trigger input, internal pull-up
resistor (~50kΩ)
4
CLK
DI,ST
5
NC
-
6
DO
DO_T
7
VSS
S
8
Prog_DI
DI_PD
9
DACref
AI
DAC Reference voltage input for external reference
10
DACout
AO
DAC output (unbuffered, Ri ~8kΩ)
11
FB
AI
Feedback, OPAMP inverting input
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Description
Clock Input of Synchronous Serial Interface; Schmitt-Trigger input
Must be left unconnected
Data Output of Synchronous Serial Interface
Negative Supply Voltage (GND)
OTP Programming Input and Data Input for Daisy Chain mode.
Internal pull-down resistor (~74kΩ).
Should be connected to VSS if programming is not used
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Pin Assignment
Pin
Symbol
Type
Description
12
Vout
AO
OPAMP output
13
NC
-
Must be left unconnected
14
NC
-
Must be left unconnected
15
VDD3V3
S
3V-Regulator Output for internal core, regulated from
VDD5V.Connect to VDD5V for 3V supply voltage. Do not load
externally.
16
VDD5V
S
Positive Supply Voltage, 3.0 to 5.5 V
Abbreviations for Pin Types in Figure 5:
DO_OD
: Digital output open drain
DI_PD
: Digital input pull-down
DI_PU
: Digital input pull-up
S
: Supply pin
DO_T
: Digital output /tri-state
ST
: Schmitt-Trigger input
AI
: Analog input
AO
: Analog output
D1
: Digital input
Pin Description
Pins 7, 15 and 16 are supply pins, pins 5, 13 and 14 are for
internal use and must be left open.
Pin 1 is the magnetic field strength indicator, MagRNGn. It is
an open-drain output that is pulled to VSS when the magnetic
field is out of the recommended range (45mT to 75mT). The chip
will still continue to operate, but with reduced performance,
when the magnetic field is out of range. When this pin is low,
the analog output at pins #10 and #12 will be 0V to indicate the
out-of-range condition.
Pin 2 MODE allows switching between filtered (slow) and
unfiltered (fast mode). This pin must be tied to VSS or VDD5V,
and must not be switched after power up.
Pin 3 Chip Select (CSn; active low) selects a device for serial
data transmission over the SSI interface. A “logic high” at CSn
forces output DO to digital tri-state.
Pin 4 CLK is the clock input for serial data transmission over the
SSI interface.
ams Datasheet
[v1-83] 2017-Jul-18
Page 5
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AS5043 − Pin Assignment
Pin 6 DO (Data Out) is the serial data output during data
transmission over the SSI interface.
Pin 8 PROG_DI is used to program the different operation
modes, as well as the zero-position in the OTP register.
This pin is also used as a digital input to shift serial data through
the device in Daisy Chain Mode.
Pin 9 DACref is the external voltage reference input for the
Digital-to-Analog Converter (DAC). If selected, the analog
output voltage on pin 12 (Vout) will be ratiometric to the voltage
on this pin.
Pin10 DACout is the unbuffered output of the DAC. This pin
may be used to connect an external OPAMP, etc. to the DAC.
Pin 11 FB (Feedback) is the inverting input of the OPAMP buffer
stage.
Access to this pin allows various OPAMP configurations.
Pin 12 Vout is the analog output pin. The analog output is a DC
voltage, ratiometric to VDD5V (3.0 – 5.5V) or an external voltage
source and proportional to the angle.
Page 6
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ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated in Operating
Conditions is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 6:
Absolute Maximum Ratings
Symbol
VDD5V
VDD3V3
Vin
Parameter
DC supply voltage at pin
VDD5V
Input pin voltage
Iscr
Input current
(latchup immunity)
ESD
Electrostatic discharge
Tstrg
Storage temperature
TBody
Body temperature
RHNC
Relative humidity
(non condensing)
MSL
Moisture sensitivity level
ams Datasheet
[v1-83] 2017-Jul-18
Min
Max
Units
-0.3
7
V
Pin VDD5V
5
V
Pin VDD3V3
-0.3
VDD5V +0.3
-0.3
5
-0.3
7.5
-100
100
5
3
Pins MagRngn, Mode, CSn, CLK,
DO, DACout, FB, Vout
V
Pin DACref
Pin PROG_DI
mA
JEDEC 78
kV
MIL 883 E method 3015
125
ºC
Min – 67°F; Max 257°F
260
ºC
t=20s to 40s, IPC/JEDEC
J-Std-020C
Lead finish 100% Sn “matte tin”
85
%
±2
-55
Note
Maximum floor life time of 168h
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AS5043 − Electrical Characteristics
Electrical Characteristics
Operating Conditions
Figure 7:
Operating Conditions
Symbol
Parameter
Min
Tamb
Ambient temperature
-40
Isupp
Supply current
VDD5V
Supply voltage at pin VDD5V
Typ
Max
Unit
125
°C
16
21
mA
4.5
5.0
5.5
V
Note
-40°F to 257°F
5V operation
VDD3V3
Voltage regulator output
voltage at pin VDD3V3
3.0
3.3
3.6
V
VDD5V
Supply voltage at pin VDD5V
3.0
3.3
3.6
V
VDD3V3
Supply voltage at pin VDD3V3
3.0
3.3
3.6
V
3.3V operation (pins VDD5V
and VDD3V3 connected)
DC Characteristics for Digital Inputs and
Outputs
CMOS Schmitt-Trigger Inputs: CLK, CSn (Internal
Pull-Up), Mode (Internal Pull-Down)
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted)
Figure 8:
CMOS Schmitt-Trigger Inputs: CLK, CSn (CSn = Internal Pull-Up), Mode (Internal Pull-Down)
Symbol
Parameter
VIH
High level input voltage
VIL
Low level input voltage
VIon-VIoff
ILEAK
IiL
IiH
Min
Max
0.7 * VDD5V
V
0.3 * VDD5V
Schmitt Trigger hysteresis
1
Input leakage current
-1
1
-30
30
-100
100
Page 8
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Note
Normal operation
V
V
Pull-up low level input current
Pull-down high level input
current
Unit
Pin CLK,
VDD5V = 5.0V
μA
Pin CSn,
VDD5V= 5.0V
Pin Mode,
VDD5V= 5.0V
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Electrical Characteristics
CMOS Input: Program Input (Prog)
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted)
Figure 9:
CMOS Input: Program Input (Prog)
Symbol
Parameter
VIH
High level input voltage
VPROG
High level input voltage
VIL
Low level input voltage
IiL
Pull-down high level input
current
Min
Max
Unit
0.7 * VDD5V
5
V
See Programming
Conditions
V
0.3 * VDD5V
V
100
μA
Note
During
programming
VDD5V: 5.5V
CMOS Output Open Drain: MagRngn
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 10:
CMOS Output Open Drain: MagRngn
Symbol
VOL
Parameter
Low level output voltage
Min
Max
Unit
VSS+0.4
V
IO
Output current
4
2
mA
IOZ
Open drain leakage current
1
μA
ams Datasheet
[v1-83] 2017-Jul-18
Note
VDD5V: 4.5V
VDD5V: 3V
Page 9
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AS5043 − Electrical Characteristics
Tristate CMOS Output: DO
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 11:
Tristate CMOS Output: DO
Symbol
Parameter
VOH
High level output voltage
VOL
Low level output voltage
Min
Max
VDD5V-0.5
Unit
Note
V
VSS+0.4
V
IO
Output current
4
2
mA
IOZ
Tri-state leakage current
1
μA
VDD5V: 4.5V
VDD5V: 3V
Digital-to-Analog Converter
Figure 12:
Digital-to-Analog Converter
Symbol
Parameter
Min
Resolution
VOUTM1
Output range
VOUTM2
ROut,DAC
Vref
Max
10
Unit
Note
bit
Vref
V
0% …100% Vref
(default)
ClampMdEn = 0
(default)
0.10
*Vref
0.90
*Vref
V
10% …90% Vref
ClampMdEn = 1
8
kΩ
Unbuffered Pin
DACout (#10)
VDD3V3
- 0.2
V
DAC reference =
external: Pin:
DACref (#9)
RefExt EN = 1
VDD5V /
2
V
DAC reference =
internal
RefExtEn = 0 (default)
0.2
INLDAC
Integral
non-linearity
±1.5
LSB
DNLDAC
Differential
non-linearity
±0.5
LSB
1
LSB
All analog modes
2
LSB
At 360°-0°
transition, 360°
mode only
Hyst
Analog
output
hysteresis
Page 10
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OTP Setting
0
Output
resistance
DAC
reference
voltage (DAC
full scale
range)
Typ
Non-Linearity of
DAC and OPAMP;
-40°C to 125°C,
for all analog
modes: 1LSB =
Vref / 1024
OR1,OR0 = 00 (default)
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Electrical Characteristics
OPAMP Output Stage
Figure 13:
OPAMP Output Stage
Symbol
Parameter
Min
VDD5V
Power Supply
Range
3.0
CL
Parallel Load
Capacitance
RL
Parallel Load
Resistance
4.7
A0
Open Loop Gain
92
VosOP
Offset Voltage RTI
-5
VoutL
Output Range Low
Typ
Max
Unit
5.5
V
100
pF
kΩ
130
144
dB
5
mV
0.05 *
VDD5V
V
Note
3.3V operation
3 sigma
Linear range of analog
output
VoutH
Output Range High
0.95 *
VDD5V
Isink
Current capability
sink
4.8
50
mA
Permanent short circuit
current: Vout to VDD5V
Isource
Current capability
source
4.6
66
mA
Permanent short circuit
current: Vout to VSS
Vnoise
Output noise
160
V
220
490
2
Gain
ams Datasheet
[v1-83] 2017-Jul-18
OPAMP gain
(non-inverting)
1
μVrms
Over full temperature
range;
BW= 1Hz …10MHz,
Gain = 2x
Internal; OTP: FB_int EN = 1
4
External OTP: FB_int EN = 0
(default) With external
resistors, pins Vout [#12]
and FB [#11]:
see Figure 33
Page 11
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AS5043 − Electrical Characteristics
Magnetic Input Specification
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Two-pole cylindrical diametrically magnetized source:
Figure 14:
Magnetic Input Specification
Symbol
Parameter
Min
Typ
6
dmag
Diameter
4
tmag
Thickness
2.5
Bpk
Magnetic input
field amplitude
Boff
Magnetic offset
45
fmag_abs
Disp
Input frequency
(rotational speed
of magnet)
Displacement
radius
Recommended
magnet material
and temperature
drift
Page 12
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Unit
mm
mm
Field non-linearity
fmag_inc
Max
Note
Recommended magnet: Ø 6mm x
2.5mm for cylindrical magnets
75
mT
Required vertical component of the
magnetic field strength on the die’s
surface, measured along a concentric
circle with a radius of 1.1mm
± 10
mT
Constant magnetic stray field
5
%
Including offset gradient
10
Hz
Absolute mode: 600 rpm @ readout of
1024 positions (see Figure 48)
166
Hz
Incremental mode: no missing pulses
at rotational speeds of up to 10,000
rpm (see Figure 48)
0.25
mm
Max. offset between defined device
center and magnet axis
-0.12
NdFeB (Neodymium Iron Boron)
%/K
-0.035
SmCo (Samarium Cobalt)
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Electrical Characteristics
Electrical System Specifications
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 15:
Electrical System Specifications
Symbol
RES
Parameter
Min
Typ
Resolution (1)
INLopt
Integral non-linearity
(optimum)(1)
INLtemp
Integral non-linearity
(optimum) (1)
INL
Integral non-linearity (1)
DNL
Differential non-linearity (1)
Max
Unit
10
bit
0.352 deg
deg
Maximum error with respect to
the best line fit. Verified at
optimum magnet placement,
Tamb =25 °C.
deg
Maximum error with respect to
the best line fit. Verified at
optimum magnet placement,
Tamb = -40°C to 125°C
± 1.4
deg
Best line fit = (Errmax – Errmin) /
2 Over displacement tolerance
with 6mm diameter magnet,
Tamb = -40°C to 125°C
± 0.176
deg
10bit, no missing codes
± 0.5
± 0.9
0.06
TN
deg
RMS
Transition noise (1)
0.03
Note
1 sigma, fast mode
(pin MODE = 1)
1 sigma, slow mode (pin
MODE=0 or open)
Von
Power-ON reset threshold
ON voltage; 300mV typ.
hysteresis
1.37
2.2
2.9
V
DC supply voltage 3.3V
(VDD3V3)
Voff
Power-ON reset threshold
OFF voltage; 300mV typ.
hysteresis
1.08
1.9
2.6
V
DC supply voltage 3.3V
(VDD3V3)
tPwrUp
Power-up time,
Until offset compensation
finished, OCF = 1, Angular
Data valid
tdelay
System propagation delay
absolute output : delay of
ADC and DSP
ams Datasheet
[v1-83] 2017-Jul-18
20
Fast mode (pin MODE=1)
ms
80
Slow mode (pin MODE=0 or
open)
96
Fast mode (pin MODE=1)
μs
384
Slow mode (pin MODE=0 or
open)
Page 13
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AS5043 − Electrical Characteristics
Symbol
fS, mode 0
fS, mode 1
CLK
Parameter
Min
Typ
Max
2.48
2.61
2.74
Internal sampling rate for
absolute output
Note
Tamb = 25°C, slow mode (pin
MODE = 0 or open)
kHz
2.35
2.61
2.87
Tamb = -40°C to 125°C, slow
mode (pin MODE = 0 or open)
9.90
10.4
2
10.94
Tamb = 25°C, fast mode (pin
MODE = 1)
9.38
10.4
2
Internal sampling rate for
absolute output
Read-out frequency
Unit
kHz
>0
Tamb = -40°C to 125°C, fast
mode (pin MODE = 1)
11.46
1
MHz
Max. clock frequency to read
out serial data
Note(s) and/or Footnote(s):
1. Digital interface
Figure 16:
Integral and Differential Non-Linearity Example (exaggerated curve)
1023
D 10bit code
1023
Actual curve
2
TN
1
0
512
Ideal curve
DNL+1LSB
INL
0.35°
512
0
0q
q
360 q
D [degrees]
Integral Non-Linearity (INL) is the maximum deviation between
actual position and indicated position.
Differential Non-Linearity (DNL) is the maximum deviation of
the step length from one position to the next.
Transition Noise (TN) is the repeatability of an indicated
position.
Page 14
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ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Electrical Characteristics
Timing Characteristics
Synchronous Serial Interface (SSI)
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 17:
Synchronous Serial Interface (SSI)
Symbol
Parameter
t DO active
Data output activated
(logic high)
tCLK FE
First data shifted to
output register
T CLK / 2
Start of data output
t DO valid
Data output valid
t DO tristate
Data output tristate
t CSn
Pulse width of CSn
fCLK
Read-out frequency
ams Datasheet
[v1-83] 2017-Jul-18
Min
Typ
Max
Unit
100
ns
Time between falling edge of CSn
and data output activated
500
ns
Time between falling edge of CSn
and first falling edge of CLK
500
ns
Rising edge of CLK shifts out one bit
at a time
413
ns
Time between rising edge of CLK
and data output valid
100
ns
After the last bit DO changes back to
“tristate”
ns
CSn = high; To initiate read-out of
next angular position
MHz
Clock frequency to read out serial
data
500
>0
1
Note
Page 15
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AS5043 − Electrical Characteristics
Programming Conditions
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 18:
Programming Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Note
Time between rising edge at
Prog pin and rising edge of CSn
Programming enable
time
2
μs
t Data in
Write data start
2
μs
t Data in valid
Write data valid
250
ns
t Load PROG
Load programming
data
3
μs
t PrgR
Rise time of VPROG
before CLKPROG
0
μs
t PrgH
Hold time of VPROG
after CLKPROG
0
t Prog enable
CLK PROG
t PROG
t PROG finished
Write data –
programming CLKPROG
CLK pulse width
Hold time of VPROG
after programming
1.8
2
Write data at the rising edge of
CLKPROG
5
μs
250
kHz
2.2
μs
During programming; 16 clock
cycles
μs
Programmed data is available
after next power-on
7.5
V
Must be switched OFF after
zapping
1
V
Line must be discharged to this
level
2
V PROG
Programming voltage
7.3
V ProgOff
Programming voltage
OFF level
0
I PROG
Programming current
130
mA
During programming
Analog read CLK
100
kHz
Analog readback mode
Programmed Zener
voltage (log.1)
100
mV
VRef-VPROG during analog
readback mode (see Analog
Readback Mode)
CLKAread
Vprogrammed
Vunprogrammed
Unprogrammed Zener
voltage (log. 0)
Page 16
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1
7.4
V
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Functional Description
Functional Description
The AS5043 is manufactured in a CMOS standard process and
uses a spinning current Hall technology for sensing the
magnetic field distribution across the surface of the chip.
The integrated Hall elements are placed in a circle around the
center of the device and deliver a voltage representation of the
magnetic field perpendicular to the surface of the IC.
Through Sigma-Delta Analog / Digital Conversion and Digital
Signal-Processing (DSP) algorithms, the AS5043 provides
accurate high-resolution absolute angular position
information. For this purpose a Coordinate Rotation Digital
Computer (CORDIC) calculates the angle and the magnitude of
the Hall array signals.
The DSP is also used indicate movements of the magnet
towards or away from the chip and to indicate, when the
magnetic field is outside of the recommended range
(status bits = MagInc, MagDec; hardware pin = MagRngn).
A small low cost diametrically magnetized (two-pole) standard
magnet, centered over the chip, is used as the input device.
The AS5043 senses the orientation of the magnetic field and
calculates a 10-bit binary code. This code can be accessed via a
Synchronous Serial Interface (SSI). In addition, the absolute
angular representation is converted to an analog signal,
ratiometric to the supply voltage.
The analog output can be configured in many ways, such as
360°/180°/90° or 45° angular range, external or internal DAC
reference voltage, 0-100%*VDD or 10-90% *VDD analog output
range, external or internal amplifier gain setting.
The various output modes as well as a user programmable zero
position can be programmed in an OTP register. As long as no
programming voltage is applied to pin PROG, the new setting
may be overwritten at any time and will be reset to default when
power is cycled. To make the setting permanent, the OTP
register must be programmed by applying a programming
voltage.
The AS5043 is tolerant to magnet misalignment and unwanted
external magnetic fields due to differential measurement
technique and Hall sensor conditioning circuitry.
It is also tolerant to airgap and temperature variations due to
Sin-/Cos- signal evaluation.
ams Datasheet
[v1-83] 2017-Jul-18
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AS5043 − 3.3V / 5V Operation
3.3V / 5V Operation
The AS5043 operates either at 3.3V ±10% or at 5V ±10%. This is
made possible by an internal 3.3V Low-Dropout (LDO) Voltage
regulator. The core supply voltage is always taken from the LDO
output, as the internal blocks are always operating at 3.3V.
For 3.3V operation, the LDO must be bypassed by connecting
VDD3V3 with VDD5V (see Figure 19).
For 5V operation, the 5V supply is connected to pin VDD5V,
while VDD3V3 (LDO output) must be buffered by a 1 to10μF
capacitor, which should be placed close to the supply pin.
The VDD3V3 output is intended for internal use only. It should
not be loaded with an external load.
The voltage levels of the digital interface I/O’s correspond to
the voltage at pin VDD5V, as the I/O buffers are supplied from
this pin (see Figure 19).
Figure 19:
Connections for 5V / 3.3V Supply Voltages
A buffer capacitor of 100nF is recommended in both cases close
to pin VDD5V. Note that pin VDD3V3 must always be buffered
by a capacitor. It must not be left floating, as this may cause an
instable internal 3.3V supply voltage which may lead to larger
than normal jitter of the measured angle.
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ams Datasheet
[v1-83] 2017-Jul-18
10-Bit Absolute Synchronous
Serial Interface (SSI)
The serial data transmission timing is outlined in Figure 21: if
CSn changes to logic low, Data Out (DO) will change from high
impedance (tri-state) to logic high and the read-out sequence
will be initiated. After a minimum time t CLK FE, data is latched
into the output shift register with the first falling edge of CLK.
Each subsequent rising CLK edge shifts out one bit of data.The
serial word contains 16 bits, the first 10 bits are the angular
information D[9:0], the subsequent 6 bits contain system
information, about the validity of data such as OCF, COF, LIN,
Parity and Magnetic Field status (increase / decrease /
out of range).
A subsequent measurement is initiated by a logic “high” pulse
at CSn with a minimum duration of t CSn. Data transmission
may be terminated at any time by pulling CSn = high.
Serial Data Contents
D9:D0 absolute angular position data (MSB is clocked out first).
OCF (Offset Compensation Finished), logic high indicates that
the Offset Compensation Algorithm has finished and data is
valid.
COF (CORDIC Overflow), logic high indicates an out of range
error in the CORDIC part. When this bit is set, the data at D9:D0
is invalid. The absolute output maintains the last valid angular
value. This alarm may be resolved by bringing the magnet
within the X-Y-Z tolerance limits.
LIN (Linearity Alarm), logic high indicates that the input field
generates a critical output linearity. When this bit is set, the data
at D9:D0 may still be used, but may contain invalid data. This
warning may be resolved by bringing the magnet within the
X-Y-Z tolerance limits.
Data D9:D0 is valid, when the status bits have the following
configurations:
Figure 20:
Status Bit Outputs
OCF
1
COF
0
ams Datasheet
[v1-83] 2017-Jul-18
LIN
0
Mag INC
Mag DEC
0
0
0
1
1
0
Parity
Even checksum of bits 1:15
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AS5043 − 10-Bit Absolute Synchronous Serial Inter face (SSI)
MagInc, (Magnitude Increase) becomes HIGH, when the
magnet is pushed towards the IC, thus the magnetic field
strength is increasing.
MagDec, (Magnitude Decrease) becomes HIGH, when the
magnet is pulled away from the IC, thus the magnetic field
strength is decreasing.
Both signals HIGH indicate a magnetic field that is out of the
allowed range (see Figure 22).
Note(s): Pin 1 (MagRngn) is a combination of MagInc and
MagDec. It is active low via an open drain output and requires
an external pull-up resistor. If the magnetic field is in range, this
output is turned OFF. (logic “high”).
Even Parity bit for transmission error detection of bits 1 …15
(D9 …D0, OCF, COF, LIN, MagInc, MagDec)
The absolute angular output is always set to a resolution of 10
bit / 360°. Placing the magnet above the chip, angular values
increase in clockwise direction by default.
Figure 21:
Synchronous Serial Interface with Absolute Angular Position Data
CSn
t CLK FE
T CLK / 2
t CSn
1
CLK
DO
D9
t DO active
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t DO valid
8
D8
D7
D6
D5
D4
D3
Angular Position Data
D2
1
16
D1
D0
OCF
COF
LIN
Mag
INC
Status Bits
Mag
DEC
t CLK FE
Even
PAR
D9
t DO Tristate
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − 10-Bit Absolute Synchronous Serial Interface (SSI)
Z-Axis Range Indication (Push Button Feature,
Red/Yellow/Green Indicator)
The AS5043 provides several options of detecting movement
and distance of the magnet in the vertical (Z-) direction. Signal
indicators MagINC, MagDEC and LIN are available as status bits
in the serial data stream, while MagRngn is an open-drain
output that indicates an out-of range status (On in YELLOW or
RED range). Additionally, the analog output provides a safety
feature in the form that it will be turned OFF when the magnetic
field is too strong or too weak (RED range). The serial data is
always available, the red/yellow/green status is indicated by the
status bits as shown below:
Figure 22:
Magnetic Field Strength Indicators
SSI Status Bits
Hardware Pins
Description
Mag
INC
Mag
DEC
LIN
Mag
Rngn
Analog
Output
0
0
0
OFF
Enabled
No distance change
Magnetic Input Field OK (GREEN range,
~45mT … 75mT)
0
1
0
OFF
Enabled
Distance increase, GREEN range; Pull-function. This
state is dynamic and only active while the magnet is
moving away from the chip.
1
0
0
OFF
Enabled
Distance decrease, GREEN range; Push- function. This
state is dynamic and only active while the magnet is
moving towards the chip.
1
1
0
ON
Enabled
YELLOW Range: Magnetic field is ~ 25mT …45mT or
~75mT …135mT. The AS5043 may still be operated in
this range, but with slightly reduced accuracy.
Disabled
RED Range: Magnetic field is ~~135mT. The
analog output will be turned OFF in this range by
default. It can be enabled permanently by OTP
programming (see Diagnostic Output Mode).
It is still possible to use the absolute serial interface in
the red range, but not recommended.
1
1
ams Datasheet
[v1-83] 2017-Jul-18
1
ON
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AS5043 − Mode Input Pin
Mode Input Pin
The absolute angular position is sampled at a rate of 10.4kHz
(t=96μs) in fast mode and at a rate of 2.6kHz (t=384μs) in slow
mode.
These modes are selected by pin MODE (#2) during the power
up of the AS5043. This pin activates or deactivates an internal
filter, which is used to reduce the digital jitter and consequently
the analog output noise.
Activating the filter by pulling Mode = LOW reduces the
transition noise to 90% VDD(2)
SSI Digital Output
#0 - #1023 (0°-360°), MagRngn = 1
#0 - #1023 (0°-360°)
Out of range is signaled in status bits:
MagInc=MagDec=LIN=1, MagRngn= 0
With pull down resistor at DO (receiving
side), all bits read by the SSI will be “0”-s,
indicating a non-valid output
Note(s) and/or Footnote(s):
1. Vref = internal: ½ * VDD5V (pin #16) or external: V DACref (pin#9), depending on Ref_extEN bit in OTP (0=int., 1=ext.).
2. VDD = positive supply voltage at receiving side (3.0 – 5.5V).
ams Datasheet
[v1-83] 2017-Jul-18
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AS5043 − Programming the AS5043
Programming the AS5043
After power-on, programming the AS5043 is enabled with the
rising edge of CSn and Prog = logic high. 16 bit configuration
data must be serially shifted into the OTP register via the
Prog-pin. The first “CCW” bit is followed by the zero position
data (MSB first) and the Analog Output Mode setting as shown
in Figure 38. Data must be valid at the rising edge of CLK (see
Figure 29). Following this sequence, the voltage at pin Prog
must be raised to the programming voltage V PROG (see
Figure 29). 16 CLK pulses (t PROG) must be applied to program
the fuses. To exit the programming mode, the chip must be reset
by a power-on-reset. The programmed data is available after
the next power-up.
Note(s): During the programming process, the transitions in
the programming current may cause high voltage spikes
generated by the inductance of the connection cable. To avoid
these spikes and possible damage to the IC, the connection
wires, especially the signals PROG and VSS must be kept as short
as possible. The maximum wire length between the VPROG
switching transistor and pin PROG (see Figure 31) should not
exceed 50mm (2 inches).
To suppress eventual voltage spikes, a 10nF ceramic capacitor
should be connected close to pins PROG and VSS. This capacitor
is only required for programming, it is not required for normal
operation. The clock timing t clk must be selected at a proper
rate to ensure that the signal PROG is stable at the rising edge
of CLK (see Figure 29). Additionally, the programming supply
voltage should be buffered with a 10μF capacitor mounted
close to the switching transistor. This capacitor aids in providing
peak currents during programming. The specified
programming voltage at pin PROG is 7.3 –7.5V (see
Programming Conditions). To compensate for the voltage drop
across the V PROG switching transistor, the applied programming
voltage may be set slightly higher (7.5 - 8.0V, see Figure 31).
OTP Register Contents:
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CCW
Counter Clockwise Bit
• ccw=0 – angular value increases in
clockwise direction
• ccw=1 – angular value increases in
counterclockwise direction
Z [9:0]
Programmable Zero / Index Position
FB_intEN
OPAMP gain setting: 0=external, 1=internal
RefExtEN
DAC reference: 0=internal, 1=external
ClampMd EN
Analog output span: 0=0-100%,
1=10-90%*VDD
Output Range
(OR0, OR1)
[1:0]
Analog Output Range Selection
00 = 360°; 01 = 180°; 10 = 90°; 11 = 45°
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Programming the AS5043
Figure 29:
Programming Access – OTP Write Cycle
CSn
tDatain
Prog
CCW
Z9
Z8
Z7
Z6
Z5
1
CLKPROG
tProg enable
Z4
Z3
Z2
Z1
Z0
FB_int
EN
RefExt
EN
Clamp
Md En
Output
Range1
Output
Range0
8
tDatain valid
16
tclk
see text
Analog Modes
Zero Position
Figure 30:
Complete OTP Programming Sequence
Write Data
Programming Mode
Power Off
CSn
Prog
7.5V
VDD
VProgOff
0V
Data
1
16
CLKPROG
tLoad PROG
ams Datasheet
[v1-83] 2017-Jul-18
tPrgH
tPrgR
tPROG
tPROG finished
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AS5043 − Programming the AS5043
USB
Figure 31:
OTP Programming Hardware Connection of AS5043 (shown with AS5043 demoboard)
Zero Position Programming
The AS5043 allows easy assembly of the system, as the actual
angle of the magnet does not need to be considered. By OTP
programming, any position can be assigned as the new
permanent zero position with an accuracy of 0.35° (all modes).
Using the same procedure, the AS5043 can be calibrated to
assign a given output voltage to a given angle. With this
approach, all offset errors (DAC + OPAMP) are also compensated
for the calibrated position.
Essentially, for a given mechanical position, the angular
measurement system is electrically rotated (by changing the
Zero Position value in the OTP register), until the output
matches the desired mechanical position.
The example in Figure 32 below shows a configuration for 5V
supply voltage and 10%-90% output voltage range. It adjusted
by Zero Position Programming to provide an analog output
voltage of 2.0 Volts at an angle of 180°. The slope of the curve
may be further adjusted by changing the gain of the OPAMP
output stage and by selecting the desired angular range
(360°/180°/90°/45°).
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ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Programming the AS5043
Figure 32:
Zero Position Programming (shown for 360° mode)
VDD5V
5V
analog
output
voltage
the output can be electrically rotated to
match a given output voltage to any
mechanical position
2V
0V
0°
90°
180°
270°
Mechanical
360° angle
Analog Mode Programming
The analog output can be configured in many ways: It consists
of three major building blocks,
• A digital range preselector,
• A 10-bit Digital-to-Analog-Converter (DAC),
• An OP-AMP buffer stage.
In the default configuration (all OTP bits = 0), the analog
output is set for 360° operation, internal DAC reference
(VDD5V/2), external OPAMP gain, 0-100% ratiometric to VDD5V.
Shown below is a typical example for a 0°-360° range, 0-5V
output. The complete application requires only one external
component, a buffer capacitor at VDD3V3 and has only 3
connections VDD, VSS and Vout (connectors 1-3).
Note(s): The default setting for the OPAMP feedback path
is:FB_intEn=0=external. The external resistors Rf and Rg must be
installed. In the programmed state (FB_intEn=1=internal), these
resistors do not need to be installed as the feedback path is internal
(Rf_int and Rg_int).
ams Datasheet
[v1-83] 2017-Jul-18
Page 31
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AS5043 − Programming the AS5043
Figure 33:
Analog Output Block Diagram
Magnetic field range alarm. Active
lo . Leave open or connect to
VSS if not used
Mode pin.
Default = open
( low noise)
1
AS 5043
External DAC reference pin.
Leave open or connect to
VSS if not used
VDD5V
15
LDO
3.3V
REF_extEN
VDD3V3
+
1=ext
0
0
1
1
OR1
fro
DSP
360°
180°
90°
45°
1-10µF
VDD5 V / 2
0
1
0
1
0=int
10
Vref
OR0
Range
Selector
VDD
Connect pins 15 and
16 for VDD= 3.0-3.6V .
Do NOT connect for
VDD = 4. 5-5.5V !
16
DACref
Mode
MagRng
1
9
2
10bit
digital
DAC
DACout
0 - 100% VDD5V /2
10bit
analog
+
VOUT
-
ClampMdEN
DAC output pin.
Leave open if not used
0=ext
0= 0-100% * Vref (def.)
1= 10-9 0% * Vref
FB_intEN
Vout
12
Rf_int
30k
2
Rf
RLmin
= 4k7
CL
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