CMV50000-1E4M1PA

Product Document Published by ams OSRAM Group Datasheet DS000522 CMV50000 47.5MP CMOS Machine Vision Image Sensor v3-01 • 2019-Dec-20 Document Feedback CMV50000 Content Guide Content Guide 1 General Description....................... 3 7.8 Additional Features .................................... 92 1.1 1.2 1.3 Key Benefits & Features .............................. 3 Applications .................................................. 4 Block Diagram .............................................. 4 8 Register Description ................. 102 8.1 8.2 Register Overview .................................... 102 Detailed Register Description .................. 106 2 Ordering Information ..................... 5 9 Application Information ............ 130 3 Pin Assignment ............................. 6 3.1 3.2 Pin Diagram .................................................. 6 Pin Description ............................................. 6 9.1 9.2 9.3 Color Filter ................................................ 130 Socket ...................................................... 130 Pin Layout ................................................ 131 4 Absolute Maximum Ratings ........ 11 10 Package Drawings & Markings. 132 5 Electrical Characteristics ............ 12 11 Packing Information .................. 135 6 Typical Operating Characteristics ............................. 14 12 Soldering Information ............... 136 13 Revision Information ................. 137 6.1 6.2 Electro-Optical Characteristics ................... 14 Spectral Characteristics ............................. 16 14 Legal Information ...................... 138 7 Functional Description ................ 19 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Sensor Architecture .................................... 19 Operating the Sensor ................................. 22 Sensor Readout Format ............................. 49 Configuring the Sensor .............................. 57 Configuring Readout and Exposure ........... 73 Configuring the Output Data Format .......... 85 Configuring the On-Chip Data Processing . 89 Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 2 Document Feedback 1 CMV50000 General Description General Description The CMV50000 is a high speed CMOS image sensor with 7920 × 6004 effective pixels (47.5Mp) developed for machine vision and video applications. The image array consists of 4.6µm pipelined 8T global shutter pixels which allow exposure during read out, while performing true CDS (Correlated Double Sampling) operation. The image sensor also integrates a programmable analog gain amplifier and offset regulation. The image sensor has 22 digital sub-LVDS data output channels. Each output channel runs up to 830 Mbit/s, which results in a frame rate of 30 fps at full resolution. Higher frame rates can be achieved in row-windowing mode or row-subsampling mode. These modes are all programmable using the SPI interface. All internal exposure and read out timings are generated by a programmable on-chip sequencer. External triggering and exposure programming is also possible. Extended optical dynamic range can be achieved by a dual exposure HDR mode. 1.1 Key Benefits & Features The benefits and features of CMV50000, 47.5MP CMOS Machine Vision Image Sensor, are listed below: Figure 1: Added Value of Using CMV50000 Benefits Features Designed for high performance applications Resolution of 7920x6004 at 30 frames per second Capture fast moving objects 8T global shutter pixel with true Correlated Double Sampling (true-CDS) Use in low light conditions Low noise (8.8e) and high sensitivity (QE=60%), with on-chip noise reduction. Use in bright light conditions In binning mode the full well capacity reaches 58000e- with an SNR of 47.6dB and DR=68dB Standard optics can be used 35mm Full Frame optical format Easy to operate On-chip digital sequencer which handles all the sensor controls, over SPI Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 3 Document Feedback 1.2 Applications ● ● ● ● ● 1.3 CMV50000 General Description ● ● ● ● Machine vision Video/Broadcast Security High-end inspection Aerial mapping Document scanning ITS Scientific 3D imaging Block Diagram The functional blocks of this device are shown below: Figure 2 : Functional Blocks of CMV50000 98 OB + 22 buffer pixels SPI, sensor control CLK in Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 98 OB + 22 buffer pixels AFE AFE ... AFE AFE ADC ADC ... ADC ADC DPP DPP DPP DPP sLVDS sLVDS sLVDS sLVDS sLVDS sLVDS CTR_OUT channel OBL _OUT channel OBR_OUT channel CLK_OUT channel Digital sequencer Thermal sensor Pixel array 7920 x 6004 (effective) active pixels PLL ... 22 DATAx_OUT channels 138 │ 4 Document Feedback 2 CMV50000 Ordering Information Ordering Information Ordering Code Package Chroma CMV50000-1E3M1PA PGA Mono 10 Pcs / Tray CMV50000-1E3C1PA PGA Color 10 Pcs / Tray CMV50000-1E3M1PN PGA Mono Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 Options windowless Delivery Quantity 10 Pcs / Tray 138 │ 5 Document Feedback 3 Pin Assignment 3.1 Pin Diagram CMV50000 Pin Assignment Figure 3 : Pin Numbering (bottom view) 3.2 Pin Description Figure 4: Pin Description of CMV50000 Pin Number Pin Name Pin Type Description A2 SPI_CSN Digital input SPI Chip Select A3 VSSA Analog ground Analog ground A5 REQ_FRAME Digital input Request frame (stop exposure) A6 VDDARRAY Analog supply Pixel array supply A7 VDDARRAY Analog supply Pixel array supply A8 NC1 Analog Do Not Connect Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 6 Document Feedback CMV50000 Pin Assignment Pin Number Pin Name Pin Type Description A9 NC2 Analog Do Not Connect A10 CTRL_P sub-LVDS Control channel output A11 CTRL_N sub-LVDS Control channel output A13 VSSA Analog ground Main analog ground A14 DOBL_P sub-LVDS Left Optical Black output A15 DOBL_N sub-LVDS Left Optical Black output B1 SPI_MISO Digital output SPI Master In/Slave Out data B2 SPI_MOSI Digital input SPI Master Out/Slave In data B3 SPI_CLK Digital input SPI clock B4 CLK_IN Digital input Sensor input clock B5 RST_N Digital input Asynchronous hard reset input pin B6 VDD33 Analog supply On-chip regulators supply B7 VSELHREG Analog On-chip regulator output B8 VS2HREG Analog On-chip regulator output B9 VS1HREG Analog On-chip regulator output B10 VTXHREG Analog On-chip regulator output B11 VRESHREG Analog On-chip regulator output B12 VDD27 Analog supply Main analog supply B13 D00_P sub-LVDS Channel 0 output B14 D00_N sub-LVDS Channel 0 output B15 D02_P sub-LVDS Channel 2 output C1 VDDD12PLL1 Digital supply Digital supply for PLL1 C2 VDDD12PLL2 Digital supply Digital supply for PLL2 C3 REQ_EXP Digital input Request exposure (start exposure) C4 VDD27 Analog supply Main analog supply C5 VSSD Digital ground Digital ground C6 VSSD Digital ground Digital ground C7 VSELH Analog Bias C8 VS2H Analog Bias C9 VS1H Analog Bias C10 VTXH Analog Bias C11 VRESH Analog Bias C12 D01_P sub-LVDS Channel 1 output C13 D01_N sub-LVDS Channel 1 output C14 D03_P sub-LVDS Channel 3 output Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 7 Document Feedback CMV50000 Pin Assignment Pin Number Pin Name Pin Type Description C15 D02_N sub-LVDS Channel 2 output D1 VDD12C Digital supply Logic supply for ADC D2 VSSD Digital ground Main digital ground D14 D03_N sub-LVDS Channel 3 output D15 D04_P sub-LVDS Channel 4 output E1 VSSDPLL1 Digital ground Digital ground for PLL1 E2 VSSDPLL2 Digital ground Digital ground for PLL2 E14 D05_P sub-LVDS Channel 0 output E15 D04_N sub-LVDS Channel 0 output F1 VSSAPLL1 Analog ground Analog ground for PLL1 F2 VSSAPLL2 Analog ground Analog ground for PLL2 F14 D05_N sub-LVDS Channel 5 output F15 D06_P sub-LVDS Channel 6 output G1 VDDA12PLL1 Analog supply Analog supply for PLL1 G2 VDDA12PLL2 Analog supply Analog supply for PLL2 G14 D07_P sub-LVDS Channel 7 output G15 D06_N sub-LVDS Channel 6 output H1 VDD12 Digital supply Logic supply for core logic H2 VSSD Digital ground Main digital ground H14 D07_N sub-LVDS Channel 7 output H15 D08_P sub-LVDS Channel 8 output J1 VDD12 Digital supply Logic supply for core logic J2 VSSA Analog ground Main analog ground J14 D09_P sub-LVDS Channel 9 output J15 D08_N sub-LVDS Channel 8 output K1 VDD12C Digital supply Logic supply for ADC K2 VSSA Analog ground Main analog ground K14 D09_N sub-LVDS Channel 9 output K15 D10_P sub-LVDS Channel 10 output L1 VSSDC Digital ground Digital ground for ADC L2 VDDARRAY Analog supply Pixel array supply L14 D11_P sub-LVDS Channel 11 output L15 D10_N sub-LVDS Channel 10 output M1 VSSDC Digital ground Digital ground for ADC M2 VDDARRAY Analog supply Pixel array supply Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 8 Document Feedback CMV50000 Pin Assignment Pin Number Pin Name Pin Type Description M14 D11_N sub-LVDS Channel 11 output M15 D12_P sub-LVDS Channel 12 output N1 VSSDC Digital ground Digital ground N2 VSSD Digital ground Digital ground N14 D13_P sub-LVDS Channel 13 output N15 D12_N sub-LVDS Channel 12 output P1 VDD18 Digital supply I/O supply for CMOS and I/O’s P2 VDD27 Analog supply Main analog supply P14 D13_N sub-LVDS Channel 13 output P15 D14_P sub-LVDS Channel 14 output R1 VDD18 Digital supply I/O supply for CMOS and I/O’s R2 VDD27 Analog supply Main analog supply R14 D15_P sub-LVDS Channel 15 output R15 D14_N sub-LVDS Channel 14 output S1 VDD27CP Analog supply Connect to VDD27 S2 VSSACP Analog ground Analog ground S14 D15_N sub-LVDS Channel 15 output S15 D16_P sub-LVDS Channel 16 output T1 VDD12C Digital supply Logic supply for ADC T2 VSSD Digital ground Main digital ground T14 D17_P sub-LVDS Channel 17 output T15 D16_N sub-LVDS Channel 16 output U1 EXTRA1 Analog ground Connect to analog ground U2 TDIGO1 Digital output Digital test output U3 TANAI1 Analog Do Not Connect U4 TANAI2 Analog Do Not Connect U5 VSELLNEG12 Analog On-chip regulator output U6 VS2LNEG12 Analog On-chip regulator output U7 VPCLNEG12 Analog On-chip regulator output U8 VS1LNEG12 Analog On-chip regulator output U9 VABNEG12 Analog On-chip regulator output U10 VRESLNEG12 Analog On-chip regulator output U11 VRESL Analog Bias U12 D19_N sub-LVDS Channel 19 output U13 D19_P sub-LVDS Channel 19 output Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 9 Document Feedback CMV50000 Pin Assignment Pin Number Pin Name Pin Type Description U14 D17_N sub-LVDS Channel 17 output U15 D18_P sub-LVDS Channel 18 output V1 REF2 Analog Do Not Connect V2 JTAG_MODE Digital input JTAG Mode select. Connect to VSSD if JTAG is not used. V3 REF3 Analog Bias V4 TANAO Analog Do Not Connect V5 VSELL Analog Bias V6 VS2L Analog Bias V7 VPCL Analog Bias V8 VS1L Analog Bias V9 VABREG Analog On-chip regulator output V10 VRESLREG Analog On-chip regulator output V11 DOBR_P sub-LVDS Right Optical Black output V12 DOBR_N sub-LVDS Right Optical Black output V13 D20_N sub-LVDS Channel 20 output V14 D20_P sub-LVDS Channel 20 output V15 D18_N sub-LVDS Channel 18 output W1 REF1 Analog Do Not Connect W2 REF0 Analog Bias W3 VSSA Analog ground Analog ground W5 VSELLREG Analog On-chip regulator output W6 VS2LREG Analog On-chip regulator output W7 VPCLREG Analog On-chip regulator output W8 VS1LREG Analog On-chip regulator output W9 VAB Analog Bias W10 CLK_N sub-LVDS Clock output W11 CLK_P sub-LVDS Clock output W13 VSSA Analog ground Main analog ground W14 D21_N sub-LVDS Channel 21 output W15 D21_P sub-LVDS Channel 21 output Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 10 Document Feedback 4 CMV50000 Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings of CMV50000 Symbol Parameter Min Max Unit Comments ±100 mA JEDEC JESD78D Nov 2011 Electrical Parameters ISCR Input Current (latch-up immunity) Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ±2000 V JEDEC JS-001-2014 ESDCDM Electrostatic Discharge CDM ±250 V JEDEC JS-002-2014 Temperature Ranges and Storage Conditions TJ Operating Junction Temperature -30 70 °C TSTRG Storage Temperature Range -30 70 °C RHNC Relative Humidity (noncondensing) 30 60 % Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 Storage condition 138 │ 11 Document Feedback 5 CMV50000 Electrical Characteristics Electrical Characteristics All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Electrical Characteristics of CMV50000 Symbol Parameter Conditions Min Typ Max Unit Power Supplies VDD12 Logic Supply Voltage of digital core, PLL 1.10 1.20 1.30 V VDD12C Logic Supply Voltage of ADC 1.10 1.20 1.30 V VDD18 I/O Supply Voltage for sub-LVDS, CMOS I/O’s 1.70 1.80 1.90 V 2.60 2.70 2.80 V 2.60 2.70 2.80 V 3.20 3.30 3.40 V VDD27 Main Analog Supply Voltage; Supply Voltage for negative regulators VDDARRAY Pixel Array Supply Voltage VDD33 Internal Regulator Supply Voltage IDD12 Supply Current IDD12C Supply Current IDD18 Supply Current IDD27 Supply Current IDDARRAY Supply Current IDD33 Supply Current Ptot Total Power Consumption Idle 350 Running 375 Idle 10 Running 410 Idle 130 Running 115 Idle 550 Running 550 Idle 130 Running 130 (1) Idle 20 Running 20 Idle 2.5 Running 3.0 mA mA mA mA mA mA W Digital I/O VIH High level input voltage 0.7 × VDD18 VDD18 +0.5 V VIL Low level input voltage -0.5 0.3 × VDD18 V VOH High level output voltage IOH=4mA VDD18 -0.15 - V VOL Low level output voltage IOL=4mA - 0.15 V CI Input load - 10 pF CO Output load - 20 pF Ttran Input transition time 0.1 5.0 ns fCLK_IN CLK_IN frequency 6 96 MHz DCCLK_IN CLK_IN duty cycle 40 60 % Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 12 Document Feedback Symbol Parameter Conditions fSPI_CLK SPI input clock frequency tsetup CMV50000 Electrical Characteristics Min Typ Max Unit - 10 MHz SPI setup time 0.25 × TSPI_CLK - ns thold SPI hold time 0 - ns tREQ REQ_FRAME/EXP pulse width 2 × TCLK_PIX - ns Sub-LVDS Interface VCM Common mode voltage 0.8 0.9 1.0 V VOD Differential voltage swing 100 150 200 mV 240 Ohm 10 % 55 % 415 MHz 2 mA 15 % (2) RO Output impedance DR0 Impedance mismatch DC Clock duty cycle 45 f Operating frequency 60 IOD Drive current 1 ∆IOD IOD variation over Temp. IDC DC current consumption 3.7 mA IAC AC current consumption 7.2 µA/MHz (1) (2) 40 50 1.5 VDDARRAY draws high peak currents (>1A) during GLOB. Enough decoupling is needed to suppress these peaks. Unused sub-LVDS channels must be terminated the same way as the used channels. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 13 Document Feedback CMV50000 Typical Operating Characteristics 6 Typical Operating Characteristics 6.1 Electro-Optical Characteristics Below are the typical electro-optical specifications of the CMV50000. These are typical values for the whole operating temperature range. Figure 7: Electro-Optical Characteristics of CMV50000 Parameter Value Remark Effective pixels 7920 × 6004 Pixel pitch 4.6 × 4.6 µm2 Optical format 35mm full frame Pixel type Global shutter with true CDS Allows fixed pattern noise correction and reset (kTC) noise canceling by true correlated double sampling (true-CDS). Shutter type Pipelined global shutter Exposure of next image during readout of the previous image. Full well charge 14500 e- Normal mode 58000 eConversion gain Responsivity 0.27 DN/e Binning mode - Normal mode, unity gain 0.068 DN/ e- Binning mode, unity gain 0.16 DN/photon @ 510nm (with micro-lenses) 0.25 A/W Temporal noise Dynamic range SNRMAX Shutter efficiency 8.8 e- Normal mode 22 e- Binning mode 64 dB Normal mode 68 dB Binning mode 41.6 dB Normal mode 47.6dB Binning mode 1/18000 At 520nm, f/8. 0.24 e-/s @ 20°C sensor temperature 66.2 e-/s @ 60°C sensor temperature 1/PLS DC Dark Current doubles every 5.1°C increase DCNU 0.72 e-/s @ 20°C sensor temperature 14.2 e-/s @ 60°C sensor temperature DC Non-Uniformity doubles every 10°C increase DSNU 24.5 e- Dark Signal Non Uniformity (FPN) 6025 Bottom buffer rows 0 -> 21 Top buffer rows 6026 -> 6047 Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 78 Document Feedback CMV50000 Functional Description Vertical ROI Settings The sensor allows up to 10 vertical windows to be concatenated in one single frame readout. Each of these windows is enabled by setting their bit in YWIN_ENA to ‘1’ (bit [0] = YWIN0, [1] = YWIN1 …). Each of these windows is configured with an YWINi register that defines the position, size and subsampling of the window. The 29 bits of each YWINi register span 4 physical SPI addresses. In the table below, only the start address is given (the upper address being 35+4×j). Figure 97: Vertical Windows Registers Register Name Bank Addr Bits Description YWIN_ENA 0 28-29 [9:0] One bit per window 0: Disable 1: Enable YWIN_BLACK 0 30 [9:0] One bit per window to control the ‘Electrical Black’ mode 0: Disable 1: Enable YWINi.SIZE 0 32+4×i [12:0] Number of read out rows in window i YWINi.START 0 32+4×i [25:13] Physical address of first row in window i YWINi.SUBS 0 32+4×i [28:26] Row subsampling in window i Ratio = 1/(2SUBS) The START address of a window should comply with the values in Figure 96. Only windows for which the respective bit in YWIN_ENA is set high are actually read out. This way multiple relevant Y-window specifications can be stored in the register map at the same time, enabling only the relevant ones. All enabled windows are concatenated together (the first row of a new window is read immediately after the last row of the previous). The number of rows actually read in one frame (= # of DVAL within one FVAL) is the sum of the SIZE fields of all windows enabled by YWIN_ENA. The figure below shows an example of using multiple windows. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 79 Document Feedback CMV50000 Functional Description Figure 98 : Vertical ROI Example (monochrome) YWIN_ENA 0000001011 0 YWIN0 100 3 1 YWIN1 0 2 0 YWIN2 200 5 3 YWIN3 50 4 FVAL DVAL YADDR 100 101 102 0 2 50 58 66 74 Electrical Black Windows With the YWIN_BLACK register, windows can be made 'electrical black' (setting a fixed voltage at the read out path instead of the pixel voltage). If the respective bit of the YWIN_BLACK register is set high (same mapping as YWIN_ENA), then all signal information in the window is suppressed. This results in a black window containing only readout FPN information. This feature could be used for column FPN correction. Window Overlap Several vertical windows may overlap, although this is only useful in subsampling mode. If the same row is read multiple times within one frame, it will only contain valid data the first time (destructive read out). One possibility is to create an interleaved readout scheme by: 1. Defining two vertical windows with identical size and SUBS set to 1 2. Giving START of the second window an offset so it starts at a row skipped by the sub sampling scheme of the first window 3. Alternating the respective YWIN_ENA bits between every frame. Figure 99 : Interleaved Readout Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 1 YWIN0 0 1080 1 YWIN1 1 1080 Even frames Odd frames YWIN_ENA = 1 YWIN_ENA = 2 138 │ 80 Document Feedback 7.5.4 CMV50000 Functional Description Vertical Subsampling Figure 100: Vertical Subsampling Registers Register Name Bank Addr Bits Description YWINi.SUBS 0 32+4×i [28:26] Row subsampling in window i COLOR_MODE 0 4 [0] 0: Monochrome 1: Color The sensor supports vertical subsampling (skipping rows), which can be set per window. The register YWINi.SUBS defines the ratio of the accessed rows in window i as 1 out of every 2SUBS rows. When COLOR_MODE register is set to 1, the rows are grouped per 2 to follow the Bayer pattern, as illustrated in Figure 101. It is recommended to only use even window sizes in color mode to keep the Bayer filter pattern intact. ROI0 in the example below demonstrates the effect of an odd window size. Figure 101 : Vertical ROI Example (color mode) Read out row 67 row 66 row 65 row 64 row 63 row 62 row 61 row 60 row 59 row 58 row 57 row 56 row 55 row 54 row 53 row 52 row 51 row 50 row 104 row 103 row 102 row 101 row 100 ROI 3 row read out row skipped ROI 0 YWIN_ENA 0000001001 1 YWIN0 100 3 1 YWIN1 0 2 0 YWIN2 200 5 3 YWIN3 50 6 Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 FVAL DVAL YADDR 100 101 104 50 51 58 59 66 67 138 │ 81 Document Feedback 7.5.5 CMV50000 Functional Description Horizontal Subsampling Figure 102: Horizontal Subsampling Registers Register Name Bank Addr Bits Description XSUBS 0 24 [1:0] Horizontal subsampling setting Ratio = 1/(2XSUBS) COLOR_MODE 0 4 [0] 0: Mono 1: Color The sensor supports horizontal subsampling, reducing the amount of pixels per line to 1:2 XSUBS. This horizontal subsampling is applied to the whole array and not per ROI like vertical subsampling. Depending on COLOR_MODE, pixel grouping is done to preserve the Bayer pattern. 7.5.6 Subsampling Mode Combining both horizontal and vertical subsampling will divide the resolution of the image by 2 in both dimensions as illustrated in Figure 103. 2 4 Figure 103 : XY-Subsampling for Color and Mono Sensors 4 2 In color mode, only 4 out of 4x4 neighboring pixels are read out. The output data is still Bayer patterned. In monochrome mode, only 1 out of 2x2 neighboring pixels is read out. The amount of pixels per channel mentioned in Figure 111 scales accordingly when combining horizontal subsampling with the readout over a reduced number of data channels. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 82 Document Feedback 7.5.7 CMV50000 Functional Description Binning Mode Figure 104: Binning Mode Registers Register Name Bank Addr Bits Description BIN_MODE 0 25 [0] 0: Binning disabled 1: Binning enabled COLOR_MODE 0 4 [0] 0: Mono 1: Color The sensor supports both color and mono-chrome binning modes. In this mode, the values of 4 pixels will be summed, before the ADC. This will reduce the read out resolution with x4, but increases full well charge, dynamic range and SNR. In color mode, the Bayer pattern is preserved. In binning mode, the summed value of 4 pixels is readout on the bottom-left position of each binning square. For every row N read at the output, two internal rows are accessed. As seen in Figure 105 in binning mode, the summed value of 4 pixels is readout on the bottom-left position of each binning square. This means only 1 out 2 columns will be read out. N+3 N+3 N+2 N+3 N+3 N+2 N+2 N+2 N+1 N+1 N N+1 N+1 2 4 Figure 105 : Color and Monochrome Binning Modes N N 4 N 2 Setting YWINi.SUBS to 0 will output binned rows N, N+1, N+2 and N+3. YWINi.SIZE refers to the number of physical rows in the array. The number of binned rows at the output will be half of this number. Binning mode cannot be combined with horizontal subsampling. For correct operation of the sensor, XSUBS must be set to 0 when binning mode is enabled. Binning mode may be combined with vertical subsampling. E.g. setting YWINi.SUBS to 1 will readout binned rows N, N+1, N+4, N+5 … in color mode and binned rows N, N+2, N+4 … in mono-chrome mode. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 83 Document Feedback CMV50000 Functional Description In binning mode, the start of a pipelined exposure must occur during an internal even row access. Depending on the control mode a distinction must be made on how to achieve this. In full external mode, the edges of REQ_EXP must be timed after the edge of REQ_FRAME in one of the discrete windows given by the equations below: Equation 13: 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃 − 𝑡𝑅𝐸𝑄_𝐹𝑅𝐴𝑀𝐸 > 𝑇𝑃𝐼𝑋 × ((2 × 𝑛 × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻) + 2) 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃 − 𝑡𝑅𝐸𝑄_𝐹𝑅𝐴𝑀𝐸 < 𝑇𝑃𝐼𝑋 × ((2 × (𝑛 + 1) × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻) − 2) For positive n and with TPIX = 1/fCLK_PIX Information In dual exposure mode, the equations must be satisfied for both edges of REQ_EXP. In programmed external mode, the time between two sequential REQ_EXP pulses must be timed according to the equations: Equation 14: 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃 − 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃_𝑝𝑟𝑒𝑣 > 𝑇𝑃𝐼𝑋 × (𝑇𝐼𝑀𝐸_𝑈𝑁𝐼𝑇 × 𝐸𝑋𝑃_𝑇𝐼𝑀𝐸_𝑖 + (2 × 𝑛 × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻) + 2) 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃 − 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃_𝑝𝑟𝑒𝑣 < 𝑇𝑃𝐼𝑋 × (𝑇𝐼𝑀𝐸_𝑈𝑁𝐼𝑇 × 𝐸𝑋𝑃_𝑇𝐼𝑀𝐸_𝑖 + (2 × (𝑛 + 1) × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻) − 2) For both EXP_TIME_L and EXP_TIME_S register settings (in dual exposure mode) and with tREQ_EXP_prev = the time of the previous REQ_EXP. The EXP_TIME_i register settings are the ones at tREQ_EXP_prev in case they are updated between frames. In Triggered internal and streaming modes, the EXP_TIME_i registers must be programmed to satisfy the equations: Equation 15: 2 × 𝑛 × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻 < 𝑇𝐼𝑀𝐸_𝑈𝑁𝐼𝑇 × (𝐹𝑅𝐴𝑀𝐸_𝑇𝐼𝑀𝐸 − 𝐸𝑋𝑃_𝑇𝐼𝑀𝐸_𝑖) < 2 × (𝑛 + 1) × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻 Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 84 Document Feedback 7.6 Configuring the Output Data Format 7.6.1 Main Output Format CMV50000 Functional Description Using the register OUTP_FORMAT one of the data readout formats introduced in section 7.3 can be selected. Figure 106: Output Format Register Reg. Name Bank Addr Bits OUTP_FORMAT 0 6 [1:0] Description 0: Pixel-based 1: Packet-based. A soft reset is required after changing OUTP_FORMAT. Refer to the flow chart in section 7.4.2. 7.6.2 Word Alignment Depending on the selected output format, word alignment must be done in a different way. Pixel-Based Word Alignment Figure 107: Training Word Register Reg. Name Bank Addr Bits Description TRAINING_WORD 0 79-80 [13:0] See below. Default value is 85 Whenever a data channel is not sending valid data (*), a training word is being transmitted continuously. The content of the training word can be set with the TRAINING_WORD register. As the sensor operates in 12-bit mode, only the lowest 12 bits of the register are sent as training word. On all DATAx_OUT channels, the last word cycle before DVAL, the training word is inverted. If the overhead time between two DVAL cycles is only 1 word wide, only the inverted training word is sent. (*) Valid data is: ● ● ● DATAx_OUT: Valid pixel data (DVAL = '1') OBL_OUT: Valid OB pixel data (LOBVAL = '1') OBR_OUT: Valid OB pixel data (ROBVAL = '1') The figure below shows illustrates this timing (drawn in the parallel domain). Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 85 Document Feedback CMV50000 Functional Description Figure 108 : Training Pattern DVAL DATAx_OUT TP TP TP TP P0 P1 ... Pn TP TP TP P0 P1 ... Pn TP When the sensor is not transmitting valid data, the training word can be used by the external controller to do word alignment (in other words: finding the position of bit [0]). Detecting the inverted training word will alert the presence of valid pixel data 1 pixel cycle in advance. When the sensor is IDLE, all control word bits except the LSB (SYNC) are '0'. Detecting the SYNC bit allows for easy word alignment at the receiver side. Since all channels are bit and word aligned by default, finding the LSB of 1 channel means the LSB of all channels has been found. Packet-Based Word Alignment As detailed in section 7.3.3, word-alignment is done using the fixed SYNC code. The HEADER field will alert the presence of valid pixel data in advance. 7.6.3 Packet Formatting Figure 109: Data Packet Formatting Registers Reg. Name Bank Addr Bits Description NOHDR_EMPTYPKT 0 79 [0] See below FEC_HEADER 0 79 [1] See below Depending on the requirements of the application, a trade-off can be made between data packet overhead (i.e. data throughput) and robustness. When register NOHDR_EMPTYPKT is set to 1, the empty packet type described in section 7.3.3, will consist only of a SYNC code, without header. When register NOHDR_EMPTYPKT is set to 0, the empty packet type will consist of SYNC+HEADER. When register FEC_HEADER is set to 1, the HEADER field will be sent as 96 bit using the 1/3 FEC described in section 7.6.3. This 1/3 FEC allows bit error corrections on the receiving side. When register FEC_HEADER is set to 0, the HEADER field will be sent in the short form (32 bit) and not be protected against bit-errors. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 86 Document Feedback CMV50000 Functional Description The register DATA_PKT_CTRL has no effect in pixel-based readout mode. 7.6.4 Outputs As illustrated in Figure 52 the sensor has 22 output channels to transfer valid image data. This means that in the fastest configuration, the sensor can output 22 pixels at the same time. As the valid image width is 7920 columns, a complete row is transferred in 370 word cycles when utilizing all outputs. Reduced Number of Data Channels In many applications, it is not mandatory to use all data channels (for example when reading a limited horizontal ROI or when operating the sensor below its nominal frame rate). In these cases, it could be interesting to use less data channels to save power consumption. The number of DATAx_OUT channels used is programmable with the NR_OUTP register. Figure 110: Number of Outputs Registers Reg. Name Bank Addr Bits Description NR_OUTP 0 26 [4:0] See above. By default all channels are used NR_OUTP_SCHEME 0 27 [0] 0: The first N channels are used 1: Channels are distributed evenly When NR_OUTP_SCHEME is set to 1, the N channels are distributed evenly, starting at DATA0_OUT. The exact mapping details are given in the table below. Figure 111: Reduced Number of Output Settings (NR_OUTP_SCHEME=1) NR_OUTP Used DATAx_OUT Channels Nr. of Pixels per Channel Nr. of Padding Pixels 1 0 7920 0 2 0,11 3960 0 3 0,8,16 2880 720 4 0,6,12,18 2160 720 5 0,5,10,15,20 1800 1080 6 0,4,8,12,16,20 1440 720 8 0,3,6,9,12,15,18,21 1080 720 11 0,2,4,6,8,10,12,14,16,18,20 720 0 22 All (0 to 21) 360 0 When NR_OUTP_SCHEME is set to 0, the first N channels starting at DATA0_OUT are used. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 87 Document Feedback CMV50000 Functional Description For example, when setting NR_OUTP to 5, DATA0_OUT to DATA4_OUT channels are used. DATA5_OUT to DATA21_OUT are disabled. All other values in table above are still applicable. It is not allowed to set NR_OUTP to any value not listed in Figure 111 (i.e. 0, 7, 9 to 10 or 12 to 21.) All unused DATAx_OUT channels are automatically disabled (powered down). The last (or rightmost) channel of the used DATAx_OUT channels pads dummy pixels after the valid pixels when needed. Every channel sends an equal amount of pixels. Pixel Order The selected ROI (or full image width) is divided over 1 or more output channels. On each output, pixels are presented in-order. The figure below shows the timing of the readout of a single row for NR_OUTP set to 4 (each box represents the physical column address of the pixel). Here pixels 7920 to 8639 are dummy padding pixels and must be discarded. Figure 112 : Multiplexed Sub-LVDS Timing Example A similar example for packet-based readout format is given in Figure 113. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 88 Document Feedback CMV50000 Functional Description Figure 113 : Multiplexed Sub-LVDS Timing Example in Packet Mode Pixel data packet 1 Pixel data packet 2 Pixel data packet 6 ... DATA0_OUT SYNC HEADER PIXELS 0 to 359 CRC SYNC SYNC SYNC Pixel data packet 7 HEADER PIXELS 360 to 719 CRC SYNC HEADER PIXELS 1800 to 2159 Pixel data packet 8 SYNC HEADER PIXELS 2160 to 2519 CRC SYNC SYNC SYNC Pixel data packet 13 HEADER PIXELS 2520 to 2879 CRC SYNC HEADER PIXELS 3960 to 4319 Pixel data packet 14 SYNC HEADER PIXELS 4320 to 4679 CRC SYNC SYNC SYNC Pixel data packet 19 HEADER PIXELS 4680 to 4999 CRC SYNC CRC SYNC SYNC CRC SYNC SYNC Pixel data packet 18 ... DATA2_OUT SYNC Pixel data packet 12 ... DATA1_OUT CRC SYNC HEADER PIXELS 6120 to 6479 Pixel data packet 20 ... DATA3_OUT SYNC HEADER PIXELS 6480 to 6839 CRC SYNC SYNC SYNC HEADER PIXELS 6840 to 7159 CRC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC Every used data output channel outputs 6 data packets per line, separated by a number of empty packets. DATA3_OUT transmits only 4 data packets per line, the last being #22 which contains pixels 7560 to 7919. After that, empty packets are sent on DATA3_OUT. In packet-base mode, the word alignment between subsequent data packets might vary (depending on subsampling …). In the example above, this may be the case if the data packet is not a multiple of 4 bytes. This translates into the need to redo word alignment between two packets on the same channel when reading out over a reduced number of data channels. 7.7 Configuring the On-Chip Data Processing 7.7.1 Optical Black Clamping Figure 114: Optical Black Registers Reg. Name Bank Addr Bits Description EOB_TARGET 0 76-77 [13:0] Sets the target black level value in DN EOB_BYPASS 1 42 [0] 0: OBC on (recommended) 1: OBC off EOB_BYPASS_VALUE Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 1 43-44 [13:0] Sets the ideal black level at the ADC (when OBC off). 138 │ 89 Document Feedback CMV50000 Functional Description This section explains how to set and correct the black levels. Black Level Mapping The black level at a certain point in the pixel data path on the sensor is the analog level or digital word that corresponds to the level of an ideal dark pixel (zero illumination). In practice, it is the average of all real dark pixels (optically shielded) at that point in the data path. The black level at the output of the ADC does not equal the desired black level in the output images for several reasons including the ADC architecture, fixed pattern and temporal noise (row noise, frame noise), dark current… As illustrated in the figure below, the black level at the ADC output needs to be mapped on the target black level at the sensor output. Figure 115 : Black Level Mapping ADC_OUT ^15 2 -1 white DATA_OUT VALID RANGE OUTPUT RANGE black row noise frame noise BLACK LEVEL target 0 The mapping is done using the equation: Equation 16: 𝑃𝐼𝑋𝐷𝐴𝑇𝐴_𝑂𝑈𝑇 = 𝑐𝑙𝑖𝑝[𝑃𝐼𝑋𝐴𝐷𝐶_𝑂𝑈𝑇 − 𝐵𝐿𝐴𝐶𝐾_𝐿𝐸𝑉𝐸𝐿𝐴𝐷𝐶_𝑂𝑈𝑇 + 𝐵𝐿𝐴𝐶𝐾_𝐿𝐸𝑉𝐸𝐿𝐷𝐴𝑇𝐴_𝑂𝑈𝑇 ] BLACK_LEVELDATA_OUT is the target black level at the output of the sensor. It is specified with the register EOB_TARGET. The recommended minimal setting is 128 (lower settings may decrease the quality of the resulting image), which means the level at the output for black pixels will be around 128DN. BLACK_LEVELADC_OUT is the black level at the output of the ADC. Its value is set differently depending on how the black level correction is done. This is detailed in the next two sections. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 90 Document Feedback CMV50000 Functional Description On-Chip OBC Setting EOB_BYPASS to 0 enables the automatic on-chip black level correction (clamping). In this mode, BLACK_LEVELADC_OUT is calculated on-chip, based on OB pixels, for every row allowing to correct for row and frame noise in the image. This is the recommended mode of operation. Off-Chip OBC Setting EOB_BYPASS to 1 disables the automatic OBC. BLACK_LEVELADC_OUT is now specified with register EOB_BYPASS_VALUE. This value is constant and cannot correct for row noise in the image. Equation 17: 𝑃𝐼𝑋𝐷𝐴𝑇𝐴_𝑂𝑈𝑇 = 𝑐𝑙𝑖𝑝[𝑃𝐼𝑋𝐴𝐷𝐶_𝑂𝑈𝑇 − 𝐸𝑂𝐵_𝐵𝑌𝑃𝐴𝑆𝑆_𝑉𝐴𝐿𝑈𝐸 + 𝐸𝑂𝐵_𝑇𝐴𝑅𝐺𝐸𝑇] Further external or off-chip OBC can be achieved by reading out the OB pixel data (refer to section 7.8.5). 7.7.2 Analog and Digital Gain Register GANA is used to set the analog gain. When changing the analog gain, the OB black level also has to be fine-tuned to have optimal black level clamping. Figure 116: Analog Gain Registers Reg. Name Bank Addr Bits Description GANA 0 78 [7:0] See settings in 7.4.2 EOB_OFFSET_FINE 1 38-39 [15:0] See settings in 7.4.2 Digital gain can be specified for the 4 color channels individually (even/odd columns, even/odd rows). E.g. GDIG_RE_CO relates to Rows Even and Columns Odd. The digital gain for each channel is defined by a similar equation: Equation 18: 𝐷𝑖𝑔𝑖𝑡𝑎𝑙 𝑔𝑎𝑖𝑛 (𝑅𝑥_𝐶𝑦) = (𝐺𝐷𝐼𝐺_𝑅𝑥_𝐶𝑦 + 1)/16 Base (default) digital gain is set by uploading a value of 15 to GDIG_Rx_Cy. The maximum digital gain is 16x with GDIG_Rx_Cy at 256. The lowest digital gain is 1/16x with GDIG_Rx_Cy at 0. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 91 Document Feedback CMV50000 Functional Description Figure 117: Digital Gain Registers Reg. Name Bank Addr Bits Description GDIG_RE_CE 0 72 [7:0] Even Rows & Even Columns See equation above GDIG_RE_CO 0 73 [7:0] Even Rows & Odd Columns See equation above GDIG_RO_CE 0 74 [7:0] Odd Rows & Even Columns See equation above GDIG_RO_CO 0 75 [7:0] Odd Rows & Odd Columns See equation above If possible, using analog gain is preferred to using digital gain because it will improve SNR. Analog gain is applied in the data path before the ADC and digital gain is applied after the black level correction. This means that changing the digital gain setting does not require any of the offset correction settings to be updated. 7.7.3 Color versus Monochrome Mode Figure 118: Color Mode Register Register Name Bank Addr Bits COLOR_MODE 0 4 [0] Description 0: Mono 1: Color As introduced in sections 7.5.6 and 7.5.7, sub sampling and binning modes behave differently for color and monochrome sensors. Set COLOR_MODE 1 for color sensors and 0 for monochrome sensors. 7.8 Additional Features 7.8.1 Digital Test Output Figure 119: Digital Test Output Register Reg. Name Bank Addr Bits Description DMUX1_SEL 1 99 [4:0] Sets pin TDIGO1 function Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 92 Document Feedback CMV50000 Functional Description A number of digital signals of the chip can be monitored in real-time during normal sensor operation via the sensor output pin TDIGO1. This can be very helpful for testing and debugging the system without having to rely on the sub-LVDS implementation of the control channel, so a test pad or connection to the FPGA is recommended. Selecting which signal to be monitored is done with DMUX1_SEL. 7.8.2 OTP Memory OTP Registers The anti-fuse memory cells are organized in 128 rows (addresses) of 16 bits each. It contains the Device Serial Number, which is the unique serial number that matches with the one printed on the package. This serial number is in ASCII, so every address contains two characters. The Device Serial Number has two retry registers in case it had to be rewritten. So, the last retry register which contains a value other than zero, contains the correct sensor serial number. Next to the serial number, the memory has the Temperature (wafer test 1) register. It contains the value of the TSENS1_OUTPUT SPI register during our wafer test with the device at 70°C. Below you can find the positions of the OTP registers which can be read out. Figure 120: OTP Registers OTP Register Name Description Addr Length Device serial nr Unique serial number of device 2 8 Device serial nr (retry 1) Retry 1 10 8 Device serial nr (retry 2) Retry 2 18 8 Temperature (wafer test 1) TSENS1_OUTPUT value at 70°C 38 1 Read Access via the SPI Interface The OTP addresses are read out via the SPI interface through a predefined protocol as indicated in the table below. Figure 121: Read Access (read from address Ai) Step Description Register Access 1 Init OTP_CONTROL = "001” wait 20µs Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 93 Document Feedback CMV50000 Functional Description Step Description Register Access 2 Set up address OTP_A = Ai 3 Read OTP_CONTROL = "101” wait 5µs OTP_CONTROL = "001” wait 10µs Read value from OTP_DOUT 4 Exit OTP_CONTROL = “000” The address Ai needs to be replaced by the desired OTP register. For multiple reads, steps 2 and 3 can be repeated consecutively for every address Ai. In the table below the addresses of the registers used during the protocol are given. Figure 122: Registers Used during Read Access 7.8.3 Register Name Bit Name Bank Addr Pos OTP_CONTROL OTP_PDN 0 97 [0] OTP_CONTROL OTP_READBPROG 0 97 [1] OTP_CONTROL OTP_SELECTWLBL 0 97 [2] OTP_A - 0 98 [6:0] OTP_DOUT - 0 101 [15:0] Temperature Sensor Figure 123: Temperature Sensor Registers Reg. Name Bank Addr Bits Description TSENS1_PDN 0 103 [0] Power down not TSENS1_RSTN 0 103 [1] Reset not TSENS1_DCORRECT 0 103 [7:2] Offset value TSENS1_OUTPUT 0 104-105 [9:0] Read-only code The sensor has a temperature sensor placed at the top side of the sensor. In the range of -40°C to 125°C, the temperature sensor has a maximum error of ±12°C without calibration. After a one-point calibration at 25°C, the maximum error is ±5°C, after a two-point calibration, the maximum error becomes ±3°C. To disable the temperature sensor, both TSENS1_PDN and TSENS1_RSTN must be set to ‘0’. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 94 Document Feedback CMV50000 Functional Description To enable the temperature sensor, both TSENS1_PDN and TSENS1_RSTN must be set to ‘1’ and a settling time of 0.5ms must be respected before reading TSENS1_OUTPUT. The bit [9] of TSENS1_OUTPUT is high when an overflow condition has occurred in the temperature sensor. If this condition occurs, the temperature is either out of range, or a wrong offset was programmed in the TSENS1_DCORRECT register. No Calibration In order to get the uncalibrated temperature of the die (±12°C), follow this procedure: 1. Write value 131 to TSENS1_CONTROL 2. Wait 0.5ms (settling time) 3. Read TSENS1_OUTPUT 4. Calculate the measured die temperature according to the equation: Tm = (TSENS1_OUTPUT[8:0] / 2) – 100 1-Point Calibration The procedure below describes how to calculate and set the calibration value for the temperature sensor to output the correct sensor temperature (±5°C) using one measurement. 1. Let the sensor reach a known temperature (T j) around 25°C and let it settle so that the die temperature (which equals the package temperature) is stable. 2. Write value 131 to TSENS1_CONTROL 3. Wait 0.5ms (settling time) 4. Read TSENS1_OUTPUT 5. Calculate the uncalibrated die temperature according to the equation Tu = (TSENS1_OUTPUT[8:0] / 2) – 100 6. Calculate the calibration error: Te = Tj - Tu 7. Update TSENS1_DCORRECT to 32 + (2 × Te) From now on, to measure the die temperature within ±5°C accuracy in the range from -40°C to 125°C: 1. Read TSENS1_OUTPUT 2. Calculate the measured die temperatures according to the equation Tm = (TSENS1_OUTPUT[8:0] / 2) – 100 An example: ● ● We let the sensor settle unpowered to a known ambient temperature of 28°C. We power up the sensor and immediately read out TSENS1_OUTPUT[8:0]. This way the junction temperature will be very close to the ambient temperature. TSENS1_OUTPUT[8:0] contains 260. So now Tu = (260/2) – 100 = 30 and Te = 28 – 30 = -2. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 95 Document Feedback ● ● ● CMV50000 Functional Description Upload TSENS1_DCORRECT with the value 32 + (2 × Te) = 28. Reading out TSENS1_OUTPUT[8:0] now gives a value of 256, which corresponds to the correct temperature Tm = (256/2) – 100 = 28. When during operation, you read out TSENS1_OUTPUT[8:0] as, for example, 338, you know that the junction temperature is equal to Tj = Tm = (338/2) – 100 = 69°C (±5°C) It is possible to take the TSENS1_OUTPUT value obtained during the wafer test at Tj = 70°C described in section 7.8.2. With those two values the procedure above can be executed immediately instead of measuring the temperature first. 2-Point Calibration A 2-point calibration will correct for the offset as well as the slope over temperature. The procedure below describes how to calculate and set the calibration value for the temperature sensor to output the correct sensor temperature (±3°C) using two measurements. 1. Let the sensor reach a known temperature (T j1) and let it settle so that the die temperature (which equals the package temperature) is stable. 2. Write value 131 to TSENS1_CONTROL, which will 3. Wait 0.5ms (settling time) 4. Read TSENS1_OUTPUT[8:0] and save it as B1. 5. Change the temperature to Tj2 (preferably more than 30°C difference with T j1) and let it settle. 6. Read out TSENS1_OUTPUT[8:0] and save it as B2. 7. Calculate the slope as: M = (Tj2 – Tj1)/(B2-B1). For an ideal and perfect temperature sensor the slope will be 0.5. 8. Calculate the offset as: C = Tj1 - M*B1 = Tj2 – M×B2 9. Store the values M and C, which define a straight line. From now on, to measure the die temperature within ±3oC accuracy in the range from -40°C to 125°C: 1. Read TSENS1_OUTPUT 2. Calculate the measured die temperatures according to the equation Tm = M ×TSENS1_OUTPUT[8:0] + C Information For 2-point calibration TSENS1_DCORRECT must be left at its default value (32). Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 96 Document Feedback 7.8.4 CMV50000 Functional Description Version ID Figure 124: Version ID Register Reg. Name Bank Addr Bits Description VERSION_ID 0 116 [7:0] Read only The read-only register VERSION_ID contains the revision number of the sensor. 7.8.5 Enable Optical Black Outputs By default, the OBx_OUT channels are disabled. To enable (or disabling again) the OB channels, use the following SPI sequence: Figure 125: Enable OB Outputs Sequence Upload # Bank Address Write Value 1 1 107 1 2 1 106 16 3 1 106 24 4 1 106 16 5 1 106 16 6 1 106 16 7 1 106 16 8 1 106 16 9 1 106 16 10 1 106 16 11 1 106 16 12 1 106 16 13 1 106 16 14 1 106 16 15 1 106 16 16 1 106 16 17 1 106 16 18 1 106 16 19 1 106 16 Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 97 Document Feedback Upload # Bank Address Write Value 20 1 106 16 21 1 106 16 22 1 106 16 23 1 106 16 24 1 106 16 25 1 106 16 26 1 106 16 27 1 106 24 28 1 106 16 29 1 107 0 CMV50000 Functional Description The OB data is read out 1 row before the image data row it refers to. See also section 7.3.2. OB channel enabling/disabling can only be done when the PLL’s are locked, enabled and reset is released. 7.8.6 Test Images Right before the sub-LVDS output drivers, the data stream can be replaced with a number of test patterns. Selection of test mode is made with the TEST_LVDS register as indicated in the table below. Figure 126: Test Images Registers Reg. Name Bank Addr Bits Description TEST_LVDS 0 81 [2:0] See table below TRAINING_WORD 0 79-80 [13:0] Choose a value Figure 127: Sub-LVDS Test Modes TEST_LVDS DATAx_OUT OBx_OUT CTR_OUT CLK_OUT 0 Normal Normal Normal Normal 1 Force training word continuously Force training word continuously Force training word continuously Normal 2 Test image: gradient Drive constant 0 Normal Normal 3 Test image: LFSR Drive constant 0 Normal Normal Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 98 Document Feedback CMV50000 Functional Description In test mode 1, the data and OB output channels are forced to output register TRAINING_WORD and the control channel outputs its own training word. In test modes 2 and 3, a fixed test image is created. The CLK_OUT and CTR_OUT channels drive their normal values, so only the actual pixel data is replaced. This is useful to debug the camera system before grabbing real images. In sub-LVDS test mode 2, the data of pixel N is replaced by the value: Equation 19: 𝐷𝑇𝐸𝑆𝑇 = 𝑁𝐶𝑂𝐿 + 𝑁𝑅𝑂𝑊 + 𝑁𝐾𝐸𝑅𝑁𝐸𝐿 + 1 With: ● ● ● NCOL is the running number of pixel N in the DVAL pulse (0 for first valid pixel on each output) NROW is the running number of the DVAL pulse within FVAL (0 for first valid row in each FVAL) NKERNEL is the number of the channel from which pixel N originates The result is a 2D gradient (per channel), with a starting offset depending on the kernel number. The figure below shows an example using NR_OUTP = 4 (NKERNEL is resp. 0, 6, 12, 18). Figure 128 : Gradient Test Image Pixel Data FVAL DVAL DATA0_OUT TP 1 (0 + 0 + 0 + 1) 2 (1 + 0 + 0 + 1) ... 2160 (2159 + 0 + 0 + 1) TP 2 (0 + 1 + 0 + 1) DATA1_OUT TP 7 (0 + 0 + 6 +1) 8 (1 + 0 + 6 +1) ... 2166 (2159 + 0 + 6 +1) TP 8 (0 + 1 + 6 + 1) DATA2_OUT TP 13 (0 + 0 + 12 + 1) 14 (1 + 0 + 12 + 1) ... 2172 (2159 + 0 +12 +1) TP 14 (0 + 1 + 12 +1) DATA3_OUT TP 19 (0 + 0 + 18 + 1) 20 (1 + 0 + 18 +1) ... 2178 (2159 + 0 +18 +1) TP 20 (0 + 1 + 18 +1) Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 99 Document Feedback CMV50000 Functional Description Figure 129 : Gradient Test Image Example In sub-LVDS test mode 3, the actual data of every pixel is replaced by the output of a pseudo-random generator. The value of the first valid pixel of a frame is 4095. All outputs drive the same output value (unlike test mode 2, where the NKERNEL generates an offset between outputs). Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 100 Document Feedback CMV50000 Functional Description Figure 130 : LSFR Test Image Example Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 101 Document Feedback 8 Register Description 8.1 Register Overview CMV50000 Register Description Figure 131: Register Overview Bank Select Addr 0 Name - - - - - - - - - - - - - PARAM_ HOLD - - - - - - - DISABLE_ FRAMESYNC BANK_SEL BANK_SEL [1:0] Figure 132: Register Overview Bank 0 Addr 1 2 Name PARAM_HOLD DISABLE_ FRAMESYNC 3 CMD_REGS - - - HALT_ NBLOCK HALT_ BLOCK REQ_ FRAME REQ_ EXP RST_ SOFT_N 4 COLOR_MODE - - - - - - - COLOR_ MODE 5 - - - - - - - - 6 OUTP_FORMAT - - - - - - 7 DATA_PKT_ CTRL - - - - - - NOHDR_ EMPTYPKT FEC_ HEADER 8 - - - - - - - - 9 CTRL_MODE - - - - - 10 TIME_UNIT 11 TIME_UNIT 12 NROF_FRAMES 13 FRAME_TIME FRAME_TIME [7:0] 14 FRAME_TIME FRAME_TIME [15:8] 15 DUAL_ EXPOSURE 16 EXP_TIME_L EXP_TIME_L [7:0] 17 EXP_TIME_L EXP_TIME_L [15:8] 18 EXP_TIME_S EXP_TIME_S [7:0] 19 EXP_TIME_S EXP_TIME_S [15:8] 20 - - - - 21 - - - - 22 ROW_LENGTH Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 OUTP_FORMAT [1:0] CTRL_MODE [2:0] TIME_UNIT [7:0] - - TIME_UNIT [13:8] NROF_FRAMES [7:0] - - - - - - DUAL_ EXPOSURE - - - - - - - - - ROW_LENGTH [7:0] 138 │ 102 Document Feedback Addr Name CMV50000 Register Description 23 ROW_LENGTH - - 24 XSUBS - - - - - - 25 BIN_MODE - - - - - - 26 NR_OUTP - - - 27 NR_OUTP_ SCHEME - - - 28 YWIN_ENA 29 YWIN_ENA 30 YWIN_BLACK 31 YWIN_BLACK 32 YWIN0 33 YWIN0 34 YWIN0 35 YWIN0 36 YWIN1 37 YWIN1 38 YWIN1 START [10:3] 39 YWIN1 SIZE [7:0] 40 YWIN2 41 YWIN2 42 YWIN2 - - - SUBS [2:0] START [12:11] 43 YWIN2 - - - SUBS [2:0] START [12:11] 44 YWIN3 45 YWIN3 46 YWIN3 47 YWIN3 48 YWIN4 49 YWIN4 50 YWIN4 51 YWIN4 52 YWIN5 53 YWIN5 54 YWIN5 55 YWIN5 56 YWIN6 57 YWIN6 58 YWIN6 59 YWIN6 60 YWIN7 61 YWIN7 62 YWIN7 Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 ROW_LENGTH [13:8] XSUBS [1:0] - BIN_MODE - NR_OUTP_ SCHEME NR_OUTP [4:0] - - - YWIN_ENA [7:0] - - - - - - YWIN_ENA [9:8] - YWIN_BLACK [9:8] YWIN_BLACK [7:0] - - - - SIZE [7:0] START [2:0] SIZE [12:8] START [10:3] - - - SUBS [2:0] START [12:11] SIZE [7:0] START [2:0] SIZE [12:8] START [2:0] SIZE [12:8] START [10:3] SIZE [7:0] START [2:0] SIZE [12:8] START [10:3] - - - SUBS [2:0] START [12:11] SIZE [7:0] START [2:0] SIZE [12:8] START [10:3] - - - SUBS [2:0] START [12:11] SIZE [7:0] START [2:0] SIZE [12:8] START [10:3] - - - SUBS [2:0] START [12:11] SIZE [7:0] START [2:0] SIZE [12:8] START [10:3] - - - SUBS [2:0] START [12:11] SIZE [7:0] START [2:0] SIZE [12:8] START [10:3] 138 │ 103 Document Feedback Addr Name - - - CMV50000 Register Description 63 YWIN7 64 YWIN8 65 YWIN8 66 YWIN8 67 YWIN8 68 YWIN9 69 YWIN9 70 YWIN9 71 YWIN9 72 GDIG_RE_CE GDIG_RE_CE [7:0] 73 GDIG_RE_CO GDIG_RE_CO [7:0] 74 GDIG_RO_CE GDIG_RO_CE [7:0] 75 GDIG_RO_CO GDIG_RO_CO [7:0] 76 EOB_TARGET EOB_TARGET [7:0] 77 EOB_TARGET 78 GANA 79 TRAINING_ WORD 80 TRAINING_ WORD - - 81 TEST_LVDS - - - - - 82 - 100 - - - - - 101 OTP_DOUT OTP_DOUT [7:0] 102 OTP_DOUT OTP_DOUT [15:8] 103 TSENS1_ CONTROL 104 TSENS1_ OUTPUT 105 TSENS1_ OUTPUT - - - - - - 106 PLL1_ENABLE - - - - - - 107 PLL1_PRE_DIV - - - - - - PLL1_PRE_DIV [1:0] 108 PLL1_NDIV 109 PLL1_ CLKOUT_SEL - - - - - - PLL1_CLKOUT_SEL [1:0] 110 PLL2_ENABLE - - - - - - - PLL2_ ENABLE 111 - - - - - - - - 112 PLL2_NDIV 113 - - - - - - - - 114 PLL_CLKDIV_ RSTN - - - - - - - PLL_ CLKDIV_ RSTN 115 PLL_LOCK - - - - - - PLL2_LOCK PLL1_LOCK Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 SUBS [2:0] START [12:11] SIZE [7:0] START [2:0] SIZE [12:8] START [10:3] - - - SUBS [2:0] START [12:11] SIZE [7:0] START [2:0] SIZE [12:8] START [10:3] - - - - SUBS [2:0] - START [12:11] EOB_TARGET [13:8] GANA [7:0] TRAINING_WORD [7:0] TRAINING_WORD [13:8] TEST_LVDS [2:0] - DCORRECT [5:0] - - RSTN PDN TSENS1_OUTPUT [7:0] TSENS1_OUTPUT [9:8] - PLL1_ ENABLE PLL1_NDIV [7:0] PLL2_NDIV [7:0] 138 │ 104 Document Feedback Addr Name CMV50000 Register Description 116 VERSION_ID 117 NO_ SHUTTER_LAG - - - - - - - NO_ SHUTTER_ LAG 118 DUAL_EXP_ GROUPING - - - - - - - DUAL_EXP_ GROUPING - - - - - - - - VERSION_ID [7:0] Figure 133: Register Overview Bank 1 Addr Name 1-4 5 GRAN_GLOB 6 CLKGEN_CFG - 7 - 98 - 99 GRAN_GLOB [7:0] TDIG [2:0] - - - - [2:0] 100 - 109 110 TG_LENGTH 111 TG_LENGTH - - 112 - 113 - - 114 SHUTTER_LAG 115 SHUTTER_LAG 116 - 119 - - CLKGEN_PHASE [1:0] - - - - - - - DMUX1_SEL [4:0] - - - - TG_LENGTH [7:0] TG_LENGTH [13:8] - - - - SHUTTER_LAG [7:0] SHUTTER_LAG [13:8] - - - - - - - - - - - - - - - - Figure 134: Register Overview Bank 2 Addr 1 - 127 Name Figure 135: Register Overview Bank 3 Addr Name 1 - 48 - - - - - - - - 49 PLL1_DISABLE _CLKOUT - - - - - - - PLL1_ DISABLE_ CLKOUT Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 105 Document Feedback Addr 50 - 57 Name CMV50000 Register Description - - - - - - - - 8.2 Detailed Register Description 8.2.1 BANK_SEL Register (Address 0) Figure 136: BANK_SEL Register Addr: 0 Bit [1:0] 8.2.2 BANK_SEL Bit Name BANK_SEL Default 0 Access Bit Description - 0: Bank 0 1: Bank 1 2: Bank 2 3: Bank 3 PARAM_HOLD Register (Bank 0, Address 1) Figure 137: PARAM_HOLD Register Bank: 0 Addr: 1 PARAM_HOLD Bit Bit Name Default Access Bit Description 0 PARAM_HOLD 0 - 0: Frame sync 1: During SPI upload Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 106 Document Feedback 8.2.3 CMV50000 Register Description DISABLE_FRAMESYNC Register (Bank 0, Address 2) Figure 138: DISABLE_FRAMESYNC Register 8.2.4 Bank: 0 Addr: 2 DISABLE_FRAMESYNC Bit Bit Name Default Access Bit Description [0] DISABLE_FRAMESYNC 0 - 0: Enable frame sync 1: Disable frame sync CMD_REGS Register (Bank 0, Address 3) Figure 139: CMD_REGS Register Bank: 0 Addr: 3 CMD_REGS Bit Bit Name Default Access Bit Description [0] RST_SOFT_N 0 - 0: Assert soft reset 1: Release soft reset [1] REQ_EXP 0 - 0: 1: Sensor in EXPOSURE state [2] REQ_FRAME 0 - 0: 1: Sensor in GLOB state [3] HALT_BLOCK 0 - 0: 1: Finish active READOUT state and go to IDLE state [4] HALT_NBLOCK 0 - 0: 1: Immediately stop sensor and go to IDLE state Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 107 Document Feedback 8.2.5 CMV50000 Register Description COLOR_MODE Register (Bank 0, Address 4) Figure 140: COLOR_MODE Register 8.2.6 Bank: 0 Addr: 4 COLOR_MODE Bit Bit Name Default Access Bit Description [0] COLOR_MODE 0 DC 0: Monochrome mode 1: Color mode OUTP_FORMAT Register (Bank 0, Address 6) Figure 141: OUTP_FORMAT Register 8.2.7 Bank: 0 Addr: 6 OUTP_FORMAT Bit Bit Name Default Access Bit Description [1:0] OUTP_FORMAT 0 RST 0: Pixel based format 1: Packet based format DATA_PKT_CTRL Register (Bank 0, Address 7) Figure 142: DATA_PKT_CTRL Register Bank: 0 Addr: 7 DATA_PKT_CTRL Bit Default Bit Name Access Bit Description [0] NOHDR_EMPTYPKT 1 DC 0: SYNC + HEADER in empty packet. 1: Only SYNC in empty packet [1] FEC_HEADER 1 DC 0: 32b HEADER 1: 96b HEADER with 1/3 FEC Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 108 Document Feedback 8.2.8 CMV50000 Register Description CTRL_MODE Register (Bank 0, Address 9) Figure 143: CTRL_MODE Register Bank: 0 Addr: 9 CTRL_MODE Bit Default [2:0] 8.2.9 Bit Name CTRL_MODE 1 Access Bit Description DC 0: Full External (FE) 1: Programmed External (PE) 2: Triggered Internal (TI) 3: Streaming (S) TIME_UNIT Register (Bank 0, Address 10-11) Figure 144: TIME_UNIT Register 8.2.10 Bank: 0 Addr: 10-11 TIME_UNIT Bit Bit Name Default Access Bit Description [13:0] TIME_UNIT 69 FRAME Sets unit for frame and exposure time NROF_FRAMES Register (Bank 0, Address 12) Figure 145: NROF_FRAMES Register Bank: 0 Addr: 12 NROF_FRAMES Bit Bit Name Default Access Bit Description [7:0] NROF_FRAMES 1 - Sets sequence length for TI control mode Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 109 Document Feedback 8.2.11 CMV50000 Register Description FRAME_TIME Register (Bank 0, Address 13-14) Figure 146: FRAME_TIME Register 8.2.12 Bank: 0 Addr: 13-14 FRAME_TIME Bit Bit Name Default Access Bit Description [15:0] FRAME_TIME 33000 DC Sets the frame time in time units DUAL_EXPOSURE Register (Bank 0, Address 15) Figure 147: DUAL_EXPOSURE Register Bank: 0 Addr: 15 DUAL_EXPOSURE Bit Default [0] 8.2.13 Bit Name DUAL_EXPOSURE 0 Access Bit Description DC 0: Disable dual exposure HDR 1: Enable dual exposure HDR EXP_TIME_L Register (Bank 0, Address 16-17) Figure 148: EXP_TIME_L Register Bank: 0 Addr: 16-17 EXP_TIME_L Bit Bit Name Default Access Bit Description [15:0] EXP_TIME_L 10000 FRAME Sets the exposure time of pixels in group L in time units Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 110 Document Feedback 8.2.14 CMV50000 Register Description EXP_TIME_S Register (Bank 0, Address 18-19) Figure 149: EXP_TIME_S Register 8.2.15 Bank: 0 Addr: 18-19 EXP_TIME_S Bit Bit Name Default Access Bit Description [15:0] EXP_TIME_S 0 FRAME Sets the exposure time of pixels in group S in time units ROW_LENGTH Register (Bank 0, Address 22-23) Figure 150: ROW_LENGTH Register 8.2.16 Bank: 0 Addr: 16-17 ROW_LENGTH Bit Bit Name Default Access Bit Description [13:0] ROW_LENGTH 380 SYNC Sets the row time XSUBS Register (Bank 0, Address 24) Figure 151: XSUBS Register Bank: 0 Addr: 24 XSUBS Bit Bit Name Default Access Bit Description [1:0] XSUBS 0 SYNC Set horizontal subsampling ratio to 1/(2XSUBS) Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 111 Document Feedback 8.2.17 CMV50000 Register Description BIN_MODE Register (Bank 0, Address 25) Figure 152: BIN_MODE Register 8.2.18 Bank: 0 Addr: 25 BIN_MODE Bit Bit Name Default Access Bit Description [0] BIN_MODE 0 SYNC 0: Disable binning 1: Enable binning NR_OUTP Register (Bank 0, Address 26) Figure 153: NR_OUTP Register 8.2.19 Bank: 0 Addr: 26 NR_OUTP Bit Bit Name Default Access Bit Description [4:0] NR_OUTP 22 DC Sets the number of data outputs used to 1, 2, 3, 4, 5, 6, 8, 11 or 22. NR_OUTP_SCHEME Register (Bank 0, Address 27) Figure 154: NR_OUTP_SCHEME Register Bank: 0 Addr: 27 NR_OUTP_SCHEME Bit Default [0] Bit Name NR_OUTP_SCHEME Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 0 Access Bit Description DC 0: Use the first NR_OUTP data outputs 1: Used channels are distributed evenly 138 │ 112 Document Feedback 8.2.20 CMV50000 Register Description YWIN_ENA Register (Bank 0, Address 28-29) Figure 155: YWIN_ENA Register Bank: 0 Addr: 28-29 YWIN_ENA Bit Default [9:0] 8.2.21 Bit Name YWIN_ENA 1 Access Bit Description SYNC Enables/disables one window per bit 0: Disable window N 1: Enable window N YWIN_BLACK Register (Bank 0, Address 30-31) Figure 156: YWIN_BLACK Register Bank: 0 Addr: 30-31 YWIN_BLACK Bit Default [9:0] 8.2.22 Bit Name YWIN_BLACK 0 Access Bit Description SYNC Enables/disables Electrical Black for one window per bit 0: Disable EB of window N 1: Enable EB of window N YWIN0 Register (Bank 0, Address 32-35) Figure 157: YWIN0 Register Bank: 0 Addr: 32-35 YWIN0 Bit Bit Name Default Access Bit Description [12:0] SIZE 6004 SYNC Number of rows in this window [25:13] START 22 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 113 Document Feedback 8.2.23 CMV50000 Register Description YWIN1 Register (Bank 0, Address 36-39) Figure 158: YWIN1 Register 8.2.24 Bank: 0 Addr: 36-39 YWIN1 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) YWIN2 Register (Bank 0, Address 40-43) Figure 159: YWIN2 Register 8.2.25 Bank: 0 Addr: 40-43 YWIN2 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) YWIN3 Register (Bank 0, Address 44-47) Figure 160: YWIN3 Register Bank: 0 Addr: 44-47 YWIN3 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 114 Document Feedback 8.2.26 CMV50000 Register Description Bank: 0 Addr: 44-47 YWIN3 Bit Bit Name Default Access Bit Description [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) YWIN4 Register (Bank 0, Address 48-51) Figure 161: YWIN4 Register 8.2.27 Bank: 0 Addr: 48-51 YWIN4 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) YWIN5 Register (Bank 0, Address 52-55) Figure 162: YWIN5 Register Bank: 0 Addr: 52-55 YWIN5 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 115 Document Feedback 8.2.28 CMV50000 Register Description YWIN6 Register (Bank 0, Address 56-59) Figure 163: YWIN6 Register 8.2.29 Bank: 0 Addr: 56-59 YWIN6 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) YWIN7 Register (Bank 0, Address 60-63) Figure 164: YWIN7 Register 8.2.30 Bank: 0 Addr: 60-63 YWIN7 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) YWIN8 Register (Bank 0, Address 64-67) Figure 165: YWIN8 Register Bank: 0 Addr: 64-67 YWIN8 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 116 Document Feedback 8.2.31 CMV50000 Register Description Bank: 0 Addr: 64-67 YWIN8 Bit Bit Name Default Access Bit Description [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) YWIN9 Register (Bank 0, Address 68-71) Figure 166: YWIN9 Register 8.2.32 Bank: 0 Addr: 68-71 YWIN9 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS) GDIG_RE_CE Register (Bank 0, Address 72) Figure 167: GDIG_RE_CE Register Bank: 0 Addr: 72 GDIG_RE_CE Bit Bit Name Default Access Bit Description [7:0] GDIG_RE_CE 15 SYNC Sets the digital gain for the pixels in the even rows and even columns Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 117 Document Feedback 8.2.33 CMV50000 Register Description GDIG_RE_CO Register (Bank 0, Address 73) Figure 168: GDIG_RE_CO Register 8.2.34 Bank: 0 Addr: 73 GDIG_RE_CO Bit Bit Name Default Access Bit Description [7:0] GDIG_RE_CO 15 SYNC Sets the digital gain for the pixels in the even rows and odd columns GDIG_RO_CE Register (Bank 0, Address 74) Figure 169: GDIG_RO_CE Register 8.2.35 Bank: 0 Addr: 74 GDIG_RO_CE Bit Bit Name Default Access Bit Description [7:0] GDIG_RO_CE 15 SYNC Sets the digital gain for the pixels in the odd rows and even columns GDIG_RO_CO Register (Bank 0, Address 75) Figure 170: GDIG_RO_CO Register Bank: 0 Addr: 75 GDIG_RO_CO Bit Bit Name Default Access Bit Description [7:0] GDIG_RO_CO 15 SYNC Sets the digital gain for the pixels in the odd rows and odd columns Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 118 Document Feedback 8.2.36 CMV50000 Register Description EOB_TARGET Register (Bank 0, Address 76-77) Figure 171: EOB_TARGET Register 8.2.37 Bank: 0 Addr: 76-77 EOB_TARGET Bit Bit Name Default Access Bit Description [13:0] EOB_TARGET 32 SYNC Sets the target black level value in DN 128: 128DN Access Bit Description SYNC Sets the analog gain. Non-binning / binning mode: 255 / 223: x1 243 / 211: x2 241 / 209: x4 GANA Register (Bank 0, Address 78) Figure 172: GANA Register Bank: 0 Addr: 78 GANA Bit Default [7:0] 8.2.38 Bit Name GANA 0 TRAINING_WORD Register (Bank 0, Address 79-80) Figure 173: TRAINING_WORD Register Bank: 0 Addr: 79-80 TRAINING_WORD Bit Bit Name Default Access Bit Description [13:0] TRAINING_WORD 85 - The training word on the data outputs Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 119 Document Feedback 8.2.39 CMV50000 Register Description TEST_LVDS Register (Bank 0, Address 81) Figure 174: TEST_LVDS Register Bank: 0 Addr: 81 TEST_LVDS Bit Default [2:0] 8.2.40 Bit Name TEST_LVDS 0 Access Bit Description - Sets the output test mode. 0: Normal data output 1: Continuous training word 2: Gradient test image 3: LFSR test image OTP_CONTROL Register (Bank 0, Address 97) Figure 175: OTP_CONTROL Register 8.2.41 Bank: 0 Addr: 97 OTP_CONTROL Bit Bit Name Default Access Bit Description [3:0] OTP_CONTROL 0 - OTP control input OTP_A Register (Bank 0, Address 98) Figure 176: OTP_A Register Bank: 0 Addr: 98 OTP_A Bit Bit Name Default Access Bit Description [6:0] OTP_A 0 - OTP address input Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 120 Document Feedback 8.2.42 CMV50000 Register Description OTP_DOUT Register (Bank 0, Address 101-102) Figure 177: OTP_DOUT Register 8.2.43 Bank: 0 Addr: 101-102 OTP_DOUT Bit Bit Name Default Access Bit Description [15:0] OTP_DOUT 0 RO OTP data output TSENS1_CONTROL Register (Bank 0, Address 103) Figure 178: TSENS1_CONTROL Register Bank: 0 Addr: 103 TSENS1_CONTROL Bit Default [0] 8.2.44 Bit Name PDN 0 Access Bit Description - Temperature sensor power state: 0: Down 1: Up [1] RSTN 0 - Temperature sensor reset state: 0: Assert reset 1: Release reset [7:2] DCORRECT 32 - Temperature sensor correction value TSENS1_OUTPUT Register (Bank 0, Address 104-105) Figure 179: TSENS1_OUTPUT Register Bank: 0 Addr: 104-105 TSENS1_OUTPUT Bit Bit Name Default Access Bit Description [9:0] TSENS1_OUTPUT 0 RO Temperature sensor output Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 121 Document Feedback 8.2.45 CMV50000 Register Description PLL1_ENABLE Register (Bank 0, Address 106) Figure 180: PLL1_ENABLE Register 8.2.46 Bank: 0 Addr: 106 PLL1_ENABLE Bit Bit Name Default Access Bit Description [0] PLL1_ENABLE 0 RST 0: Disable PLL1 1: Enable PLL1 PLL1_PRE_DIV Register (Bank 0, Address 107) Figure 181: PLL1_PRE_DIV Register Bank: 0 Addr: 107 PLL1_PRE_DIV Bit Default [1:0] 8.2.47 Bit Name PLL1_PRE_DIV 0 Access Bit Description RST Set by CLK_IN frequency: 0: 6MHz – 12MHz 1: 12MHz – 24MHz 2: 24MHz – 48MHz 3: 48MHz – 96MHz PLL1_NDIV Register (Bank 0, Address 108) Figure 182: PLL1_NDIV Register Bank: 0 Addr: 108 PLL1_NDIV Bit Bit Name Default Access Bit Description [7:0] PLL1_NDIV 0 RST PLL1 divider parameter Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 122 Document Feedback 8.2.48 CMV50000 Register Description PLL1_CLKOUT_SEL Register (Bank 0, Address 109) Figure 183: PLL1_CLKOUT_SEL Register Bank: 0 Addr: 109 PLL1_CLKOUT_SEL Bit Default [1:0] 8.2.49 Bit Name PLL1_CLKOUT_SEL 0 Access Bit Description RST Set by target output data rate: 0: 460 – 830Mbit/s 1: 230 – 460Mbit/s 2: 120 – 230Mbit/s PLL2_ENABLE Register (Bank 0, Address 110) Figure 184: PLL2_ENABLE Register 8.2.50 Bank: 0 Addr: 110 PLL2_ENABLE Bit Bit Name Default Access Bit Description [0] PLL2_ENABLE 0 RST 0: Disable PLL1 1: Enable PLL1 PLL2_NDIV Register (Bank 0, Address 112) Figure 185: PLL2_NDIV Register Bank: 0 Addr: 112 PLL2_NDIV Bit Bit Name Default Access Bit Description [7:0] PLL2_NDIV 0 RST PLL2 divider parameter Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 123 Document Feedback 8.2.51 CMV50000 Register Description PLL_CLKDIV_RSTN Register (Bank 0, Address 114) Figure 186: PLL_CLKDIV_RSTN Register Bank: 0 Addr: 114 PLL_CLKDIV_RSTN Bit Default [0] 8.2.52 Bit Name PLL_CLKDIV_RSTN 0 Access Bit Description - 0: Assert CLK_IN divider reset 1: Release CLK_IN divider reset PLL_LOCK Register (Bank 0, Address 115) Figure 187: PLL_LOCK Register 8.2.53 Bank: 0 Addr: 115 PLL_LOCK Bit Bit Name Default Access Bit Description [0] PLL1_LOCK 0 RO 0: PLL1 out of lock 1: PLL1 in lock [1] PLL2_LOCK 0 RO 0: PLL2 out of lock 1: PLL2 in lock VERSION_ID Register (Bank 0, Address 116) Figure 188: VERSION_ID Register Bank: 0 Addr: 116 VERSION_ID Bit Bit Name Default Access Bit Description [7:0] VERSION_ID 1 RO Sensor revision number Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 124 Document Feedback 8.2.54 CMV50000 Register Description NO_SHUTTER_LAG Register (Bank 0, Address 117) Figure 189: NO_SHUTTER_LAG Register 8.2.55 Bank: 0 Addr: 117 NO_SHUTTER_LAG Bit Bit Name Default Access Bit Description [0] NO_SHUTTER_LAG 0 DC 0: Enable shutter lag 1: Disable shutter lag DUAL_EXP_GROUPING Register (Bank 0, Address 118) Figure 190: DUAL_EXP_GROUPING Register Bank: 0 Addr: 118 DUAL_EXP_GROUPING Bit Default [0] 8.2.56 Bit Name DUAL_EXP_GROUPING 0 Access DC Bit Description Dual exposure column grouping: 0: Default (monochrome) 1: Paired (color) GRAN_GLOB Register (Bank 1, Address 5) Figure 191: GRAN_GLOB Register Bank: 1 Addr: 5 GRAN_GLOB Bit Bit Name Default Access Bit Description [7:0] GRAN_GLOB 1 - Sets shutter timing granularity Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 125 Document Feedback 8.2.57 CMV50000 Register Description CLKGEN_CFG Register (Bank 1, Address 6) Figure 192: CLKGEN_CFG Register 8.2.58 Bank: 1 Addr: 6 CLKGEN_CFG Bit Bit Name Default Access [0] 0 RST [2:1] PHASE 1 RST [3] 1 RST [6:4] 0 RST Bit Description Sets the phase of the output clock to the data. 0: 0° 1: 90° 2: 180° 3: 270° EOB_OFFSET_FINE Register (Bank 1, Address 38-39) Figure 193: EOB_OFFSET_FINE Register Bank: 1 Addr: 38-39 EOB_OFFSET_FINE Bit Default [15:0] Bit Name EOB_OFFSET_FINE Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 0 Access - Bit Description Fine tunes the OB offset depending on gain: 32920: Analog gain x1 33083: Analog gain x2 33418: Analog gain x4 138 │ 126 Document Feedback 8.2.59 CMV50000 Register Description EOB_BYPASS Register (Bank 1, Address 42) Figure 194: EOB_BYPASS Register Bank: 1 Addr: 42 EOB_BYPASS Bit Default [0] 8.2.60 Bit Name EOB_BYPASS 0 Access Bit Description - Enables Optical Black Correction (OBC) 0: OBC on (recommended) 1: OBC off EOB_BYPASS_VALUE Register (Bank 1, Address 43-44) Figure 195: EOB_BYPASS_VALUE Register 8.2.61 Bank: 1 Addr: 43-44 EOB_BYPASS_VALUE Bit Bit Name Default Access Bit Description [13:0] EOB_BYPASS_VALUE 0 - Sets the black level at the ADC (with OBC off) NR_DUMMIES Register (Bank 1, Address 46) Figure 196: NR_DUMMIES Register Bank: 1 Addr: 46 NR_DUMMIES Bit Bit Name Default Access Bit Description [3:0] NR_DUMMIES 0 - Sets the number of dummy rows in pipeline mode Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 127 Document Feedback 8.2.62 CMV50000 Register Description TDIG Register (Bank 1, Address 99) Figure 197: TDIG Register Bank: 1 Addr: 99 TDIG Bit Default [4:0] 8.2.63 Bit Name DMUX1_SEL 0 Access Bit Description - Sets pin TDIGO1 function: 0: None 1: PLL_1_LOCK 2: PLL_2_LOCK 5: CLK_PIX 6: INT_REQ_FRAME 7: INT_REQ_EXP(L) 12: GLOB start 14: CTR_EXP(L) TG_LENGTH Register (Bank 1, Address 110-111) Figure 198: TG_LENGTH Register 8.2.64 Bank: 1 Addr: 110-111 TG_LENGTH Bit Bit Name Default Access Bit Description [13:0] TG_LENGTH 0 DC Sets shutter timing SHUTTER_LAG Register (Bank 1, Address 114-115) Figure 199: SHUTTER_LAG Register Bank: 1 Addr: 114-115 SHUTTER_LAG Bit Bit Name Default Access Bit Description [13:0] SHUTTER_LAG 0 DC Sets the shutter lag Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 128 Document Feedback 8.2.65 CMV50000 Register Description PLL1_DISABLE_CLKOUT Register (Bank 3, Address 49) Figure 200: PLL1_DISABLE_CLKOUT Register Bank: 1 Addr: 49 SHUTTER_LAG Bit Default [0] Bit Name PLL1_DISABLE_CLKOUT Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 0 Access Bit Description RST Disables the PLL1 clock output for soft-reset. 0: Enabled 1: Disabled 138 │ 129 Document Feedback 9 Application Information 9.1 Color Filter CMV50000 Application Information A color version of the CMV50000 has color filters applied with a Bayer pattern. The first pixel read-out, pixel(0, 0), is the bottom left one and has a blue filter. Figure 201 : Bayer Color Filter 9.2 Socket To avoid putting the sensor through the soldering heat (stressing the color filters and micro-lenses), it is advised to use a socket and place the sensor after the solder stage. Sockets for this device are available from Andon Electronics (www.andonelectronics.com) in both SMD (p/n: 575-20-19A-14193M-R27-L14) and TH (p/n: 575-20-19A-141-01M-R27-L14) configuration. Contact Andon Electronics directly for more information. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 130 Document Feedback 9.3 CMV50000 Application Information Pin Layout Figure 202 : Pin Layout from Top View Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 131 Document Feedback 10 CMV50000 Package Drawings & Markings Package Drawings & Markings Figure 203: 141-PGA Package Outline Drawing RoHS (1) (2) (3) (4) (5) (6) (7) (8) Green All dimensions are in millimeters. Angles in degrees. Au plate 0.75µm min. over 2.0µm min Ni Unplated are on tip shall be less than Ø0.30 within 0.50 max from pin tip Materials: 1. Package: Alumina ceramic; 2. Pin: Alloy42; 3: Standoff pin: Alloy42 Unless otherwise specified tolerances are ±1%; N.L.T: x.x ±0.25; x.xx ±0.13 The package has a marking on top, in the left bottom corner, at pin A1 position This package contains no lead (Pb). This drawing is subject to change without notice. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 132 Document Feedback CMV50000 Package Drawings & Markings Figure 204: 141-PGA Assembly Outline Drawing (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) Die size: 39.4mm x 31.1mm, relative to the die SEAL ring edge, the dimensions after dicing will be typically larger. Optical center to die and package center offset: in X = 0, in Y = 628µm Die positioned in the middle of the package cavity Die placement accuracy: ±100µm Die rotation in package: max ±0.2° Die tilt towards cavity bottom: max ±0.1° Distance from the cavity bottom to the photosensitive pixel layer (top of the die): 0.86 ±0.06mm Distance from the top of the glass to the photosensitive pixel layer (top of the die): 1.65 ±0.20mm Glass lid positioned in the middle of the package; Glass size tolerance: ±0.1mm Glass thickness: 0.7 ±0.05mm Glass lid placement accuracy: ±200µm All dimensions are in millimeters. Angles in degrees. This package contains no lead (Pb). This drawing is subject to change without notice. The devices come covered with a heat resistant protective tape The 4 notches are not to be mechanically stressed! They can be used to measure the level and tilt of the cavity bottom (die attach surface). Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 133 Document Feedback CMV50000 Package Drawings & Markings Figure 205 : 141-PGA Package Marking/Code Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 134 Document Feedback 11 CMV50000 Packing Information Packing Information The devices are shipped in JEDEC PGA matrix trays. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 135 Document Feedback 12 CMV50000 Soldering Information Soldering Information Attention Image sensors with color filter arrays (CFA) and micro lenses are especially sensitive to high temperatures. Prolonged heating at elevated temperatures may result in deterioration of the optical performance of the sensor. A socket (see 9.2) is the safest way to avoid any thermal stress. When not using a socket, to avoid heating up the device we recommend to use manual hand soldering. Wave soldering can be used with precautions (see below). Reflow soldering is not recommended. Manual soldering: Use partial heating method and use a soldering iron with temperature control. The soldering iron tip temperature is not to exceed 350°C with a 270°C maximum pin temperature. Touch for a 2 seconds maximum duration per pin. Avoid touching and global heating of the ceramic package during soldering. Failure to do so may alter device performance and reliability. Wave soldering: Wave solder dipping can cause damage to the glass and harm the imaging capability of the device. Avoid the solder to come in contact with the glass or ceramic body. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 136 Document Feedback 13 CMV50000 Revision Information Revision Information ● ● Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Datasheet (discontinued) Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Changes from previous version to current revision v3-01 Page Update Assembly Outline Drawing details 7, 8 (no physical change) 131 OTP Memory added 92-94 Remove IO logic level for sublvds 15 Part nr added 5 Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. Correction of typographical errors is not explicitly mentioned. Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 137 Document Feedback 14 CMV50000 Legal Information Legal Information Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. RoHS Compliant & ams Green Statement RoHS Compliant: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Headquarters Please visit our website at www.ams.com ams AG Buy our products or get free samples online at www.ams.com/Products Tobelbader Strasse 30 Technical Support is available at www.ams.com/Technical-Support 8141 Premstaetten Provide feedback about this document at www.ams.com/Document-Feedback Austria, Europe For sales offices, distributors and representatives go to www.ams.com/Contact Tel: +43 (0) 3136 500 0 For further information and requests, e-mail us at ams_sales@ams.com Datasheet • PUBLIC DS000522 • v3-01 • 2019-Dec-20 138 │ 138