74HCT259D,652

74HC259; 74HCT259 8-bit addressable latch Rev. 7 — 2 September 2020 Product data sheet 1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states. In memory mode, all latches retain their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the D input and all other outputs are LOW. In the reset mode, all outputs are forced LOW and unaffected by the data or address inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • • • • • • • Wide supply voltage range from 2.0 V to 6.0 V Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) Combined demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder Input levels: • For 74HC259: CMOS level • For 74HCT259: TTL level ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22E exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 74HC259; 74HCT259 Nexperia 8-bit addressable latch 3. Ordering information Table 1. Ordering information Type number Package 74HC259D Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 74HCT259D 74HC259PW 74HCT259PW 74HC259BQ 74HCT259BQ 4. Functional diagram 13 Z9 15 G8 14 1 LE Q0 D Q1 Q2 1 2 3 Q3 A0 Q4 A1 Q5 A2 Q6 MR 15 Fig. 1. 9,10D DX 14 13 G10 Q7 4 2 5 3 6 0 0 G 2 0 7 7 1 C10 8R 5 1 6 2 7 3 9 9 4 10 10 5 11 12 11 6 12 7 mna573 4 mna572 Logic symbol Fig. 2. 1 A0 2 A1 3 A2 IEC logic symbol 1-of-8 DECODER 8 LATCHES Q0 4 Q1 5 Q2 6 Q3 7 Q4 9 14 LE Q5 10 15 MR Q6 11 13 D Q7 12 mna571 Fig. 3. Functional diagram 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 2 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch 5. Pinning information 5.1. Pinning 1 A0 terminal 1 index area A1 2 15 MR A2 3 14 LE Q0 4 13 D Q1 5 12 Q7 Q2 6 11 Q6 Q3 7 10 Q5 GND 8 9 3 14 LE 4 13 D Q1 5 12 Q7 Q2 6 Q3 7 GND(1) 11 Q6 10 Q5 001aaj445 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Q4 001aaj444 Fig. 4. A2 Q0 9 16 VCC 15 MR Q4 1 2 8 A0 A1 GND 74HC259 74HCT259 16 VCC 74HC259 74HCT259 Pin configuration SOT109-1 (SO16) and SOT403-1 (TSSOP16) Fig. 5. Pin configuration SOT763-1 (DHVQFN16) 5.2. Pin description Table 2. Pin description Symbol Pin Description A0, A1, A2 1, 2, 3 address input Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output GND 8 ground (0 V) D 13 data input LE 14 latch enable input (active LOW) MR 15 conditional reset input (active LOW) VCC 16 supply voltage 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 3 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. Operating mode Input Output MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L H X X X X L L L L L L L L L Demultiplexer (active HIGH 8-channel) L decoder (when D = H) L L d L L L Q=d L L L L L L L L d H L L L Q=d L L L L L L L d L H L L L Q=d L L L L L L L d H H L L L L Q=d L L L L L L d L L H L L L L Q=d L L L L L d H L H L L L L L Q=d L L L L d L H H L L L L L L Q=d L Reset (clear) L L d H H H L L L L L L L Q=d Memory (no action) H H X X X X q0 q1 q2 q3 q4 q5 q6 q7 Addressable latch H L d L L L Q = d q1 q2 q3 q4 q5 q6 q7 H L d H L L q0 Q = d q2 q3 q4 q5 q6 q7 H L d L H L q0 q1 Q = d q3 q4 q5 q6 q7 H L d H H L q0 q1 q2 Q = d q4 q5 q6 q7 H L d L L H q0 q1 q2 q3 Q = d q5 q6 q7 H L d H L H q0 q1 q2 q3 q4 Q = d q6 q7 H L d L H H q0 q1 q2 q3 q4 q5 Q = d q7 H L d H H H q0 q1 q2 q3 q4 q5 q6 Q=d Table 4. Operating mode select table H = HIGH voltage level; L = LOW voltage level. LE MR Mode L H Addressable latch mode H H Memory mode L L Demultiplexer mode H L Reset mode 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 4 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC supply voltage -0.5 +7.0 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V IO output current VO = -0.5 V to VCC + 0.5 V [1] - ±20 mA - ±25 mA ICC supply current - +70 mA IGND ground current -70 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Conditions Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C. 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC259 74HCT259 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature °C Δt/ΔV input transition rise and fall rate -40 - +125 -40 - +125 VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V 74HC259 VIH VIL HIGH-level input voltage LOW-level input voltage 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 5 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch Symbol Parameter VOH VOL Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VI = VIH or VIL HIGH-level output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL LOW-level output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1 - ±1 μA II input leakage current VI = VCC or GND; VCC = 6.0 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 μA CI input capacitance - 3.5 - - - - - pF 74HCT259 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH VI = VIH or VIL; VCC = 4.5 V HIGH-level output voltage IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V 3.98 4.32 - 3.84 - 3.7 - V - 0 0.1 - 0.1 - 0.1 V - 0.15 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1 - ±1 μA - - 8.0 - 80 - 160 μA pin An, LE - 150 540 - 675 - 735 μA pin D - 120 432 - 540 - 588 μA pin MR - 75 270 - 338 - 368 μA - 3.5 - - - - - pF IO = -4.0 mA VOL VI = VIH or VIL; VCC = 4.5 V LOW-level output voltage IO = 20 μA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V ΔICC VI = VCC - 2.1 V; IO = 0 A; additional supply current other inputs at VCC or GND; VCC = 4.5 V to 5.5 V CI input capacitance 74HC_HCT259 Product data sheet VI = VCC or GND; VCC = 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 6 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 12. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max 74HC259 tpd propagation delay D to Qn; see Fig. 6 [2] VCC = 2.0 V - 58 185 - 230 - 280 ns VCC = 4.5 V - 21 37 - 46 - 56 ns VCC = 5.0 V; CL = 15 pF - 18 - - - - - ns VCC = 6.0 V - 17 31 - 39 - 48 ns VCC = 2.0 V - 58 185 - 230 - 280 ns VCC = 4.5 V - 21 37 - 46 - 56 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 17 31 - 39 - 48 ns VCC = 2.0 V - 55 170 - 215 - 255 ns VCC = 4.5 V - 20 34 - 43 - 51 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 29 - 37 - 43 ns VCC = 2.0 V - 50 155 - 195 - 235 ns VCC = 4.5 V - 18 31 - 39 - 47 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 40 ns VCC = 2.0 V - 19 75 - 95 - 119 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 70 17 - 90 - 105 - ns VCC = 4.5 V 14 6 - 18 - 21 - ns VCC = 6.0 V 12 5 - 15 - 18 - ns VCC = 2.0 V 70 17 - 90 - 105 - ns VCC = 4.5 V 14 6 - 18 - 21 - ns VCC = 6.0 V 12 5 - 15 - 18 - ns VCC = 2.0 V 80 19 - 100 - 120 - ns VCC = 4.5 V 16 7 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns An to Qn; see Fig. 7 [2] LE to Qn; see Fig. 8 tPHL tt tW HIGH to LOW propagation delay transition time pulse width [2] MR to Qn; see Fig. 9 see Fig. 8 [3] LE HIGH or LOW; see Fig. 8 MR LOW; see Fig. 9 tsu set-up time 74HC_HCT259 Product data sheet D, An to LE; see Fig. 10 and Fig. 11 All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 7 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max th hold time Min Max Min Max D to LE; see Fig. 10 and Fig. 11 VCC = 2.0 V 0 -19 - 0 - 0 - ns VCC = 4.5 V 0 -6 - 0 - 0 - ns VCC = 6.0 V 0 -5 - 0 - 0 - ns VCC = 2.0 V 2 -11 - 2 - 2 - ns VCC = 4.5 V 2 -4 - 2 - 2 - ns VCC = 6.0 V 2 -3 - 2 - 2 - ns - 19 - - - - - pF VCC = 4.5 V - 23 39 - 49 - 59 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns - 25 41 62 ns - 20 - - - - - ns VCC = 4.5 V - 22 38 - 48 - 57 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns VCC = 4.5 V - 23 39 - 49 - 59 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns - 7 15 - 19 - 22 ns 19 11 - 24 - 29 - ns 18 10 - 23 - 27 - ns 17 10 - 21 - 26 - ns 0 -8 - 0 - 0 - ns 0 -4 - 0 - 0 - ns An to LE; see Fig. 10 and Fig. 11 CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC [4] 74HCT259 tpd propagation delay D to Qn; see Fig. 6 [2] An to Qn; see Fig. 7 [2] VCC = 4.5 V VCC = 5.0 V; CL = 15 pF LE to Qn; see Fig. 8 tPHL tt HIGH to LOW propagation delay MR to Qn; see Fig. 9 transition time see Fig. 8 [2] [3] VCC = 4.5 V tW pulse width 51 LE HIGH or LOW; see Fig. 8 VCC = 4.5 V MR LOW; see Fig. 9 VCC = 4.5 V tsu set-up time D, An to LE; see Fig. 10 and Fig. 11 th hold time D to LE; see Fig. 10 and Fig. 11 VCC = 4.5 V VCC = 4.5 V An to LE; see Fig. 10 and Fig. 11 VCC = 4.5 V 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 8 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max CPD [1] [2] [3] [4] power dissipation capacitance fi = 1 MHz; VI = GND to VCC - 1.5 V [4] - 19 - Min Max Min Max - - - - pF Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of the outputs. 10.1. Waveforms and test circuit VCC D input VM GND tPHL tPLH VOH VM Qn output VOL 001aah123 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. Data input to output propagation delays VCC VM An input GND tPHL tPLH VOH VM Qn output VOL 001aah122 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Address input to output propagation delays 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 9 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch VCC D input GND VCC VM LE input GND tW tPHL VOH tPLH VY VM Qn output VX VOL tTHL tTLH 001aaj446 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. Enable input to output propagation delays and pulse width VCC MR input VM GND tW tPHL VOH VM Qn output VOL 001aah124 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. Master reset input to output propagation delays VCC LE input VM GND tsu tsu th VCC th VM D input GND VOH Qn output Q=D VM VOL Q=D 001aah125 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 10. Data input to latch enable input set-up and hold times 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 10 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch VCC An input VM ADDRESS STABLE GND tsu th VCC LE input VM GND 001aah126 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 11. Address input to latch enable input set-up and hold times Table 9. Measurement points Input Type Output VM VM VX VY 74HC259 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT259 1.3 V 1.3 V 0.1VCC 0.9VCC VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI VCC VO DUT RT RL S1 open CL 001aad983 Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig. 12. Test circuit for measuring switching times Table 10. Test data Type Input S1 position Load VI tr, tf CL RL tPHL, tPLH 74HC259 VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HCT259 3V 6 ns 15 pF, 50 pF 1 kΩ open 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 11 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 13. Package outline SOT109-1 (SO16) 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 12 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 14. Package outline SOT403-1 (TSSOP16) 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 13 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm B D A A E A1 c detail X terminal 1 index area terminal 1 index area C e1 e b 2 7 y y1 C v M C A B w M C L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig. 15. Package outline SOT763-1 (DHVQFN16) 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 14 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch 12. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT259 v.7 20200902 Product data sheet - 74HC_HCT259 v.6 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74HC259DB and 74HCT259DB (SOT338-1/SSOP16) removed. Section 2 updated. Table 5: Derating values for Ptot total power dissipation have been updated. 74HC_HCT259 v.6 20160202 Modifications: • 74HC_HCT259 v.5 20120807 Modifications: • • 74HC_HCT259 v.5 Product data sheet - 74HC_HCT259 v.4 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 20090225 Modifications: • • 74HC_HCT259 v.3 20090108 Product data sheet - 74HC_HCT259 v.3 Added type number 74HC259N and 74HCT259N (DIP16 package) Added type number 74HC259DB and 74HCT259DB (SSOP16 package) 74HC_HCT259_CNV v.2 19970828 Product data sheet - Type numbers 74HC259N and 74HCT259N (SOT38-4) removed. 74HC_HCT259 v.4 74HC_HCT259 Product data sheet Product data sheet - 74HC_HCT259_CNV v.2 Product specification - - All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 15 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC_HCT259 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 16 / 17 74HC259; 74HCT259 Nexperia 8-bit addressable latch Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit........................................ 9 11. Package outline........................................................ 12 12. Abbreviations............................................................ 15 13. Revision history........................................................15 14. Legal information......................................................16 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 2 September 2020 74HC_HCT259 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 September 2020 © Nexperia B.V. 2020. All rights reserved 17 / 17