HEF4094B-Q100
8-stage shift-and-store register
Rev. 5 — 8 July 2021
Product data sheet
1. General description
The HEF4094B-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register
and 3-state outputs. Both the shift and storage register have separate clocks. The device features
a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the
LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions
of the CP input to allow cascading when clock edges are fast. The same data is available at QS2
on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow.
The data in the shift register is transferred to the storage register when the STR input is HIGH.
Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH.
A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE
input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VDD.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
•
•
•
•
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Wide supply voltage range from 3.0 to 15.0 V
CMOS low power dissipation
High noise immunity
Standardized symmetrical output characteristics
ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from -40 °C to +125 °C.
Type number
Package
Name
Description
Version
HEF4094BT-Q100
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
HEF4094BTT-Q100
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
HEF4094B-Q100
Nexperia
8-stage shift-and-store register
4. Functional diagram
2
3
1
15
D
8-STAGE SHIFT
REGISTER
CP
QS2
QS1
STR
3
1
CP
STR
10
9
2
D
8-BIT STORAGE
REGISTER
OE
3-STATE OUTPUTS
OE
QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7
4
Fig. 1.
5
6
7
14
13
12
11
Functional diagram
Fig. 2.
STAGE 0
D
15
001aaf119
D
D
9
QS2
10
QP0
4
QP1
5
QP2
6
QP3
7
QP4
14
QP5
13
QP6
12
QP7
11
001aaf111
Logic symbol
STAGES 1 TO 6
Q
QS1
STAGE 7
Q
CP
D
Q
QS1
CP
FF 0
CP
D
FF 7
CP
Q
QS2
LE
LATCH
D
Q
D
Q
LE
LE
LATCH 0
LATCH 7
STR
OE
QP0
Fig. 3.
QP1
QP2
QP3
QP4
QP5
QP6
QP7
001aag799
Logic diagram
HEF4094B_Q100
Product data sheet
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HEF4094B-Q100
Nexperia
8-stage shift-and-store register
5. Pinning information
5.1. Pinning
HEF4094B
STR
1
16 VDD
D
2
15 OE
CP
3
14 QP4
QP0
4
13 QP5
QP1
5
12 QP6
QP2
6
11 QP7
QP3
7
10 QS2
VSS
8
9
QS1
aaa-007666
Fig. 4.
Pin configuration SOT109-1 (SO16) and SOT403-1 (TSSOP16)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
STR
1
strobe input
D
2
data input
CP
3
clock input
QP0 to QP7
4, 5, 6, 7, 14, 13, 12, 11
parallel output
VSS
8
ground supply voltage
QS1
9
serial output
QS2
10
serial output
OE
15
output enable input
VDD
16
supply voltage
HEF4094B_Q100
Product data sheet
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Rev. 5 — 8 July 2021
©
Nexperia B.V. 2021. All rights reserved
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HEF4094B-Q100
Nexperia
8-stage shift-and-store register
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = HIGH-impedance OFF-state; NC = no change;
↑ = positive-going transition; ↓ = negative-going transition;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Inputs
Parallel outputs
Serial outputs
CP
OE
STR
D
QP0
QPn
QS1
QS2
↑
L
X
X
Z
Z
Q6S
NC
↓
L
X
X
Z
Z
NC
Q7S
↑
H
L
X
NC
NC
Q6S
NC
↑
H
H
L
L
QPn -1
Q6S
NC
↑
H
H
H
H
QPn -1
Q6S
NC
↓
H
H
H
NC
NC
NC
Q7S
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
Z-state
OUTPUT QP0
INTERNAL Q6S (FF 6)
Z-state
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
001aaf117
At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the
QSn outputs.
Fig. 5.
Timing diagram
HEF4094B_Q100
Product data sheet
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Rev. 5 — 8 July 2021
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4 / 15
HEF4094B-Q100
Nexperia
8-stage shift-and-store register
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min
Max
Unit
-0.5
+18
V
-
±10
mA
-0.5
VDD + 0.5
-
±10
mA
VDD
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
II/O
input/output current
-
±10
mA
IDD
supply current
-
50
mA
Tstg
storage temperature
-65
+150
°C
Tamb
ambient temperature
-40
+125
°C
Ptot
total power dissipation
-
500
mW
P
power dissipation
-
100
mW
[1]
VI < -0.5 V or VI > VDD + 0.5 V
VO < -0.5 V or VO > VDD + 0.5 V
[1]
per output
V
For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
3
-
15
V
VDD
supply voltage
VI
input voltage
0
-
VDD
V
Tamb
ambient temperature
in free air
-40
-
+125
°C
Δt/ΔV
input transition rise and fall rate
VDD = 5 V
-
-
3.75
μs/V
VDD = 10 V
-
-
0.5
μs/V
VDD = 15 V
-
-
0.08
μs/V
HEF4094B_Q100
Product data sheet
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Rev. 5 — 8 July 2021
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5 / 15
HEF4094B-Q100
Nexperia
8-stage shift-and-store register
9. Static characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
VIH
VIL
VOH
VOL
IOH
IOL
HIGH-level input |IO| < 1 μA
voltage
LOW-level input |IO| < 1 μA
voltage
HIGH-level
output voltage
|IO| < 1 μA
VDD
Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit
Min
Max
Min
Max
Min
Max
Min
Max
3.5
-
3.5
-
3.5
-
3.5
-
V
10 V
7.0
-
7.0
-
7.0
-
7.0
-
V
15 V
11.0
-
11.0
-
11.0
-
11.0
-
V
5V
-
1.5
-
1.5
-
1.5
-
1.5
V
10 V
-
3.0
-
3.0
-
3.0
-
3.0
V
15 V
-
4.0
-
4.0
-
4.0
-
4.0
V
5V
4.95
-
4.95
-
4.95
-
4.95
-
V
10 V
9.95
-
9.95
-
9.95
-
9.95
-
V
15 V
14.95
-
14.95
-
14.95
-
14.95
-
V
5V
-
0.05
-
0.05
-
0.05
-
0.05
V
10 V
-
0.05
-
0.05
-
0.05
-
0.05
V
5V
LOW-level
output voltage
|IO| < 1 μA
15 V
-
0.05
-
0.05
-
0.05
-
0.05
V
HIGH-level
output current
VO = 2.5 V
5V
-
-1.7
-
-1.4
-
-1.1
-
-1.1
mA
VO = 4.6 V
5V
-
-0.64
-
-0.5
-
-0.36
-
-0.36
mA
VO = 9.5 V
10 V
-
-1.6
-
-1.3
-
-0.9
-
-0.9
mA
VO = 13.5 V
15 V
-
-4.2
-
-3.4
-
-2.4
-
-2.4
mA
VO = 0.4 V
5V
0.64
-
0.5
-
0.36
-
0.36
-
mA
VO = 0.5 V
10 V
1.6
-
1.3
-
0.9
-
0.9
-
mA
VO = 1.5 V
15 V
4.2
-
3.4
-
2.4
-
2.4
-
mA
QPn output
is HIGH;
VO = 15 V
15 V
-
0.4
-
0.4
-
12
-
12
μA
15 V
-
±0.1
-
±0.1
-
±1.0
-
±1.0
μA
5V
-
5
-
5
-
150
-
150
μA
10 V
-
10
-
10
-
300
-
300
μA
15 V
-
20
-
20
-
600
-
600
μA
-
-
-
7.5
-
-
-
-
pF
LOW-level
output current
IOZ
OFF-state
output current
II
input leakage
current
IDD
supply current
CI
Conditions
input
capacitance
HEF4094B_Q100
Product data sheet
all valid input
combinations;
IO = 0 A
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HEF4094B-Q100
Nexperia
8-stage shift-and-store register
10. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Fig. 10; unless otherwise specified.
Symbol Parameter
Conditions
VDD
tPHL
CP to QS1;
see Fig. 6
5V
HIGH to LOW
propagation delay
CP to QS2;
see Fig. 6
CP to QPn;
see Fig. 6
STR to QPn;
see Fig. 7
tPLH
LOW to HIGH
propagation delay,
CP to QS1;
see Fig. 6
CP to QS2;
see Fig. 6
CP to QPn;
see Fig. 6
STR to QPn;
see Fig. 7
tt
tPZH
tPZL
tPHZ
tPLZ
OFF-state to HIGH
propagation delay
OE to QPn;
see Fig. 8
OFF-state to LOW
propagation delay
OE to QPn;
see Fig. 8
HIGH to OFF-state
propagation delay
OE to QPn;
see Fig. 8
LOW to OFF-state
propagation delay
HEF4094B_Q100
Product data sheet
OE to QPn;
see Fig. 8
[1] 108 ns + (0.55 ns/pF)CL
Min
Typ
Max
Unit
-
135
270
ns
65
130
ns
10 V
54 ns + (0.23 ns/pF)CL
-
15 V
42 ns + (0.16 ns/pF)CL
-
50
100
ns
5V
78 ns + (0.55 ns/pF)CL
-
105
210
ns
10 V
39 ns + (0.23 ns/pF)CL
-
50
100
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
5V
138 ns + (0.55 ns/pF)CL
-
165
330
ns
10 V
64 ns + (0.23 ns/pF)CL
-
75
150
ns
15 V
47 ns + (0.16 ns/pF)CL
-
55
110
ns
5V
83 ns + (0.55 ns/pF)CL
-
110
220
ns
10 V
39 ns + (0.23 ns/pF)CL
-
50
100
ns
15 V
27 ns + (0.16 ns/pF)CL
-
35
70
ns
5V
[1] 78 ns + (0.55 ns/pF)CL
-
105
210
ns
10 V
39 ns + (0.23 ns/pF)CL
-
50
100
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
5V
78 ns + (0.55 ns/pF)CL
-
105
210
ns
10 V
39 ns + (0.23 ns/pF)CL
-
50
100
ns
15 V
32 ns + (0.16 ns/pF)CL
-
40
80
ns
5V
123 ns + (0.55 ns/pF)CL
-
150
300
ns
10 V
59 ns + (0.23 ns/pF)CL
-
70
140
ns
15 V
47 ns + (0.16 ns/pF)CL
-
55
110
ns
5V
73 ns + (0.55 ns/pF)CL
-
100
200
ns
10 V
34 ns + (0.23 ns/pF)CL
-
45
90
ns
15 V
27 ns + (0.16 ns/pF)CL
-
35
70
ns
[1] 10 ns + (1.00 ns/pF)CL
-
60
120
ns
5V
transition time
Extrapolation formula
10 V
9 ns + (0.42 ns/pF)CL
-
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-
20
40
ns
5V
-
40
80
ns
10 V
-
25
50
ns
15 V
-
20
40
ns
5V
-
40
80
ns
10 V
-
25
50
ns
15 V
-
20
40
ns
5V
-
75
150
ns
10 V
-
40
80
ns
15 V
-
30
60
ns
5V
-
80
160
ns
10 V
-
40
80
ns
15 V
-
30
60
ns
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HEF4094B-Q100
Nexperia
8-stage shift-and-store register
Symbol Parameter
Conditions
VDD
tsu
D to CP;
see Fig. 9
set-up time
th
hold time
tW
fmax
[1]
maximum frequency
Min
Typ
Max
Unit
5V
60
30
-
ns
10 V
20
10
-
ns
15 V
15
5
-
ns
5V
+5
-15
-
ns
10 V
20
5
-
ns
15 V
20
5
-
ns
minimum LOW 5 V
clock pulse; see 10 V
Fig. 6
15 V
60
30
-
ns
30
15
-
ns
24
12
-
ns
D to CP;
see Fig. 9
pulse width
Extrapolation formula
minimum HIGH
strobe pulse;
see Fig. 7
5V
40
20
-
ns
10 V
30
15
-
ns
15 V
24
12
-
ns
see Fig. 6
5V
5
10
-
MHz
10 V
11
22
-
MHz
15 V
14
28
-
MHz
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 8. Dynamic power dissipation
VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
PD
dynamic power
dissipation
VDD
Typical formula for PD (μW)
5V
PD = 2100 x fi + Σ(fo x CL) x VDD
where:
2
2
10 V
PD = 9700 x fi + Σ(fo x CL) x VDD
15 V
PD = 26000 x fi + Σ(fo x CL) x VDD
2
fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
Σ(fo x CL) = sum of the outputs.
10.1. Waveforms and test circuit
1/fmax
VI
CP input
VM
GND
VOH
QPn, QS1 output
tW
tPHL
tPLH
VM
VOL
VOH
QS2 output
tPHL
tPLH
VM
VOL
001aaf113
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6.
Clock to outputs propagation delays, and clock pulse width and maximum frequency
HEF4094B_Q100
Product data sheet
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HEF4094B-Q100
Nexperia
8-stage shift-and-store register
VI
STR input
VM
GND
tW
tPHL
tPLH
VOH
QPn output
VM
VOL
001aaj058
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 7.
Strobe to output propagation delays, and strobe pulse width, set up and hold times
VI
VM
OE input
GND
tPZL
tPLZ
VDD
output
LOW-to-OFF
OFF-to-LOW
VOL
VM
VX
tPHZ
tPZH
VOH
output
HIGH-to-OFF
OFF-to-HIGH
GND
VY
VM
outputs
enabled
outputs
enabled
outputs
disabled
001aai545
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 8.
3-state output enable and disable times for OE input
VI
VM
CP input
GND
t su
t su
th
th
VI
VM
D input
GND
VOH
VM
QPn, QS1, QS2 output
VOL
001aaf115
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 9.
Data input data set up and hold times
HEF4094B_Q100
Product data sheet
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HEF4094B-Q100
Nexperia
8-stage shift-and-store register
Table 9. Measurement points
Supply voltage
Input
Output
VDD
VM
VM
VX
VY
5 V to 15 V
0.5VDD
0.5VDD
0.1VDD
0.9VDD
VI
negative
pulse
tW
90 %
90 %
VM
10 %
0V
VI
positive
pulse
0V
VM
10 %
VEXT
tf
tr
tr
tf
90 %
VDD
90 %
VM
VI
G
RL
VO
DUT
VM
RT
10 %
CL
10 %
tW
001aaj915
001aaj781
a. Input waveform
b. Test circuit
Test and measurement data is given in Table 10.
Definitions test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 10. Test circuit
Table 10. Test data
Supply voltage Input
VEXT
Load
VDD
VI
tr, tf
tPHL, tPLH
tPHZ, tPZH
tPLZ, tPZL
CL
RL
5 V to 15 V
VSS or VDD
≤ 20 ns
open
VSS
VDD
50 pF
1 kΩ
11. Application information
Some examples of applications for the HEF4094B-Q100 are:
•
•
Serial-to-parallel data conversion
Remote control holding register
DIGITALLY CONTROLLED
EQUIPMENT
(REQUIRES CONTINUOUS
DIGITAL CONTROL)
QP0
QP7
D HEF4094B-Q100 QS2
STR
CP
DIGITALLY CONTROLLED
EQUIPMENT
QP0
QP7
D HEF4094B-Q100 QS2
STR
DIGITALLY CONTROLLED
EQUIPMENT
QP0
D
CP
QP7
HEF4094B-Q100
STR
CP
CONTROL
AND
SYNC
CIRCUITRY
data
clock
from remote
control panel
aaa-004311
Fig. 11. Remote control holding register
HEF4094B_Q100
Product data sheet
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Rev. 5 — 8 July 2021
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Nexperia B.V. 2021. All rights reserved
10 / 15
HEF4094B-Q100
Nexperia
8-stage shift-and-store register
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
w M
bp
0
2.5
detail X
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.05
0.039
0.016
0.028
0.020
0.01
0.01
0.004
0.028
0.012
0.244
0.041
0.228
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig. 12. Package outline SOT109-1 (SO16)
HEF4094B_Q100
Product data sheet
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Rev. 5 — 8 July 2021
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11 / 15
HEF4094B-Q100
Nexperia
8-stage shift-and-store register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
D
SOT403-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig. 13. Package outline SOT403-1 (TSSOP16)
HEF4094B_Q100
Product data sheet
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Rev. 5 — 8 July 2021
©
Nexperia B.V. 2021. All rights reserved
12 / 15
HEF4094B-Q100
Nexperia
8-stage shift-and-store register
13. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
14. Revision history
Table 12. Revision history
Document ID
Release date
Data sheet status
Change notice Supersedes
HEF4094B_Q100 v.5
20210708
Product data sheet
-
Modifications:
•
•
HEF4094B_Q100 v.4
20181114
Modifications:
•
•
•
Section 1 and Section 2 updated.
Section 7: Derating values for Ptot total power dissipation updated.
20130704
Modifications:
•
HEF4094B_Q100 v.2
20130606
Modifications:
•
HEF4094B_Q100 v.1
20120807
Product data sheet
Product data sheet
-
HEF4094B_Q100 v.3
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Fig. 5 corrected.
HEF4094B_Q100 v.3
HEF4094B_Q100
HEF4094B_Q100 v.4
Product data sheet
-
HEF4094B_Q100 v.2
-
HEF4094B_Q100 v.1
Fig. 3 corrected (errata).
Product data sheet
added type number HEF4094BTT-Q100.
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 8 July 2021
-
©
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13 / 15
HEF4094B-Q100
Nexperia
8-stage shift-and-store register
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
15. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
This document contains data from
the preliminary specification.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Product [short]
data sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
HEF4094B_Q100
Product data sheet
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Rev. 5 — 8 July 2021
©
Nexperia B.V. 2021. All rights reserved
14 / 15
HEF4094B-Q100
Nexperia
8-stage shift-and-store register
Contents
1. General description...................................................... 1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description............................................................. 3
6. Functional description................................................. 4
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................5
9. Static characteristics....................................................6
10. Dynamic characteristics............................................ 7
10.1. Waveforms and test circuit........................................ 8
11. Application information............................................10
12. Package outline........................................................ 11
13. Abbreviations............................................................ 13
14. Revision history........................................................13
15. Legal information......................................................14
©
Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 8 July 2021
HEF4094B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 8 July 2021
©
Nexperia B.V. 2021. All rights reserved
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