AS7261
XYZ Chromatic White Color Sensor +
NIR with Electronic Shutter and Smart
Interface
General Description
The AS7261is a chromatic white color sensor providing direct
XYZ color coordinates consistent with the CIE 1931 2° Standard
Observer color coordinates. It also maps the XYZ coordinates
to the x, y (Y) of the 2-dimensional color gamut and scales the
coordinates to the CIE 1976 u’v’ coordinate system.
The device provides accurate Correlated Color Temperature
(CCT) measurements and provides color point deviation from
the black body curve for white light color in the delta u’ v’
coordinate system. It also integrates a Near-IR channel for other
applications. LED drivers with programmable currents are
provided for electronic shutter applications.
The AS7261 integrates Gaussian filters into standard CMOS
silicon via Nano-optic deposited interference filter technology
and is packaged in an LGA package that provides a built in
aperture to control the light entering the sensor array.
Control and spectral data access is implemented through either
the I²C register set, or with a high level AT Spectral Command
set via a serial UART.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS7261, XYZ Chromatic White
Color Sensor + NIR with Electronic Shutter and Smart Interface
are listed below:
Figure 1:
AS7261 Benefits and Features
Benefits
Features
• Calibrated Chromatic white data
•
•
•
•
• Simple text-based command interface via UART,
or direct register read and write with interrupt
on sensor ready option on I²C
• UART or I²C slave digital Interface
• Lifetime-calibrated sensing with minimal drift
over time or temperature
• Filter set realized by silicon interference filters
• No additional signal conditioning required
• 16-bit ADC with digital access
ams Datasheet
[v1-00] 2016-Dec-30
XYZ
xy data (CIE 1931)
DUV, u’v’, uv (CIE 1976)
CCT, LUX
Page 1
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AS7261 − General Description
Benefits
Features
• Electronic shutter control/synchronization
• Programmable LED drivers
• Low voltage operation
• 2.7V to 3.6V with I²C interface
• Small, robust package, with built-in aperture
• 20-pin LGA package 4.5mm x 4.7mm x 2.5mm
• -40°C to 85°C temperature range
Applications
The AS7261 applications include:
• Color measurement and absorbance
• Color matching and identification
• Precision color tuning/calibration
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
AS7261 Chromatic White Color System
3.3V
100nF
uP
10uF
VDD1 VDD2
RX / SCL_S
TX / SDA_S
LED_IND
INT
LED_DRV
AS7261
Flash
Memory
MOSI
MISO
SCK
CSN_EE
GND
Page 2
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XYZ, NIR,
C&D
Sensors
3.3V
3.3V
Light
Source
Light in
Reflective
Surface
ams Datasheet
[v1-00] 2016-Dec-30
AS7261 − Pin Assignments
Pin Assignments
The device pin assignments are described below.
Figure 3:
AS7261 Pin Diagram (Top View)
20
16
1
15
5
11
6
10
Figure 4:
AS7261 Pin Description
Pin #
Pin Name
1
NC
2
RESN
Reset, active LOW
3
SCK
SPI serial clock
4
MOSI
SPI master out slave in
5
MISO
SPI master in slave out
6
CSN_EE
Chip Select for external serial Flash memory, Active LOW
7
CSN_SD
Chip Select for SD Card Interface, Active LOW
8
I2C_ENB
Select UART (Low) or I²C (High) Operation
9
NF
ams Datasheet
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Description
Not functional. Do not connect
Not Functional. Do not connect.
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AS7261 − Pin Assignments
Pin #
Pin Name
10
NF
11
RX/SCL_S
RX (UART) or SCL_S (I²C Slave) Depending on I2C_ENB
12
TX/SDA_S
TX (UART) or SDA_S (I²C Slave) Depending on I2C_ENB
13
INT
14
VDD2
15
LED_DRV
16
GND
Ground
17
VDD1
Voltage Supply
18
LED_IND
19
NF
Not Functional. Do not connect.
20
NF
Not Functional. Do not connect.
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Description
Not Functional. Do not connect.
Interrupt, Active LOW
Voltage Supply
LED Driver Output for Driving LED, Current Sink
LED Driver Output for Indicator LED, Current Sink
ams Datasheet
[v1-00] 2016-Dec-30
AS7261 − Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under Electrical
Characteristics is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 5:
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Electrical Parameters
VDD1_MAX
Supply voltage VDD1
-0.3
5
V
Pin VDD1 to GND
VDD2_MAX
Supply voltage VDD2
-0.3
5
V
Pin VDD2 to GND
Input/output pin voltage
-0.3
VDD + 0.3
V
Input/output pin to GND
VDD_IO
I_scr
Input current
(latch-up immunity)
±100
mA
JESD78D
Electrostatic Discharge
ESDHBM
Electrostatic discharge
HBM
±1000
V
JS-001-2014
ESDCDM
Electrostatic discharge
CDM
±500
V
JSD22-C101F
Temperature Ranges and Storage Conditions
Tstrg
Storage temperature
range
Tbody
Package body
temperature
RHNC
Relative humidity
non-condensing
MSL
Moisture sensitivity level
ams Datasheet
[v1-00] 2016-Dec-30
-40
85
5
3
°C
260
°C
85
%
IPC/JEDEC J-STD-020.
The reflow peak soldering
temperature (body
temperature) is specified
according IPC/JEDEC
J-STD-020 “Moisture/Reflow
Sensitivity Classification for
Non-hermetic Solid State
Surface Mount Devices”
Represents a 168 hours max.
floor life time
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AS7261 − Electrical Characteristics
Electrical Characteristics
All limits are guaranteed with VDD = VDD1 = VDD2 = 3.3V,
TAMB = 25°C. The parameters with min and max values are
guaranteed with production tests or SQC (Statistical Quality
Control) methods.VDD1 and VDD2 must be sourced from the
same power supply.
Figure 6:
AS7261 Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
General Operating Conditions
VDD1 /VDD2
Voltage operating
supply
UART interface
2.97
3.3
3.6
V
VDD1 /VDD2
Voltage operating
supply
I²C interface
2.7
3.3
3.6
V
-40
25
85
°C
5
mA
16.3
MHz
1.2
ns
-8.5
8.5
°C
1
8
mA
-30
30
%
0.3
VDD
V
TAMB
Operating
temperature
IVDD
Operating current
Internal RC Oscillator
FOSC
Internal RC oscillator
frequency
tJITTER
Internal clock jitter
15.7
@25°C
16
Temperature Sensor
DTEMP
Absolute accuracy of
the internal
temperature
measurement
Indicator LED
IIND
LED current
IACC
Accuracy of current
VLED
Voltage range of
connected LED
Vds of current sink
LED_DRV
ILED1
LED current
12.5
100
mA
IACC
Accuracy of current
-10
10
%
VLED
Voltage range of
connected LED
0.3
VDD
V
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Vds of current sink
ams Datasheet
[v1-00] 2016-Dec-30
AS7261 − Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-1
-0.2
mA
Digital Inputs and Outputs
IIL RESN
Logic input current
(RESN pin)
Vin=0V
VIH
CMOS logic high
input
0.7* VDD
VDD
V
VIL
CMOS logic low
input
0
0.3* VDD
V
VOH
CMOS logic high
output
I=1mA
VDD-0.4
V
VOL
CMOS logic low
output
I=1mA
0.4
V
tRISE(1)
Current rise time
C(Pad)=30pF
5
ns
tFALL(1)
Current fall time
C(Pad)=30pF
5
ns
Note(s):
1. Guaranteed, not tested in production.
ams Datasheet
[v1-00] 2016-Dec-30
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AS7261 − Electrical Characteristics
Timing Characteristics
Figure 7:
AS7261 I²C Slave Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
400
kHz
I²C Interface
fSCLK
SCL Clock Frequency
tBUF
Bus Free Time Between a
STOP and START
1.3
μs
Hold Time (Repeated) START
0.6
μs
tLOW
LOW Period of SCL Clock
1.3
μs
tHIGH
HIGH Period of SCL Clock
0.6
μs
tSU:STA
Setup Time for a Repeated
START
0.6
μs
tHD:DAT
Data Hold Time
0
tSU:DAT
Data Setup Time
100
tR
Rise Time of Both SDA and
SCL
20
300
ns
tF
Fall Time of Both SDA and
SCL
20
300
ns
Setup Time for STOP
Condition
0.6
tHD:STA
tSU:STO
0
CB
Capacitive Load for Each Bus
Line
CI/O
I/O Capacitance (SDA, SCL)
0.9
μs
ns
μs
CB — total capacitance of
one bus line in pF
400
pF
10
pF
Figure 8:
I²C Slave Timing Diagram
tR
tF
tLOW
SCL
P
tHIGH
S
tHD:STA
tHD:DAT
S
tSU:DAT
t SU:STA
P
tSU:STO
VIH
SDA
tBUF
Stop
VIL
Start
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AS7261 − Electrical Characteristics
Figure 9:
AS7261SPI Slave Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
16
MHz
SPI Interface
fSCLK
Clock Frequency
0
tSCK_H
Clock high time
40
ns
tSCK_L
Clock low time
40
ns
tSCK_RISE
SCK rise time
5
ns
tSCK_FALL
SCK fall time
5
ns
tCSN_S
CSN setup time
Time between CSN
high-low transition to first
SCK high transition
50
ns
tCSN_H
CSN hold time
Time between last SCK
falling edge and CSN
low-high transition
100
ns
tCSN_DIS
CSN disable time
100
ns
tDO_S
Data-out setup time
5
ns
tDO_H
Data-out hold time
5
ns
tDI_V
Data-in valid
10
ns
Figure 10:
SPI Master Write Timing Diagram
tCSN_DIS
CSN
tSCK_RISE
tCSN_S
tCSN_H
tSCK_FALL
SCK
tDO_S
MOSI
tDO_H
MSB
HI-Z
LSB
HI-Z
MISO
ams Datasheet
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AS7261 − Electrical Characteristics
Figure 11:
SPI Master Read Timing Diagram
CSN_xx
tSCK_H
tSCK_L
SCK
tDI_V
Dont care
MOSI
MISO
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MSB
LSB
ams Datasheet
[v1-00] 2016-Dec-30
AS7261 − Typical Optical Characteristics
Typical Optical Characteristics
Figure 12:
Spectral Responsivity
CIE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
380 395 410 425 440 455 470 485 500 515 530 545 560 575 590 605 620 635 650 665 680 695 710 725 740 755 770
X
Y
Z
Figure 13:
AS7261 Optical Characteristics
Symbol
(2)
Color_m
Z_count
Parameter
Test Conditions
Color
measurement
accuracy
White Light
CCT = 2700K, 3500K,
4500K and 5700K
Z channel count
accuracy
White Light
CCT = 5700K
Min
Typ(1)
Max
0.002
3.375
4.5
Unit
du’v’
5.625
counts/
(μW/cm2)
Note(s):
1. Typical values at Lux ≥50, Integration time=400.4ms, Gain=1x, TAMB = 25ºC.
2. Calibration and measurements are made using diffused light.
Figure 14:
AS7261 LGA Package Field of View
ams Datasheet
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AS7261 − Detailed Descriptions
Detailed Descriptions
Figure 15:
Internal Block Diagram
VDD1
VDD2
INT
LED_IND
RX / SCL_S
2
UART / I C
TX / SDA_S
LED_DRV
I2C_ENB
°C
Cognitive Light
Engine (CLE)
MISO
SPI
Master
MOSI
SCK
CSN_SD
Multi
Spectral
Sensor
X
Y
Z
D C NIR
RESN
RC Osc
16MHz
AS7261
GND
XYZ Chromatic White Color Sensor
The XYZ Chromatic White Color sensor is a next-generation
digital color sensor device. Each channel is a designed to meet
the X, Y, Z standard observer filter characteristics compliant
with the CIE 1931 standard or an NIR spectrum.
The sensor contains analog-to-digital converters (16-bit
resolution ADC), which integrate the current from each
channel’s photodiode. Upon completion of the conversion
cycle, the integrated result is transferred to the corresponding
data registers. The transfers are double-buffered to ensure that
the integrity of the data is maintained.
Standard observer interference filters realize the XYZ response,
which enables minimal life-time drift and very high
temperature stability. Filter accuracy will be affected by the
angle of incidence which itself is limited by an integrated
aperture and an internal micro-lens structure. The
aperture-limited field of view is ±20.5° to deliver specified
accuracy.
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ams Datasheet
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AS7261 − Detailed Descriptions
Data Conversion Description
AS7261 Spectral Conversion is implemented via two
photodiode banks. The First Bank, Bank1 consists of data from
the X, Y, Z and NIR (near-IR) photodiodes. Bank2 provides data
from the same X and Y photodiodes as well as the D (dark) and
C (Clear) photodiodes. Spectral conversion requires the
integration time (IT in ms) set to complete. If both photodiode
banks are required to complete the conversion, the 2nd bank
requires an additional IT ms. Minimum IT for a single bank
conversion is 2.8 ms. If data is required from all 6 photodiodes
then the device must perform 2 full conversions (2 x Integration
Time).
The spectral conversion process is controlled with four BANK
Mode settings as follows:
BANK Mode 0:
Conversions will occur continuously and data will be available
in I²C registers X, Y, Z, and NIR or via the ATDATA command when
using the UART device interface.
BANK Mode 1:
Conversions will occur continuously and data will be available
in I²C registers X, Y, D, and C or via the ATDATA command.
BANK Mode 2:
Conversions occur continuously and data will be available in
registers X, Y, Z, NIR, D and C or via the ATDATA command after
two integration periods. In this Mode 2 the calibrated, corrected
values may also be obtained from the appropriate I²C registers
or using the ATXYZC command.
When the bank setting is Mode 0, Mode 1, or Mode 2, the
spectral data conversion process operates continuously, with
new data available after each IT ms period. In the continuous
modes, care should be taken to assure prompt interrupt
servicing so that integration values from both banks are all
derived from the same spectral conversion cycle.
BANK Mode 3:
Data will be available in registers X, Y, Z, NIR, D and C in One-Shot
mode. And in this Mode 3 the calibrated, corrected values may
also be obtained from the appropriate I²C registers or using the
ATXYZC command.
When the bank setting is set to Mode 3 the device initiates
One-Shot operation. The DATA_RDY bit is set to 1 once data is
available, indicating spectral conversion is complete. One-Shot
mode is intended for use when it is critical to ensure spectral
conversion results are obtained contemporaneously.
ams Datasheet
[v1-00] 2016-Dec-30
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AS7261 − Detailed Descriptions
Figure 16:
Photo Diode Array
Photo Diode Array
X
Y
C
Z
D
NIR
Figure 17:
Bank Mode and Data Conversion
BANK Mode 0
One Conversion
X, Y, Z, NIR
Integration Time
BANK Mode 1
One Conversion
X, Y, D, C
Integration Time
BANK Mode 2
1st Conversion
Integration Time
X, Y, Z, NIR
2nd Conversion
X, Y, D, C
Integration Time
RC Oscillator
The timing generation circuit consists of an on-chip 16MHz,
temperature compensated oscillator which provides the master
clock for the AS7261.
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AS7261 − Detailed Descriptions
Temperature Sensor
The internal temperature sensor is constantly measuring the
on-chip temperature and enables temperature compensation
procedures. It can be read via I²C or AT Command.
Reset
Pulling down the RESN pin for longer than 100ms resets the
AS7261.
Figure 18:
Reset Circuit
Cognitive
Lighting
Engine
Reset
AS7261
RESN
Push > 100ms
Indicator LED for Flash Memory Programming
Progress
The LED, connected to pin LED_IND, can be used to indicate
Flash memory programming progress of the device. While
programming the AS7261 via the external SD card the indicator
LED automatically starts flashing. When programming is
completed the indicator LED is automatically switched off. The
Flash Memory Programming is initiated by the user as needed,
but once started the LED flashing is not under user control.
Electronic Shutter with LED_IND or LED_DRV
Driver Control
Under user control there are two LED driver outputs that can
be used to control LEDs on each driver pin. This allows different
wavelength light sources to be used in the same system. The
LED output sink currents are programmable and can drive
external LED sources: LED_IND for 1mA, 2mA, 4mA or 8mA and
LED_DRV for 12.5mA, 25mA, 50mA or 100mA. After
programming for current the sources can be turned off and on
via I²C registers or AT commands to provide the AS7261 with an
electronic shutter capability.
ams Datasheet
[v1-00] 2016-Dec-30
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AS7261 − Detailed Descriptions
Interrupt Operation
If BANK is set to Mode 0 or Mode 1 then the data is ready after
the 1st integration time. If BANK is set to Mode 2 or Mode 3 then
the data is ready after two integration times. If the interrupt is
enabled (INT = 1) then when the data is ready, the INT line is
pulled low and DATA_RDY is set to 1. The INT line is released
(returns high) when the control register is read.
DATA_RDY is cleared to 0 when any of the sensor registers X, Y,
Z, NIR, D and C are read. For multi-byte sensor data (2 or 4 bytes),
after the 1st byte is read the remaining bytes are shadow
protected in case an integration cycle completes just after the
1st byte is read.
In continuous spectral conversion mode (BANK setting of Mode
0, 1, or 2), the sensors continue to gather information at the rate
of the integration time, hence if the sensor registers are not read
when the interrupt line goes low, it will stay low and the next
cycle’s sensor data will be available in the registers at the end
of the next integration cycle.
When the control register BANK bits are written with a value of
Mode 3, One-Shot Spectral Conversion mode is entered. When
a single set of contemporaneous sensor readings is desired,
writing BANK Mode 3 to the control register immediately
triggers exactly two spectral data conversion cycles. At the end
of these two conversion cycles, the DATA_RDY bit is set as for
the other BANK modes. To perform a new One-Shot sequence,
the control register BANK bits should be written with a value of
Mode 3 again. This process may continue until the user writes
a different value into the BANK bits.
I²C Slave Interface
If selected by the I2C_ENB pin setting, interface and control can
be accomplished through an I²C compatible slave interface to
a set of registers that provide access to device control functions
and output data. These registers on the AS7261 are, in reality,
implemented as virtual registers in software. The actual I²C
slave hardware registers number only three and are described
in the table below. The steps necessary to access the virtual
registers defined in the following are explained in pseudocode
for external I²C master writes and reads below.
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AS7261 − Detailed Descriptions
I²C Feature List
• Fast mode (400kHz) and standard mode (100kHz) support
• 7+1-bit addressing mode
• Write format: Byte
• Read format: Byte
Figure 19:
I²C Slave Device Address and Physical Registers
Entity
Description
Note
8-bit Slave Address
Byte = 1001001x (device address = 49 hex)
x= 1 for Master Read (byte = 93 hex)
x= 0 for Master Write (byte = 92 hex)
STATUS Register
I²C slave interface STATUS
register
Read-only
Register Address = 0x00
Bit 1: TX_VALID
0 New data may be written to WRITE register
1 WRITE register occupied. Do NOT write.
Bit 0: RX_VALID
0 No data is ready to be read in READ register.
1 Data byte available in READ register.
WRITE Register
I²C slave interface WRITE
register
Write-only
Register Address = 0x01
8-Bits of data written by the I²C Master intended for
receipt by the I²C slave. Used for both virtual register
addresses and write data.
READ Register
I²C slave interface READ
register
Read-only
Register Address = 0x02
8-Bits of data to be read by the I²C Master.
Device Slave
Address
I²C Virtual Register Write Access
I²C Virtual Resister Byte Write, detailed below, shows the
pseudocode necessary to write virtual registers on the AS7261.
Note that, because the actual registers of interest are realized
as virtual registers, a means of indicating whether there is a
pending read or write operation of a given virtual register is
needed. To convey this information, the most significant bit of
the virtual register address is used as a marker. If it is 1, then a
write is pending, otherwise the slave is expecting a virtual read
operation. The pseudocode illustrates the proper technique for
polling of the I²C slave status register to ensure the slave is ready
for each transaction.
ams Datasheet
[v1-00] 2016-Dec-30
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AS7261 − Detailed Descriptions
I²C Virtual Register Byte Write
Pseudocode
Poll I²C slave STATUS register;
If TX_VALID bit is 0, a write can be performed on the interface;
Send a virtual register address and set the MSB of the register address to 1 to indicate the pending write;
Poll I²C slave STATUS register;
If TX_VALID bit is 0, the virtual register address for the write has been received and the data may now be written;
Write the data.
Sample Code:
#define I2C_AS72XX_SLAVE_STATUS_REG
0x00
#define I2C_AS72XX_SLAVE_WRITE_REG
0x01
#define I2C_AS72XX_SLAVE_READ_REG
0x02
#define I2C_AS72XX_SLAVE_TX_VALID
0x02
#define I2C_AS72XX_SLAVE_RX_VALID
0x01
void i2cm_AS72xx_write(uint8_t virtualReg, uint8_t d)
{
volatile uint8_t status;
while (1)
{
// Read slave I²C status to see if the write buffer is ready.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG);
if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0)
// No inbound TX pending at slave. Okay to write now.
break,
}
// Send the virtual register address (setting bit 7 to indicate a pending write).
i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, (virtualReg | 0x80)) ;
while (1)
{
// Read the slave I²C status to see if the write buffer is ready.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG) ;
if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0)
// No inbound TX pending at slave. Okay to write data now.
break;
}
//Send the data to complete the operation.
i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, d) ;
}
I²C Virtual Register Read Access
I²C Virtual Register Byte Read, detailed below, shows the
pseudocode necessary to read virtual registers on the AS7261.
Note that in this case, reading a virtual register, the register
address is not modified.
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AS7261 − Detailed Descriptions
I²C Virtual Register Byte Read
Pseudocode
Poll I²C slave STATUS register;
If TX_VALID bit is 0, the virtual register address for the read may be written;
Send a virtual register address;
Poll I²C slave STATUS register;
If RX_VALID bit is 1, the read data is ready;
Read the data.
Sample Code:
uint8_t i2cm_AS72xx_read(uint8_t virtualReg)
{
volatile uint8_t status, d ;
while (1)
{
// Read slave I²C status to see if the read buffer is ready.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG);
if ((status & I2C_AS72XX_SLAVE_TX_VALID) == 0)
// No inbound TX pending at slave. Okay to write now.
break;
}
// Send the virtual register address (setting bit 7 to indicate a pending write).
i2cm_write(I2C_AS72XX_SLAVE_WRITE_REG, virtualReg);
while (1)
{
// Read the slave I²C status to see if our read data is available.
status = i2cm_read(I2C_AS72XX_SLAVE_STATUS_REG) ;
if ((status & I2C_AS72XX_SLAVE_RX_VALID) != 0)
// Read data is ready.
break ;
}
// Read the data to complete the operation.
d = i2cm_read(I2C_AS72XX_SLAVE_READ_REG) ;
return d ;s
}
The details of the i2cm_read() and i2cm_write() functions in
previous Figures are dependent upon the nature and
implementation of the external I²C master device.
ams Datasheet
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AS7261 − Detailed Descriptions
4-Btye Floating-Point (FP) Registers
Several 4 byte registers (hex) are used by the AS7261. Here is
an example of how these registers are used to represent floating
point data (based on the IEEE 754 standard):
Figure 20:
Example of the IEEE 754 Standard
The floating point (FP) value assumed by 32 bit binary32 data
with a biased exponent e (the 8 bit unsigned integer) and a
23 bit fraction is (for the above example):
23
– i
1
+
b
2
23 – i × 2 ( e – 127 )
i=1
sign
(EQ1)
FPvalue = ( – 1 )
(EQ2)
–i
FPvalue = ( – 1 ) 1 + b 23 – i 2 × 2 ( 124 – 127 )
i=1
(EQ3)
FPvalue = 1 × ( 1 + 2 ) × 2 ( – 3 ) = 0.15625
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23
0
–2
ams Datasheet
[v1-00] 2016-Dec-30
AS7261 − Detailed Descriptions
I²C Virtual Register Set
The figure below provides a summary of the AS7261 I²C register
set. Figures after that provide additional register details. All
register data is hex, and all multi-byte entities are Big Endian
(most significant byte is situated at the lowest register address).
Multiple byte registers (2 byte integer, or, 4 byte floating point)
must be read in the order of ascending register addresses (low
to high). And if capable of being written to, must also be written
in the order ascending register addresses.
Figure 21:
I²C Virtual Register Set Overview
Addr
Name
DATA_
RDY
RSVD
Version Registers
0x00:0x01
HW_Version
Hardware Version
0x02:0x03
FW_Version
Firmware Version
Control Registers
0x04
Control_Setup
0x05
INT_T
0x06
Device_Temp
0x07
LED_Control
RST
INT
GAIN
Bank
Integration Time
Device Temperature
RSVD
ICL_DRV
LED_
DRV
ICL_IND
LED_IND
Sensor Raw Data Registers
0x08
X_High
Channel X High Data Byte
0x09
X_Low
Channel X Low Data Byte
0x0A
Y_High
Channel Y High Data Byte
0x0B
Y_Low
Channel Y Low Data Byte
0x0C
Z_High
Channel Z High Data Byte
0x0D
Z_Low
Channel Z Low Data Byte
0x0E
NIR_High
Channel NIR High Data Byte
0x0F
NIR_Low
Channel NIR Low Data Byte
0x10
Dark_High
Channel Dark High Data Byte
0x11
Dark_Low
Channel Dark Low Data Byte
0x12
Clear_High
Channel Clear High Data Byte
0x13
Clear_Low
Channel Clear Low Data Byte
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AS7261 − Detailed Descriptions
Sensor Calibrated Data Registers
0x14:0x17
Cal_X
Cal-X data (4-byte floating-point)
0x18:0x1B
Cal_Y
Cal-Y data (4-byte floating-point)
0x1C:0x1F
Cal_Z
Cal-Z data (4-byte floating-point)
0x20:0x23
Cal_x_1931
Cal-x (CIE 1931) (4-byte floating-point)
0x24:0x27
Cal_y_1931
Cal-y (CIE 1931) (4-byte floating-point)
0x28:0x2B
Cal_upri
Cal_u’ (CIE 1976) (4-byte floating-point)
0x2C:0x2F
Cal_vpri
Cal_v’ (CIE 1976) (4-byte floating-point)
0x30:0x33
Cal_u
Cal_u (CIE 1976) (4-byte floating-point)
0x34:0x37
Cal_v
Cal_y (CIE 1976) (4-byte floating-point)
0x38:0x3B
Cal_DUV
Cal_DUV (CIE 1976) (4-byte floating-point)
0x3C:0x3F
Cal_LUX
Calibrated LUX (4-byte)
0x40:0x4F
Cal_CCT
Calibrated CCT (4-byte)
Detailed Register Description
Figure 22:
HW Version Registers
Addr: 0x00
HW_Version
Bit
Bit Name
Default
Access
7:0
Device Type
01000000
R
Addr: 0x01
Device type number
HW_Version
Bit
Bit Name
Default
Access
7:0
HW Version
00111101
R
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Bit Description
Bit Description
Hardware version
ams Datasheet
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AS7261 − Detailed Descriptions
Figure 23:
FW Version Registers
Addr: 0x02
FW_Version
Bit
Bit Name
Default
Access
7:6
Minor version
R
Minor version [1:0]
5:0
Sub version
R
Sub version
Addr: 0x03
Bit Description
FW_Version
Bit
Bit Name
Default
Access
Bit Description
7:4
Major version
R
Major version
3:0
Minor version
R
Minor version [5:2]
Figure 24:
Control Setup Register
Addr: 0x04/0x84
Control_Setup
Bit
Bit Name
Default
Access
Bit Description
7
RST
0
R/W
Soft Reset, Set to 1 for soft reset, goes to 0
automatically after the reset
6
INT
0
R/W
Enable interrupt pin output (INT),
1: Enable,
0: Disable
5:4
GAIN
10
R/W
Sensor Channel Gain Setting (all channels)
‘b00=1x; ‘b01=3.7x; ‘b10=16x; ‘b11=64x;
3:2
BANK
10
R/W
Data Conversion Type (continuous)
‘b00=Mode 0: X, Y, Z and NIR
‘b01=Mode 1: X, Y, D and C
‘b10=Mode 2: X, Y, Z, NIR, D and C
‘b11=Mode 3: One-Shot operation
1
DATA_RDY
0
R/W
1: Data Ready to Read, sets INT active if
interrupt is enabled.
Can be polled if not using INT.
0
RSVD
0
R
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[v1-00] 2016-Dec-30
Reserved; Unused
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AS7261 − Detailed Descriptions
Figure 25:
Integration Time Register
Addr: 0x05/0x85
INT_T
Bit
Bit Name
Default
Access
7:0
INT_T
0xFF
R/W
Bit Description
Integration time = * 2.8ms
Figure 26:
Device Temperature Register
Addr: 0x06
Device_Temp
Bit
Bit Name
Default
Access
Bit Description
7:0
Device_Temp
0xFF
R/W
Internal device temperature data byte (°C)
Figure 27:
LED Control Register
Addr: 0x07/0x87
LED Control
Bit
Bit Name
Default
Access
7:6
RSVD
0
R
5:4
ICL_DRV
00
R/W
LED_DRV current limit
‘b00=12.5mA; ‘b01=25mA; ‘b10=50mA;
‘b11=100mA;
3
LED_DRV
0
R/W
Enable LED_DRV
1: Enabled;
0: Disabled
2:1
ICL_IND
00
R/W
LED_IND current limit
‘b00=1mA; ‘b01=2mA; ‘b10=4mA;
‘b11=8mA;
0
LED_IND
0
R/W
Enable LED_IND
1: Enabled;
0: Disabled
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Bit Description
Reserved
ams Datasheet
[v1-00] 2016-Dec-30
AS7261 − Detailed Descriptions
Figure 28:
Sensor Raw Data Registers
Addr: 0x08
Bit
Bit Name
7:0
X_High
X_High
Default
Access
R
Addr: 0x09
Bit
Bit Name
7:0
X_Low
Bit Name
7:0
Y_High
Default
Access
R
Bit Name
7:0
Y_Low
Default
Access
R
Bit Name
7:0
Z_High
Default
Access
R
Bit Name
7:0
Z_Low
Default
Access
R
Bit Name
7:0
NIR_High
Default
Access
R
Bit Name
7:0
NIR_Low
Default
Access
R
Bit Name
7:0
Dark_High
ams Datasheet
[v1-00] 2016-Dec-30
Channel Y Low Data Byte
Bit Description
Channel Z High Data Byte
Bit Description
Channel Z Low Data Byte
Bit Description
Channel NIR High Data Byte
NIR_Low
Default
Access
R
Addr: 0x10
Bit
Bit Description
NIR_High
Addr: 0x0F
Bit
Channel Y High Data Byte
Z_Low
Addr: 0x0E
Bit
Bit Description
Z_High
Addr: 0x0D
Bit
Channel X Low Data Byte
Y_Low
Addr: 0x0C
Bit
Bit Description
Y_High
Addr: 0x0B
Bit
Channel X High Data Byte
X_Low
Addr: 0x0A
Bit
Bit Description
Bit Description
Channel NIR Low Data Byte
Dark_High
Default
Access
R
Bit Description
Channel Dark High Data Byte
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AS7261 − Detailed Descriptions
Addr: 0x11
Bit
Bit Name
7:0
Dark_Low
Dark_Low
Default
Access
R
Addr: 0x12
Bit
Bit Name
7:0
Clear_High
Bit Name
7:0
Clear_Low
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Channel Dark Low Data Byte
Clear_High
Default
Access
R
Addr: 0x13
Bit
Bit Description
Bit Description
Channel Clear High Data Byte
Clear_Low
Default
Access
R
Bit Description
Channel Clear Low Data Byte
ams Datasheet
[v1-00] 2016-Dec-30
AS7261 − Detailed Descriptions
Figure 29:
Sensor Calibrated Data Registers
Addr: 0x14:0x17
Bit
Bit Name
31:0
X_Cal
Cal_X
Default
Access
R
Addr: 0x18:0x1B
Bit
Bit Name
31:0
Y_Cal
Bit Name
31:0
Z_Cal
Default
Access
R
Bit Name
31:0
Cal_x_1931
Default
Access
R
Bit Name
31:0
Cal_y_1931
Default
Access
R
Bit Name
31:0
Cal_upri
Default
Access
R
Bit Name
31:0
Cal_vpri
Default
Access
R
Bit Name
31:0
Cal_u
Default
Access
R
Bit Name
31:0
Cal_v
ams Datasheet
[v1-00] 2016-Dec-30
Calibrated x (CIE 1931) (4-byte floating-point)
Bit Description
Calibrated y (CIE 1931) (4-byte floating-point)
Bit Description
Calibrated u’ (CIE 1976) (4-byte floating-point)
Bit Description
Calibrated v’ (CIE 1976) (4-byte floating-point)
Cal_u
Default
Access
R
Addr: 0x1C:0x1F
Bit
Bit Description
Cal_vpri
Addr: 0x18:0x1B
Bit
Calibrated Z data (4-byte floating-point)
Cal_upri
Addr: 0x14:0x17
Bit
Bit Description
Cal_y_1931
Addr: 0x28:0x2B
Bit
Calibrated Y data (4-byte floating-point)
Cal_x_1931
Addr: 0x24:0x27
Bit
Bit Description
Cal_Z
Addr: 0x20:0x23
Bit
Calibrated X data (4-byte floating-point)
Cal_Y
Addr: 0x1C:0x1F
Bit
Bit Description
Bit Description
Calibrated u (CIE 1976) (4-byte floating-point)
Cal_v
Default
Access
R
Bit Description
Calibrated v (CIE 1976) (4-byte floating-point)
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AS7261 − Detailed Descriptions
Addr: 0x20:0x23
Bit
Bit Name
31:0
Cal_DUV
Cal_DUV
Default
Access
R
Bit Description
Calibrated DUV (CIE 1976) (4-byte floating-point)
Addr: 0x24:0x27
Bit
Bit Name
31:0
Cal_LUX
Cal_LUX
Default
Access
R
Bit Description
Calibrated LUX (4-byte)
Addr: 0x28:0x2B
Bit
Bit Name
31:0
Cal_CCT
Cal_CCT
Default
Access
R
Bit Description
Calibrated CCT (4-byte)
UART Interface
If selected by the I2C_ENB pin setting, the UART module
implements the TX and RX signals as defined in the RS-232 /
V.24 standard communication protocol.
It has on both, receive and transmit path, a 16 entry deep FIFO.
It can generate interrupts as required.
UART Feature List 1
• Full Duplex Operation (Independent Serial Receive and
Transmit Registers) with FIFO buffer of 8 byte for each.
• At a clock rate of 16MHz it supports communication at
115200 Baud.
• Supports Serial Frames with 8 Data Bits, no Parity and 1
Stop Bit
Theory of Operation
TRANSMISSION
If data is available in the transmit FIFO, it will be moved into the
output shift register and the data will be transmitted at the
configured Baud Rate, starting with a Start Bit (logic zero) and
followed by a Stop Bit (logic one).
RECEPTION
At any time, with the receiver being idle, if a falling edge of a
start bit is detected on the input, a byte will be received and
stored in the receive FIFO. The following Stop Bit will be checked
to be logic one.
1. With UART operation, min VDD of 2.97V is required as shown in Electrical Characteristics figures.
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AS7261 − Detailed Descriptions
Figure 30:
UART Protocol
Data Bits
TX
D1
D0
Start Bit
D2
D3
D4
D5
D6
Stop Bit
Tbit=1/Baude Rate
Always Low
RX
D0
D7
Next Start
Always High
D1
D0
D2
D3
D4
D5
D6
D0
D7
Start Bit detected
After Tbit/2: Sampling of Start Bit
After Tbit: Sampling of Data
Sample Points
AT Command Interface
The microprocessor interface to control the AS7261 is via the
UART, using AT Commands across the UART interface. This AT
Command interface provides a text-based serial command
interface borrowed from the “AT Command” model used in early
Hayes modems. For example:
• Read DATA value: ATDATA → OK
• Set the gain of the sensor to 1x: ATGAIN =0 → OK
The “AT Command Interface Block Diagram”, shown below
between the network interface and the core of the system,
provides access to the AS7261’s Cognitive Light Engine’s control
and configuration functions.
Figure 31:
AT Command Interface Block Diagram
RX
uP
AT Commands
TX
AT
Command
Interface
Cognitive
Light
Engine
AT Command Interface
AS7261
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AS7261 − Detailed Descriptions
In the figure below, numeric values may be specified with no
leading prefix, in which case they will be interpreted as
decimals, or with a leading “0x” to indicate that they are
hexadecimal numbers, or with a leading “‘b” to indicate that
they are binary numbers. The commands are loosely grouped
into functional areas. Texts appearing between angle brackets
(‘‘) are commands or response arguments. A carriage
return character, a linefeed character, or both may terminate
commands and responses. Note that any command that
encounters an error will generate the “ERROR” response shown,
for example, in the NOP command at the top of the first table,
but has been omitted elsewhere in the interest of readability
and clarity.
Figure 32:
AT Commands
Command
Response
Description/Parameters
XYZ Calibrated Data with Its Derivatives
ATXYZC
,
,
OK
Read calibrated X, Y, and Z data. Returns comma-separated
floating-point values
ATLUXC
OK
Read the calibrated LUX value from the sensor.
ATCCTC
OK
Read the calibrated CCT value from the sensor.
ATSMALLXYC
,
OK
Read calibrated x and y for CIE 1931 color gamut. Returns
comma separated floating-point values (5 decimal places).
ATUVPRIMEC
,
,
,
OK
Read calibrated u’, v’ and u, v for CIE 1976 color gamut.
Returns comma separated floating-point values (5 decimal
places).
ATDUVC
OK
Read calibrated Duv for CIE 1976-color gamut. Returns
comma separated floating-point values (5 decimal places).
Spectral Data per Channel
ATXYZR
, ,
OK
Read raw X, Y, and Z data. Returns comma-separated 16-bit
integers.
ATDATA
, ,
,
,
,
OK
Read raw X, Y, Z and NIR data as well as two special internal
registers D, & C. Returns comma-separated 16-bit integers.
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AS7261 − Detailed Descriptions
Sensor Configuration
OK
Set sensor integration time. Values should be in the range
[1... 255], with
integration time = * 2.8msecs.
OK
Read sensor integration time, with
integration time = * 2.8msecs.
OK
Set sensor gain: 0=1X, 1=3.7X, 2=16X, 3=64X
ATGAIN
OK
Read sensor gain setting, returning 0, 1, 2, or 3 as defined
immediately above.
ATTEMP
OK
Read temperature of chip in Celsius
OK
Set Chromatic White Color Sensor Mode
0 Captures X, Y, Z, and IR (1 integration period)
1 Captures X, Y, Dk, and CLR (1 integration period)
2 Captures X, Y, Z, Dk, IR and CLR
(2 integration period)
3 Sensors are OFF
OK
Read Color Sensor Mode, see above
OK
Set the sampling interval as an integer multiple of the
Integration time. The is an integer between
[1..255].
A sampling interval=1 implies a sampling rate of 1x the
current integration time.
A sampling interval=255 implies a slow sampling rate of
255 times the current integration time.
OK
Read the sampling interval as an integer multiple of the
Integration time.
Returns an integer in the range [1..255] as defined above
OK
= # of samples
(ATBURST=1 means run until ATBURST=0 is received (a
special case for continuous output)
ATINTTIME=
ATINTTIME
ATGAIN=
ATTCSMD=
ATTCSMD
ATINTRVL=
ATINTRVL
ATBURST=.
LED Driver Controls
ATLED0=
ATLED0
ATLED1=
ATLED1
ATLEDC=
ATLEDC
ams Datasheet
[v1-00] 2016-Dec-30
OK
Sets LED_IND: 100=ON, 0=OFF
OK
Reads LED_IND setting: 100=ON, 0=OFF
OK
Sets LED_DRV: 100=ON, 0=OFF
OK
Reads LED_DRV setting: 100=ON, 0=OFF
OK
Sets LED_IND and LED_DRV current
LED_IND: bits 3:0; LED_DRV: 7:4 bits
LED_IND: ‘b00=1mA; ‘b01=2mA; ‘b10=4mA; ‘b11=8mA
LED_DRV: ‘b00=12.5mA; ‘b01=25mA; ‘b10=50mA;
‘b11=100mA
OK
Reads LED_IND and LED_DRV current settings as shown
above
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AS7261 − Detailed Descriptions
NOP, Version Access, System Reset
AT
OK Success
ERROR Failure
NOP
ATSRST
OK Success
ERROR Failure
Software Reset
ATVERSW
OK
ERROR Failure
Returns the system software version number
ATVERHW
OK
ERROR Failure
Returns the system hardware revision and product ID, with
bits 7:4 containing the part ID, and bits 3:0 yielding the chip
revision value.
Firmware Update
OK
= 16-bit checksum. Initializes the firmware update
process. Number of bytes that follow are always 56 KBytes
ATFW=
OK
Download new firmware
Up to 7 bytes represented as hex chars with no leading or
trailing 0x.
Repeat command till all 56Kbytes of firmware are
downloaded
ATFWA
OK
Causes target address for FW updates to advance. Should
be called after every successful “OK” returned after
“ATFW=” command usage.
ATFWS
OK
Causes the active image to switch between the two
possible current images and then resets the IC
ATFWU=
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ams Datasheet
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AS7261 − Application Information
Application Information
Figure 33:
AS7261 Typical Application Circuit
3V3
3V3
7
14
VDD2
CSN_EE
6
1
/CS
2
RESN
MISO
5
2
DO
16
GND
MOSI
4
5
DI
SCK
3
6
Flash
Memory
CLK
8
3
/WP
7
/HOLD
3V3 Vled
15
LED_DRV
18
LED_IND
AS7261
I2C_ENB
DNP
RX
TX
INT
ams Datasheet
[v1-00] 2016-Dec-30
11
RX/SCL_S
12
TX/SDA_S
13
INT
NC
NC
NC
NC
NC
19
20
1
10
9
1uF
VCC
8
CSN_SD
GND
10K
RST
VDD1
4
100nF 10uF
17
0R
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AS7261 − Application Information
PCB Layout
Figure 34:
Typical Layout Reading
In order to prevent interference, avoid trace routing
feedthroughs with exposure directly under the AS7261. An
example routing is illustrated in the diagram.
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ams Datasheet
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AS7261 − Package Drawings & Markings
Package Drawings & Markings
Figure 35:
AS7261 Package Drawing
AS7261
RoHS
Green
Note(s):
1. XXXXX = tracecode
ams Datasheet
[v1-00] 2016-Dec-30
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AS7261 − PCB Pad Layout
Suggested PCB pad layout guidelines for the LGA device are
shown.
PCB Pad Layout
Figure 36:
Recommended PCB Pad Layout
Unit: mm
0.30
1.10
0.65
4.60
1
4.40
Note(s):
1. Unless otherwise specified, all dimensions are in millimeters.
2. Dimensional tolerances are ±0.05mm unless otherwise noted.
3. This drawing is subject to change without notice.
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AS7261 − Mechanical Data
Mechanical Data
Figure 37:
Tape & Reel Information
Note(s):
1. All dimensions in millimeters unless of otherwise stated.
2. Measured from centreline of sprocket hole to centreline of pocket.
3. Cumulative tolerance of 10 sprocket holes is ±0.20.
4. Measured from centreline of sprocket hole to centreline of pocket.
5. Other material available.
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AS7261 − Soldering & Storage Information
Soldering & Storage
Information
Soldering Information
The module has been tested and has demonstrated an ability
to be reflow soldered to a PCB substrate. The solder reflow
profile describes the expected maximum heat exposure of
components during the solder reflow process of product on a
PCB. Temperature is measured on top of component. The
components should be limited to a maximum of three passes
through this solder reflow profile.
Figure 38:
Solder Reflow Profile
Parameter
Reference
Device
Average temperature gradient in preheating
Soak time
2.5 ºC/s
tsoak
2 to 3 minutes
Time above 217°C (T1)
t1
Max 60 s
Time above 230°C (T2)
t2
Max 50 s
Time above Tpeak - 10ºC (T3)
t3
Max 10 s
Tpeak
260 ºC
Peak temperature in reflow
Temperature gradient in cooling
Max -5 ºC/s
Figure 39:
Solder Reflow Profile Graph
Tpeak
Not to scale — for reference only
T3
T2
Temperature (5C)
T1
Time (s)
t3
t2
tsoak
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t1
ams Datasheet
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AS7261 − Soldering & Storage Information
Manufacturing Process Considerations
The AS7261 package is compatible with standard reflow
no-clean and cleaning processes including aqueous, solvent or
ultrasonic techniques. However, as an open-aperture device,
precautions must be taken to avoid particulate or solvent
con-tamination as a result of any manufacturing processes,
including pick and place, reflow, cleaning, integration assembly
and/or testing. Temporary covering of the ap-erture is allowed.
To avoid degradation of accuracy or performance in the end
prod-uct, care should be taken that any temporary covering and
associated seal-ants/debris are thoroughly removed prior to
any optical testing or final packaging.
Storage Information
Moisture Sensitivity
Optical characteristics of the device can be adversely affected
during the soldering process by the release and vaporization of
moisture that has been previously absorbed into the package.
To ensure the package contains the smallest amount of
absorbed moisture possible, each device is baked prior to being
dry packed for shipping.
Devices are dry packed in a sealed aluminized envelope called
a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before
use.
Shelf Life
The calculated shelf life of the device in an unopened moisture
barrier bag is 12 months from the date code on the bag when
stored under the following conditions:
• Shelf Life: 12 months
• Ambient Temperature: < 40°C
• Relative Humidity: < 90%
Rebaking of the devices will be required if the devices exceed
the 12 month shelf life or the Humidity Indicator Card shows
that the devices were exposed to conditions beyond the allowable moisture region.
ams Datasheet
[v1-00] 2016-Dec-30
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AS7261 − Soldering & Storage Information
Floor Life
The CS package has been assigned a moisture sensitivity level
of MSL 2. As a result, the floor life of devices removed from the
moisture barrier bag is 1 year from the time the bag was opened,
provided that the devices are stored under the following
conditions:
• Floor Life: 1 year
• Ambient Temperature:
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