KXCJ9-1008-FR

PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications Product Description N ot R The KXCJ9 is a tri-axis +/-2g, +/-4g or +/-8g silicon micromachined accelerometer. The sense element is fabricated using Kionix’s proprietary plasma micromachining process technology. Acceleration sensing is based on the principle of a differential capacitance arising from acceleration-induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process variation, temperature, and environmental stress. The sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. A separate ASIC device packaged with the sense element provides signal conditioning and digital communications. The accelerometer is delivered in a 3 x 3 x 0.9 mm LGA plastic package operating from a 1.8 – 3.6V DC supply. Voltage regulators are used to maintain constant internal operating voltages over the range of input supply voltages. This results in stable operating characteristics over the range of input supply voltages and virtually undetectable ratiometric error. The I2C digital protocol is used to communicate with the chip to configure the part and monitor outputs. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 1 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications Functional Diagram X Sensor Y Sensor Charge Amp A/D Z Sensor Digital Filter Vdd 5 2 I C Digital Engine IO Vdd 1 GND 4 6 8 9 10 INT N ot R RSVD ADDR SCL SDA 7 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 2 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 Product Specifications Table 1. Mechanical (specifications are for operation at 2.6V and T = 25C unless stated otherwise) Parameters Units Min Typical Max Operating Temperature Range ºC -40 - 85 Zero-g Offset mg - ±25 ±125 922 1024 1126 922 1024 1126 461 512 563 230 256 282 57 64 71 28 32 36 16 18 Zero-g Offset Variation from RT over Temp. Sensitivity (14-bit) 1,2 GSEL1=1, GSEL0=1 (± 8g) mg/ºC counts/g GSEL1=0, GSEL0=0 (± 2g) Sensitivity (12-bit) 1 GSEL1=0, GSEL0=1 (± 4g) counts/g GSEL1=1, GSEL0=0 (± 8g) GSEL1=0, GSEL0=0 (± 2g) Sensitivity (8-bit) 1 GSEL1=0, GSEL0=1 (± 4g) counts/g GSEL1=1, GSEL0=0 (± 8g) Sensitivity Variation from RT over Temp. Self Test Output change on Activation Mechanical Resonance (-3dB) Non-Linearity Cross Axis Sensitivity Notes: 3 0.2 14 %/ºC 0.03 g 1 (x) 0.8 (y) 0.6 (z) Hz 3500 (xy) 1800 (z) % of FS 0.6 % 2 2 N ot R 1. Resolution and acceleration ranges are user selectable via I C. 2. 14-bit Resolution is only available for registers 0x06h – 0x0Bh in the 8g Full Power mode 3. Resonance as defined by the dampened mechanical sensor. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 3 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 Table 2. Electrical (specifications are for operation at 2.6V and T = 25C unless stated otherwise) Parameters Units Min Supply Voltage (Vdd) Operating I/O Pads Supply Voltage (VIO) V 1.71 V 1.7 Full Power Mode (RES = 1) 1 Current Consumption Low Power Mode (RES = 0) A V 2 Output Low Voltage (Vio > 2V) Output High Voltage Input Low Voltage Input High Voltage Start Up Time Power Up Time 2 - 0.2 * Vio V - - 0.4 V 0.8 * Vio - - V - - 0.2 * Vio V 0.8 * Vio - - 6 650 10 MHz 3.4 5 Hz RES = 0 Hz 800 RES = 1 Hz ODR/2 Output Data Rate (ODR) Bandwidth (-3dB) 0 2.0 ms I C Communication Rate Vdd - ms 4 3.6 10 A 3 2.6 0.9 2 Input Pull-down Current Max 135 Disabled Output Low Voltage (Vio < 2V) Typical 0.781 50 1600 N ot R Notes: 1. Current varies with Output Data Rate (ODR) see table below. 2 2. For I C communication, this assumes a minimum 1.5k pull-up resistor on SCL and SDA pins. 3. Start up time is from PC1 set to valid outputs. Time varies with Output Data Rate (ODR); see chart below. 4. Power up time is from Vdd and IO_Vdd valid to device boot completion. 2 5. User selectable through I C. 6. User selectable and dependent on ODR and RES. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 4 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 Table 3 Current Profile KXCJ9 Representative Current Profile ODR (Hz) RES Current (μA) 0 0.781 1.563 3.125 6.25 12.5 25 50 100 200 400 800 1600 All Rates Disabled 0 0 0 0 0 0 0 0 0 0 0 0 1 0.9 1.7 2 2.2 3.3 5 9 16 29 57 120 120 120 120 KXCJ9 Representative Current (µA) R 1000 120 N Current (μA) ot 100 120 120 57 29 16 10 9 RES = 0 5 3.3 1.7 2 Full Power Mode 2.2 1 0.1 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com 1 10 100 1000 10000 ODR (Hz) © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 5 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications Table 4 Start Up Time Profile KXCJ9 Representative Start Up Time ODR (Hz) Start Up Time (ms) 12.5 80 25 41 50 21 100 11 200 6.4 400 3.9 800 2.7 1600 2.1 KXCJ9 Start Up Time (ms) 80 41 21 11 10 6.4 3.9 2.7 2.1 1 1 10 100 1000 10000 ODR (Hz) N ot R Start Up Time (ms) 100 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 6 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications Table 5. Environmental Parameters Units Min Typical Max V -0.5 - 3.63 Operating Temperature Range ºC -40 - 85 Storage Temperature Range ºC -55 - 150 Mech. Shock (powered and unpowered) g - - 5000 for 0.5ms 10000 for 0.2ms ESD V - - 2000 Supply Voltage (Vdd) Absolute Limits HBM Caution: ESD Sensitive and Mechanical Shock Sensitive Component, improper handling can cause permanent damage to the device. This product conforms to Directive 2002/95/EC of the European Parliament and of the Council of the European Union (RoHS). Specifically, this product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or polybrominated diphenyl ethers (PBDE) above the maximum concentration values (MCV) by weight in any of its homogenous materials. Homogenous materials are "of uniform composition throughout." This product is halogen-free per IEC 61249-2-21. Specifically, the materials used in this product contain a maximum total halogen content of 1500 ppm with less than 900-ppm bromine and less than 900-ppm chlorine. R HF ot Soldering N Soldering recommendations are available upon request or from www.kionix.com. Floor Life Factory floor life exposure of the KXCJ9 reels removed from the moisture barrier bag should not exceed a maximum of 168 hours at 30C/60%RH. If this floor life is exceeded, the parts should be dried per the IPC/JEDEC J-STD-033A standard. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 7 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications Application Schematic SDA 10 IO Vdd 1 9 SCL 2 8 ADDR 3 7 INT 4 6 KXCJ9 C2 5 C1 R Vdd ot Table 6. KXCJ9 Pin Descriptions N Pin Name Description DNC DNC The power supply input for the digital communication bus. Optionally decouple this pin to ground with a 0.1uF ceramic capacitor. Reserved – Do Not Connect Reserved – Do Not Connect 4 GND Ground 5 6 7 8 9 10 Vdd RSVD INT ADDR SCL SDA 1 2 3 IO Vdd 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com The power supply input. Decouple this pin to ground with a 0.1uF ceramic capacitor. Reserved – Connect to Vdd, IO Vdd, or GND Physical Interrupt I2C programmable address bit – Connect to IO_Vdd or GND I2C Serial Clock I2C Serial Data © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 8 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 Test Specifications ! Special Characteristics: These characteristics have been identified as being critical to the customer. Every part is tested to verify its conformance to specification prior to shipment. Table 7. Test Specifications N ot R Parameter Specification Test Conditions Zero-g Offset @ RT 0 +/- 128 counts 25C, Vdd = 2.6 V Sensitivity @ RT 1024 +/- 102 counts/g 25C, Vdd = 2.6 V 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 9 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 Package Dimensions and Orientation N ot R 3 x 3 x 0.9 mm LGA All dimensions and tolerances conform to ASME Y14.5M-1994 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 10 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r Orientation KXCJ9-1008 Rev. 5 Dec-2012 +Y Pin 1 +X +Z When device is accelerated in +X, +Y or +Z direction, the corresponding output will increase. Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g): GSEL1=0, GSEL0=0 (± 2g) Position 1 2 3 4 Diagram R Resolution (bits) X (counts) Y (counts) Z (counts) N ot X-Polarity Y-Polarity Z-Polarity 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com 12 8 12 8 12 8 0 1024 64 0 0 0 1024 64 0 0 -1024 -64 0 0 0 0 0 0 0 0 + 0 + 0 0 0 0 5 Top 6 Bottom Bottom Top 12 8 12 8 12 8 -1024 -64 0 0 0 0 0 0 0 0 0 0 0 0 1024 64 -1024 -64 0 0 0 0 + 0 0 - (1g) Earth’s Surface © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 11 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g): GSEL1=0, GSEL0=1 (± 4g) Position 1 2 3 4 Diagram Resolution (bits) X (counts) Y (counts) Z (counts) X-Polarity Y-Polarity Z-Polarity 12 8 0 0 512 32 0 0 0 0 + 0 12 512 0 0 8 32 0 0 12 0 -512 0 + 0 0 8 0 -32 0 12 -512 0 0 0 0 8 -32 0 0 0 0 5 Top 6 Bottom Bottom Top 12 0 0 512 8 0 0 32 12 0 0 -512 0 0 + 8 0 0 -32 0 0 - (1g) Earth’s Surface Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g): GSEL1=1, GSEL0=0 (± 8g) 1 2 3 4 R Position N ot Diagram Resolution (bits) X (counts) Y (counts) Z (counts) X-Polarity Y-Polarity Z-Polarity 12 8 0 0 256 16 0 0 0 0 + 0 12 256 0 0 8 16 0 0 + 0 0 12 0 -256 0 8 0 -16 0 0 0 (1g) 12 -256 0 0 8 -16 0 0 0 0 5 Top 6 Bottom Bottom Top 12 0 0 256 0 0 + 8 0 0 16 12 0 0 -256 8 0 0 -16 0 0 - Earth’s Surface 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 12 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXCJ9 Digital Interface The Kionix KXCJ9 digital accelerometer has the ability to communicate on the I2C digital serial interface bus. This allows for easy system integration by eliminating analog-to-digital converter requirements and by providing direct communication with system micro-controllers. The serial interface terms and descriptions as indicated in Table 8 below will be observed throughout this document. Term Transmitter Receiver Master Slave Description The device that transmits data to the bus. The device that receives data from the bus. The device that initiates a transfer, generates clock signals, and terminates a transfer. The device addressed by the Master. Table 8. Serial Interface Terminologies I2C Serial Interface As previously mentioned, the KXCJ9 has the ability to communicate on an I2C bus. I2C is primarily used for synchronous serial communication between a Master device and one or more Slave devices. The Master, typically a micro controller, provides the serial clock signal and addresses Slave devices on the bus. The KXCJ9 always operates as a Slave device during standard Master-Slave I2C operation. N ot R I2C is a two-wire serial interface that contains a Serial Clock (SCL) line and a Serial Data (SDA) line. SCL is a serial clock that is provided by the Master, but can be held low by any Slave device, putting the Master into a wait condition. SDA is a bi-directional line used to transmit and receive data to and from the interface. Data is transmitted MSB (Most Significant Bit) first in 8-bit per byte format, and the number of bytes transmitted per transfer is unlimited. The I2C bus is considered free when both lines are high. The I2C interface is compliant with high-speed mode, fast mode and standard mode I2C standards. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 13 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications SDA SCL IO_Vdd SDA MCU SCL SDA KXCJ9 SCL ADDR SDA KXCJ9 SCL ADDR Figure 1. Multiple KXCJ9 I2C Connection I2C Operation N ot R Transactions on the I2C bus begin after the Master transmits a start condition (S), which is defined as a highto-low transition on the data line while the SCL line is held high. The bus is considered busy after this condition. The next byte of data transmitted after the start condition contains the Slave Address (SAD) in the seven MSBs (Most Significant Bits), and the LSB (Least Significant Bit) tells whether the Master will be receiving data ‘1’ from the Slave or transmitting data ‘0’ to the Slave. When a Slave Address is sent, each device on the bus compares the seven MSBs with its internally stored address. If they match, the device considers itself addressed by the Master. The KXCJ9’s Slave Address is comprised of a programmable part and a fixed part, which allows for connection of multiple KXCJ9's to the same I2C bus. The Slave Address associated with the KXCJ9 is 000111X, where the programmable bit, X, is determined by the assignment of ADDR (pin 8) to GND or IO_Vdd. Figure 1 above shows how two KXCJ9's would be implemented on an I2C bus. It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter must release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it remains stable low during the high period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or Slave, is obliged to generate an ACK after each byte of data has been received. To conclude a transaction, the Master must transmit a stop condition (P) by transitioning the SDA line from low to high while SCL is high. The I2C bus is now free. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 14 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications Writing to a KXCJ9 8-bit Register Upon power up, the Master must write to the KXCJ9’s control registers to set its operational mode. Therefore, when writing to a control register on the I2C bus, as shown Sequence 1 on the following page, the following protocol must be observed: After a start condition, SAD+W transmission, and the KXCJ9 ACK has been returned, an 8-bit Register Address (RA) command is transmitted by the Master. This command is telling the KXCJ9 to which 8-bit register the Master will be writing the data. Since this is I 2C mode, the MSB of the RA command should always be zero (0). The KXCJ9 acknowledges the RA and the Master transmits the data to be stored in the 8-bit register. The KXCJ9 acknowledges that it has received the data and the Master transmits a stop condition (P) to end the data transfer. The data sent to the KXCJ9 is now stored in the appropriate register. The KXCJ9 automatically increments the received RA commands and, therefore, multiple bytes of data can be written to sequential registers after each Slave ACK as shown in Sequence 2 on the following page. Reading from a KXCJ9 8-bit Register R When reading data from a KXCJ9 8-bit register on the I2C bus, as shown in Sequence 3 on the next page, the following protocol must be observed: The Master first transmits a start condition (S) and the appropriate Slave Address (SAD) with the LSB set at ‘0’ to write. The KXCJ9 acknowledges and the Master transmits the 8-bit RA of the register it wants to read. The KXCJ9 again acknowledges, and the Master transmits a repeated start condition (Sr). After the repeated start condition, the Master addresses the KXCJ9 with a ‘1’ in the LSB (SAD+R) to read from the previously selected register. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NACK) it received the transmitted data, but transmits a stop condition to end the data transfer. Note that the KXCJ9 automatically increments through its sequential registers, allowing data to be read from multiple registers following a single SAD+R command as shown below in Sequence 4 on the following page. The 8-bit register data is transmitted using a left-most format, first bit shifted/clocked out being the MSB bit. N ot If a receiver cannot transmit or receive another complete byte of data until it has performed some other function, it can hold SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases SCL. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 15 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 Data Transfer Sequences The following information clearly illustrates the variety of data transfers that can occur on the I 2C bus and how the Master and Slave interact during these transfers. Table 9 defines the I2C terms used during the data transfers. Term S Sr SAD W R ACK NACK RA Data P Definition Start Condition Repeated Start Condition Slave Address Write Bit Read Bit Acknowledge Not Acknowledge Register Address Transmitted/Received Data Stop Condition Table 9. I2C Terms Sequence 1. The Master is writing one byte to the Slave. S SAD + W RA ACK R Master Slave DATA ACK P ACK Sequence 2. The Master is writing multiple bytes to the Slave. S SAD + W ot Master Slave RA ACK DATA ACK DATA ACK P ACK N Sequence 3. The Master is receiving one byte of data from the Slave. Master Slave S SAD + W RA ACK Sr SAD + R ACK NACK ACK P DATA Sequence 4. The Master is receiving multiple bytes of data from the Slave. Master Slave S SAD + W 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com RA ACK Sr ACK SAD + R ACK ACK DATA NACK DATA © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 16 of 31 P PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 KXCJ9 Embedded Registers The KXCJ9 has 25 embedded 8-bit registers that are accessible by the user. This section contains the addresses for all embedded registers and also describes bit functions of each register. Table 10 below provides a listing of the accessible 8-bit registers and their addresses. N ot R Register Name Type Read/Write I2C Address Hex Binary Kionix Reserved - 0x00 – 0x05 - XOUT_L R 0x06 0000 0110 XOUT_H R 0x07 0000 0111 YOUT_L R 0x08 0000 1000 YOUT_H R 0x09 0000 1001 ZOUT_L R 0x0A 0000 1010 ZOUT_H R 0x0B 0000 1011 DCST_RESP R 0x0C 0000 1100 Kionix Reserved - 0x0D – 0x0E - WHO_AM_I R 0x0F 0000 1111 Kionix Reserved - 0x10 – 0x15 - INT_SOURCE1 R 0x16 0001 0110 INT_SOURCE2 R 0x17 0001 0111 STATUS_REG R 0x18 0001 1000 Kionix Reserved - 0x19 - INT_REL R 0x1A 0001 1010 CTRL_REG1* R/W 0x1B 0001 1011 Kionix Reserved - 0x1C 0001 1100 CTRL_REG2* R/W 0x1D 0001 1101 INT_CTRL_REG1* R/W 0x1E 0001 1110 INT_CTRL_REG2* R/W 0x1F 0001 1111 Kionix Reserved - 0x20 0010 0000 DATA_CTRL_REG* R/W 0x21 0010 0001 Kionix Reserved - 0x22 – 0x28 - WAKEUP_TIMER* R/W 0x29 0010 1001 Kionix Reserved - 0x2A – 0x39 - SELF_TEST R/W 0x3A 0011 1010 Kionix Reserved - 0x3B – 0x69 - WAKUP_THRESHOLD* R/W 0x6A 0110 1010 * Note: When changing the contents of these registers, the PC1 bit in CTRL_REG1 must first be set to “0”. Table 10. KXCJ9 Register Map 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 17 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXCJ9 Register Descriptions Accelerometer Outputs These registers contain up to 12-bits of valid acceleration data for each axis depending on the setting of the RES bit in CTRL_REG1, where the acceleration outputs are represented in 12-bit valid data when RES = ‘1’ and 8-bit valid data when RES = ‘0’. The data is updated every user-defined ODR period, is protected from overwrite during each read, and can be converted from digital counts to acceleration (g) per Table 11 below. The register acceleration output binary data is represented in 2’s complement format. For example, if N = 12 bits, then the Counts range is from -2048 to 2047, and if N = 8 bits, then the Counts range is from -128 to 127. 12-bit Register Data Equivalent (2’s complement) Counts in decimal Range = +/-4g Range = +/-8g 0111 1111 1111 2047 +1.999g +3.998g +7.996g 0111 1111 1110 2046 +1.998g +3.996g +7.992g … … … … … 0000 0000 0001 1 +0.001g +0.002g +0.004g 0 0.000g 0.000g 0.000g 1111 1111 1111 -1 -0.001g -0.002g -0.004g … … … … … 1000 0000 0001 -2047 -1.999g -3.998g -7.996g 1000 0000 0000 -2048 -2.000g -4.000g -8.000g Range = +/-2g Range = +/-4g Range = +/-8g R 0000 0000 0000 8-bit Register Data Equivalent (2’s complement) Counts in decimal 0111 1111 127 +1.984g +3.968g +7.936g 0111 1110 126 +1.968g +3.936g +7.872g ot N Range = +/-2g … … … … … 0000 0001 1 +0.016g +0.032g +0.064g 0000 0000 0 0.000g 0.000g 0.000g 1111 1111 -1 -0.016g -0.032g -0.064g … … … … … 1000 0001 -127 -1.984g -3.968g -7.936g 1000 0000 -128 -2.000g -4.000g -8.000g Table 11. Acceleration (g) Calculation 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 18 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications XOUT_L X-axis accelerometer output least significant byte R XOUTD3 Bit7 R XOUTD2 Bit6 R XOUTD1 Bit5 R XOUTD0 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 2 I C Address: 0x06h XOUT_H X-axis accelerometer output most significant byte R R R XOUTD11 XOUTD10 XOUTD9 Bit7 Bit6 Bit5 R XOUTD8 Bit4 R XOUTD7 Bit3 R R R XOUTD6 XOUTD5 XOUTD4 Bit2 Bit1 Bit0 2 I C Address: 0x07h YOUT_L Y-axis accelerometer output least significant byte R YOUTD3 Bit7 R YOUTD2 Bit6 R YOUTD1 Bit5 R YOUTD0 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 2 I C Address: 0x08h R YOUT_H Y-axis accelerometer output most significant byte R YOUTD8 Bit4 R YOUTD7 Bit3 R R R YOUTD6 YOUTD5 YOUTD4 Bit2 Bit1 Bit0 2 I C Address: 0x09h N ot R R R YOUTD11 YOUTD10 YOUTD9 Bit7 Bit6 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 19 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications ZOUT_L Z-axis accelerometer output least significant byte R ZOUTD3 Bit7 R ZOUTD2 Bit6 R ZOUTD1 Bit5 R ZOUTD0 Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 2 I C Address: 0x0Ah ZOUT_H Z-axis accelerometer output most significant byte R ZOUTD8 Bit4 R ZOUTD7 Bit3 R R R ZOUTD6 ZOUTD5 ZOUTD4 Bit2 Bit1 Bit0 2 I C Address: 0x0Bh N ot R R R R ZOUTD11 ZOUTD10 ZOUTD9 Bit7 Bit6 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 20 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications DCST_RESP This register can be used to verify proper integrated circuit functionality. It always has a byte value of 0x55h unless the DCST bit in CTRL_REG3 is set. At that point this value is set to 0xAAh. The byte value is returned to 0x55h after reading this register. R DCSTR7 Bit7 R DCSTR6 Bit6 R DCSTR5 Bit5 R DCSTR4 Bit4 R DCSTR3 Bit3 R DCSTR2 Bit2 R R DCSTR1 DCSTR0 Bit1 Bit0 2 I C Address: 0x0Ch Reset Value 01010101 WHO_AM_I This register can be used for supplier recognition, as it can be factory written to a known byte value. The default value is 0x0Ah. R WIA6 Bit6 R WIA5 Bit5 R WIA4 Bit4 R WIA3 Bit3 R WIA2 Bit2 R R WIA1 WIA0 Bit1 Bit0 2 I C Address: 0x0Fh Reset Value 00001010 R R WIA7 Bit7 N ot Interrupt Source Registers These two registers report interrupt state changes. This data is updated when a new interrupt event occurs and each application’s result is latched until the interrupt release register is read. The programmable interrupt engine can be configured to report data in an unlatched manner via the interrupt control registers. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 21 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications INT_SOURCE1 This register reports which function caused an interrupt. Reading from the interrupt release register (INT_REL, 0x1Ah) will clear the entire contents of this register. R 0 Bit7 R 0 Bit6 R 0 Bit5 R DRDY Bit4 R 0 Bit3 R 0 Bit2 R R WUFS 0 Bit1 Bit0 2 I C Address: 0x16h DRDY - indicates that new acceleration data (at Reg Addr 0x06h to 0x0Bh) is available. This bit is cleared when acceleration data is read or the interrupt release register (INT_REL, 0x1Ah) is read. 0 = New acceleration data not available 1 = New acceleration data available WUFS - Wake up, This bit is cleared when the interrupt source latch register (INT_REL, ox1Ah) is read. 0 = No motion 1 = Motion has activated the interrupt INT_SOURCE2 This register reports the axis and direction of detected motion per Table 12. This register is cleared when the interrupt source latch register (INT_REL, 0x1Ah) is read. R XNWU Bit5 R R 0 Bit6 N ot R 0 Bit7 R XPWU Bit4 Bit XNWU XPWU YNWU YPWU ZNWU ZPWU R YNWU Bit3 R YPWU Bit2 R R ZNWU ZPWU Bit1 Bit0 2 I C Address: 0x17h Description X Negative (X-) Reported X Positive (X+) Reported Y Negative (Y-) Reported Y Positive (Y+) Reported Z Negative (Z-) Reported Z Positive (Z+) Reported Table 12. KXCJ9 Motion Reporting 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 22 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications STATUS_REG This register reports the status of the interrupt. R 0 Bit7 R 0 Bit6 R 0 Bit5 R INT Bit4 R 0 Bit3 R 0 Bit2 R R 0 0 Bit1 Bit0 2 I C Address: 0x18h INT reports the combined (OR) interrupt information of DRDY and WUFS in the interrupt source register (INT_SOURCE1, 0x16h). This bit is cleared when acceleration data is read or the interrupt release register (INT_REL, 1Ah) is read. 0 = no interrupt event 1 = interrupt event has occurred INT_REL Latched interrupt source information (INT_SOURCE1, 0x16h and INT_SOURCE2, 0x17h) is cleared and physical interrupt latched pin (7) is changed to its inactive state when this register is read. R X Bit6 R X Bit5 R X Bit4 R X Bit3 R X Bit2 R R X X Bit1 Bit0 2 I C Address: 0x1Ah N ot R R X Bit7 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 23 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 CTRL_REG1 Read/write control register that controls the main feature set. R/W PC1 Bit7 R/W RES Bit6 R/W DRDYE Bit5 R/W GSEL1 Bit4 R/W GSEL0 Bit3 R/W 0 Bit2 R/W R/W WUFE 0 Bit1 Bit0 2 I C Address: 0x1Bh Reset Value 00000000 PC1 controls the operating mode of the KXCJ9. 0 = disabled mode 1 = operating mode RES determines the performance mode of the KXCJ9. Note that to change the value of this bit, the PC1 bit must first be set to “0”. 0 = low current, 8-bit valid. Only available for ODR = 400Hz will force device into Full Power mode 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 27 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications WAKEUP_TIMER This register sets the time motion must be present before a wake-up interrupt is set. Every count is calculated as 1/OWUF delay period. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. Valid Entries are 1 to 255, zero is excluded. R/W WUFC7 Bit7 R/W WUFC6 Bit6 R/W WUFC5 Bit5 R/W WUFC4 Bit4 R/W WUFC3 Bit3 R/W WUFC2 Bit2 R/W R/W WUFC1 WUFC0 Bit1 Bit0 2 I C Address: 0x29h Reset Value 00000000 SELF_TEST When 0xCA is written to this register, the MEMS self-test function is enabled. Electrostatic-actuation of the accelerometer, results in a DC shift of the X, Y and Z axis outputs. Writing 0x00 to this register will return the accelerometer to normal operation. R/W 1 Bit7 R/W 1 Bit6 R/W 0 Bit5 R/W 0 Bit4 R/W 1 Bit3 R/W 0 Bit2 R/W R/W 1 0 Bit1 Bit0 2 I C Address: 0x3Ah Reset Value 00000000 ot R WAKEUP_THRESHOLD This register sets the threshold for wake-up (motion detect) interrupt is set. The KXCJ9 will ship from the factory with this value set to correspond to a change in acceleration of 0.5g. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W WUTH6 Bit6 R/W WUTH5 Bit5 N R/W WUTH7 Bit7 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R/W WUTH4 Bit4 R/W WUTH3 Bit3 R/W WUTH2 Bit2 R/W R/W WUTH1 WUTH0 Bit1 Bit0 2 I C Address: 0x6Ah Reset Value 00001000 © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 28 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXCJ9 Embedded Wake Up Function The KXCJ9 contains an interrupt engine that can be configured by the user to report when qualified changes in acceleration occur. The user has the option to enable or disable specific axes and specific directions, as well as to specify the delay time. An example use case for the engine would be to detect motion on any axis to signal an event and wake up the accelerometer or other devices. This can be achieved by configuring the engine to detect when the acceleration on any axis is greater than the user-defined threshold for a userdefined amount of time. Equations 1 and 2 show how to calculate the engine threshold (WAKEUP_THRESHOLD) and delay time (WAKEUP_TIMER) register values for the desired result. WAKEUP_THRESHOLD (counts) = Desired Threshold (g) x 16 (counts/g) Equation 1. Wake Up Threshold WAKEUP_TIMER (counts) = Desired Delay Time (sec) x OWUF (Hz) N ot R Equation 2. Wake Up Delay Time 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 29 of 31 PART NUMBER: KXCJ9-1008 Rev. 5 Dec-2012 e N co ew m m D es en ig de ns d fo r ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications Figure 2 below shows the latched response of the Wake Up Function with WUF Timer = 10 counts. Typical Wake Up Interrupt Example Acceleration WUF Threshold 0g 10 WUF Timer Ex: Delay Counter = 10 Motion Figure 2. Latched Motion Interrupt Response ot R Inactive N The KXCJ9-1008 wake-up function is always latched. However, if the INT_CTROL_REG1 is set with IEL = 1, then upon a wake-up event the WUF interrupt signal will pulse and return low, but only once. The WUF interrupt output will not reset until a read of the INT_REL latch reset register. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 30 of 31 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications e N co ew m m D es en ig de ns d fo r KXCJ9-1008 Rev. 5 Dec-2012 Revision History DESCRIPTION Production Release Included Floor Life specification Included Table of Start Up Time Revised Power Up Time footnote Updated ADDR Pin description DATE 24-Jul-2012 02-Aug-2012 03-Aug-2012 08-Aug-2012 03-Dec-2012 ot R REVISION 1 2 3 4 5 N "Kionix" is a registered trademark of Kionix, Inc. Products described herein are protected by patents issued or pending. No license is granted by implication or otherwise under any patent or other rights of Kionix. The information contained herein is believed to be accurate and reliable but is not guaranteed. Kionix does not assume responsibility for its use or distribution. Kionix also reserves the right to change product specifications or discontinue this product at any time without prior notice. This publication supersedes and replaces all information previously supplied. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2012 Kionix – All Rights Reserved 564-4177-1212061615 Page 31 of 31