SIT5002AC-GE-33E0-100.000000Y

SiT5002 Preliminary 80-220 MHz MEMS TCXO and VCTCXO The Smart Timing Choice The Smart Timing Choice Features Applications  Any frequency between 80.000001 and 220 MHz accurate to 6 decimal places  100% pin-to-pin drop-in replacement to quartz-based (VC)TCXO  Frequency stability as low as ±5 ppm. Contact SiTime for tighter stability options  Ultra low phase jitter: 0.5 ps (12 kHz to 20 MHz)  Voltage control option with pull range from ±12.5 ppm to ±50 ppm  LVCMOS/HCMOS compatible output  Voltage control, standby, output enable or no connect modes  Standard 4-pin packages: 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mm  Outstanding silicon reliability of 2 FIT, 10 times better than quartz  Pb-free, RoHs and REACH compliant  Ideal for telecom, networking, smart meter, GPS and wireless applications Electrical Characteristics Parameter Output Frequency Range Initial Tolerance Stability Over Temperature Symbol Min. Typ. Max. Unit f 80.000001 – 220 MHz Condition F_init -1.5 – 1.5 ppm At 25°C after two reflows F_stab -5 – +5 ppm Over operating temperature range at rated nominal power supply voltage and load. (see ordering codes on page 5) Contact SiTime for tighter stability options. Supply Voltage F_vdd – 0.05 – ppm ±10% Vdd (±5% for Vdd = 1.8V) Output Load F_load – 0.1 – ppm ±10% of 15 pF load First year Aging F_aging 10-year Aging Operating Temperature Range Supply Voltage Pull Range T_use Vdd -2.5 – +2.5 ppm -4.0 – +4.0 ppm -20 – +70 °C Extended Commercial -40 – +85 °C Industrial 1.71 1.8 1.89 V Contact SiTime for any other supply voltage options. 2.25 2.5 2.75 V 2.52 2.8 3.08 V 2.70 3.0 3.3 V 2.97 3.3 3.63 V PR ±12.5, ±25, ±50 ppm Upper Control Voltage VC_U Vdd-0.1 – – V Control Voltage Range VC_L – – 0.1 V Control Voltage Input Impedance Z_vc 100 – – k Frequency Change Polarity Control Voltage -3dB Bandwidth Current Consumption – 25°C Positive slope All Vdds. Voltage at which maximum deviation is guaranteed. – V_BW – – 8 kHz Idd – 31 33 mA No load condition, f = 20 MHz, Vdd = 2.5V, 2.8V or 3.3V. – 29 31 mA No load condition, f = 20 MHz, Vdd = 1.8V. – 31 mA Vdd = 2.5V, 2.8V or 3.3V, OE = GND, output is Weakly Pulled OE Disable Current I_OD – – – 30 mA Vdd = 1.8 V. OE = GND, output is Weakly Pulled Down Standby Current I_std – – 70 µA Vdd = 2.5V, 2.8V or 3.3V, ST = GND, output is Weakly Pulled Down. – – 10 µA Vdd = 1.8V. ST = GND, output is Weakly Pulled Down. DC 45 – 55 % All Vdds LVCMOS Rise/Fall Time Tr, Tf – 1.5 2 ns LVCMOS option. Default rise/fall time, All Vdds, 10% - 90% Vdd. Duty Cycle Output Voltage High VOH 90% – – Vdd Output Voltage Low VOL – – 10% Vdd Input Voltage High VIH 70% – – Vdd OH = -7 mA, IOL = 7 mA, (Vdd = 3.3V, 3.0V) IOH = -4 mA, IOL = 4 mA, (Vdd = 2.8V, 2.5V) IOH = -2 mA, IOL = 2 mA, (Vdd = 1.8V) Pin 1, OE or ST Input Voltage Low VIL – – 30% Vdd Pin 1, OE or ST Input Pull-up Impedance Z_in – 100 250 k SiTime Corporation Rev. 1.0 990 Almanor Avenue Sunnyvale, CA 94085 (408) 328-4400 www.sitime.com Revised November 12, 2015 SiT5002 80-220 MHz MEMS TCXO and VCTCXO The Smart Timing Choice The Smart Timing Choice Electrical Characteristics (continued) Parameter Startup Time OE Enable/Disable Time Symbol Min. Typ. Max. Unit Condition T_start – – 10 ms Measured from the time Vdd reaches its rated minimum value f = 80 MHz. For other frequencies, T_oe = 100 ns + 3 cycles T_oe – – 150 ns T_resume – 6 10 ms Measured from the time ST pin crosses 50% threshold RMS Period Jitter T_jitt – 1.7 2 ps f = 10 MHz, Vdd = 2.5V, 2.8V or 3.3V – 1.7 2 ps f = 10 MHz, Vdd = 1.8V RMS Phase Jitter (random) T_phj – 0.5 1 ps f = 10 MHz, Integration bandwidth = 12 kHz to 20 MHz, All Vdds Resume Time Note: 1. All electrical specifications in the above table are measured with 15pF output load, Contact SiTime for higher drive options. Pin Configuration Pin Symbol Functionality V control 1 Voltage control Output Enable H or Open[2]: specified frequency output L: output is high impedance. Only output driver is disabled. Standby H or Open[2]: specified frequency output L: output is low (weak pull down). Device goes to sleep mode. Supply current reduces to I_std. VC/OE/ST/NC NC Top View VC/OE/ST 1 4 VDD GND 2 3 OUT No connect (input receiver off) 2 GND Power Electrical and case ground 3 CLK Output Oscillator output 4 VDD Power Power supply voltage Note: 2. A pull-up resistor of