SLG55021-200010V

 SLG55021-200010 High Voltage Gate Driver Features Pin Configuration 5 V ±5% Power supply • SLG55021 Drain Voltage Range 1.0 V to 20 V • Internal Gate Voltage Charge Pump • Controlled Turn on Delay • Controlled Load Discharge Rate • Controlled Turn on Slew Rate • Stable Slew Rate (±2% typ) over Temperature Range • TDFN-8 Package • Pb-Free / Halogen-Free / RoHS compliant VCC 1 ON 2 SHDN# 3 GND 4 SLG55021 • 8 PG 7 G 6 S 5 D TDFN-8 (Top View) Applications • Power Rail Switches • Hot Plugging Applications • Soft Switching • Personal computers and Servers • Data Communications Equipment Block Diagram CC D 1 ON SHDN# 2 3 Q-PUMP 5 + 7 D G _ Timing & Logic 8 PG 6 S Discharge LOAD 4 G SLG55021 For N-MOSFETS with VGS < 20V Datasheet CFR0011-120-01 Revision 1.05 Page 1 of 8 9-Feb-2022 ©2022 Renesas Electronics Corporation  SLG55021-200010 High Voltage Gate Driver Pin Description Pin # Pin Name Type Pin Description VCC 1 Power Supply Voltage ON 2 Input CMOS Logic Level. High True SHDN# 3 Input Shut Down# - Low True Signal which immediately turns FET off GND 4 GND Ground D 5 Input FET Drain Connection Source Connection S 6 Input G 7 Output FET Gate Drive PG 8 Output Output CMOS Open Drain - Power Good, indicates external FET fully on Overview The SLG55021 N-Channel FET Gate Driver is used for controlling a delayed turn on and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level input. Intended as a supporting control element for switched voltage rails in energy efficient, advanced power management systems, the SLG55021 also integrates circuits to discharge opened switched voltage rails. The gate driver is available in a variety of configurations supporting a range of turn-on slew rates from 0.80 V/ms up to 4 V/ms which, depending on load supplying source voltages in the range of 1.0 V to 20 V results in ramp times from 200 µs up to over 20 ms (see Application Section). Delays until the ramp begins are source voltage independent and range from 250 µs to 5 ms. A power good condition is output to indicate that the ramp-up slew of the source voltage is finished. Additionally, an internal discharge circuit provides a controlled path to remove charge from open power rails. The SLG55021 gate drive is packaged in an 8 pin DFN package. When used with external N-Channel FETs, the SLG55021 supports low transient, energy efficient switching of high current loads at source voltages ranging from 1.0 V to 20 V. Ordering Information Part Number Ramp Slew Rate (Volts/ms) Delay Time (ms) Discharge Resistor (ohms) SLG55021-200010V 2.0 0.15 200 TDFN-8 SLG55021-200010VTR 2.0 0.15 200 TDFN-8 - Tape and Reel (3k units) Datasheet CFR0011-120-01 Revision 1.05 Page 2 of 8 Package Type 9-Feb-2022 ©2022 Renesas Electronics Corporation  SLG55021-200010 High Voltage Gate Driver Absolute Maximum Ratings Parameter Min. Max. Unit VD or VS to GND -0.3 40.0 V Voltage at Logic Input pins -0.3 6.5 V Current at input pin -1.0 1.0 mA Storage temperature range -65 150 °C Operating temperature range -55 125 °C Junction temperature -- 150 °C ESD Human Body Model -- 2000 V ESD Machine Model -- 200 V Moisture Sensitivity Level 1 Electrical Characteristics TA = -10 °C to 75 °C Parameter VCC Iq Description Conditions Supply Voltage Quiescent Current 5.25 V --