SLG59H1127V

 SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output General Description Pin Configuration RSET NC ON Designed to operate over a -40 °C to 85 °C range, the SLG59H1127V is available in a low thermal resistance, RoHS-compliant, 1.6 x 3.0 mm STQFN package. Features • Wide Operating Input Voltage: 4.5 V to 13.2 V • Maximum Continuous Current: 4 A • Automatic nFET SOA Protection • 5 W SOA Protection Threshold • High-performance MOSFET Switch Low RDSON: 15 mΩ at VIN = 12 V Low ΔRDSON/ΔVIN: < 0.05 mΩ/V Low ΔRDSON/ΔT: < 0.06 mΩ/°C • Capacitor-adjustable Inrush Current Control • Two stage Current Limit Protection: Resistor-adjustable Active Current Limit Internal Short-circuit Current limit • Open-drain Power Good (PG) Signaling • Open-drain FAULT Signaling • Fast 4 kΩ Output Discharge • Pb-Free / Halogen-Free / RoHS Compliant Packaging 1 18 SEL 2 GND 3 VIN 4 VIN 5 VIN 6 VIN 7 17 SLG59H1127V The SLG59H1127V is a high-performance, self-powered 15 mΩ nFET load switch designed for all 4.5 V to 12 V power rails up to 4 A. Using a proprietary MOSFET design, the SLG59H1127V achieves a stable 15 mΩ RDSON across a wide input voltage range. In combining novel FET design and copper pillar interconnects, the SLG59H1127V package also exhibits a low thermal resistance for high-current operation. 8 16 CAP 15 FAULT 14 PG 9 VIN 13 VOUT 12 VOUT 11 VOUT 10 VOUT VOUT 18-pin STQFN 1.6 x 3.0 mm, 0.40mm pitch (Top View) Applications • Enterprise Computing & Telecom Equipment 5 V and 12 V Point-of-Load Power Distribution • PCI/PCIe Adapter Cards • General-purpose High-voltage, Power-Rail Switching • Multifunction Printers • Fan Motor Control Block Diagram CLOAD 22 µF 12 V ±10% 3A VIN VOUT CIN = C1 + C2 C1 1 to 22 µF Charge Pump C2 0.1 µF Linear Ramp Control CAP CSLEW 10 nF VLOGIC RSET RSET 30.1 kΩ 100 kΩ SEL ON ON VIN OVLO 14.4V State Machine (CL/SC Detection and Over Temperature Protection) CMOS Input 100 kΩ FAULT PG Connect to System GPI Discharge OFF GND Datasheet CFR0011-120-01 Revision 1.03 Page 1 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Pin Description Pin # Pin Name Type 1 ON Input 2 SEL Input 3 GND GND 4-8 VIN MOSFET 9-13 VOUT MOSFET 14 PG Output 15 FAULT Output 16 CAP Output 17 NC NC 18 RSET Input Pin Description A low-to-high transition on this pin initiates the operation of the SLG59H1127V’s state machine. ON is an asserted HIGH, level-sensitive CMOS input with ON_VIL < 0.3 V and ON_VIH > 0.9 V. As the ON pin input circuit does not have an internal pull-down resistor, connect this pin to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller – do not allow this pin to be open-circuited. Connect this pin to GND. Pin 3 is the main ground connection for the SLG59H1127V’s internal charge pump, its gate driver and current-limit circuits as well as its internal state machine. Therefore, use a short, stout connection from Pin 3 to the system’s analog or power plane. VIN supplies the power for the operation of the SLG59H1127V, its internal control circuitry, and the drain terminal of the nFET load switch. With 5 pins fused together at VIN, connect a 22 µF (or larger) low-ESR capacitor from this pin to ground. Capacitors used at VIN should be rated at 20 V or higher. Source terminal of n-channel MOSFET (5 pins fused for VOUT). Connect a 22 µF (or larger) low-ESR capacitor from this pin to ground. Capacitors used at VOUT should be rated at 20 V or higher. An open-drain output, PG is asserted within TPGHIGH when VOUT is higher than the SLG59H1127V’s PGTRIGGER threshold. PG output becomes deasserted within TPGLOW when VOUT is less than the PGHYS threshold. PG is not defined for VIN < 4 V. An open-drain output, FAULT is asserted within TFAULTLOW when a VIN overvoltage, a current-limit, or an over-temperature condition is detected. FAULT is deasserted within TFAULTHIGH when the fault condition is removed. Connect an 100 kΩ external resistor from the FAULT pin to local system logic supply. A low-ESR, stable dielectric, ceramic surface-mount capacitor connected from CAP pin to GND sets the VOUT slew rate and overall turn-on time of the SLG59H1127V. For best performance, the range for CSLEW values are 10 nF ≤ CSLEW ≤ 20 nF – please see typical characteristics for additional information. Capacitors used at the CAP pin should be rated at 10 V or higher. Please consult Applications Section on how to select CSLEW based on VOUT slew rate and loading conditions. No Connect A 1%-tolerance, metal-film resistor between 18 kΩ and 91 kΩ sets the SLG59H1127V’s active current limit. A 91 kΩ resistor sets the SLG59H1127V’s active current limit to 1 A and a 18 kΩ resistor sets the active current limit to 5 A. Ordering Information Part Number Type Production Flow SLG59H1127V STQFN 18L FC Industrial, -40 °C to 85 °C SLG59H1127VTR STQFN 18L FC (Tape and Reel) Industrial, -40 °C to 85 °C Datasheet CFR0011-120-01 Revision 1.03 Page 2 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Absolute Maximum Ratings Parameter Description VIN to GND Load Switch Input Voltage to GND Conditions Min. Typ. Max. Unit Continuous -0.3 -- 16 V -- -- 18 V Load Switch Output Voltage to VOUT to GND GND -0.3 -- VIN V ON, SEL, CAP, ON, SEL, CAP, RSET, PG, and RSET, PG, and FAULT Pin Voltages to GND FAULT to GND -0.3 -- 7 V -65 -- 150 °C TS Maximum pulsed VIN, pulse width < 0.1 s Storage Temperature ESDHBM ESD Protection Human Body Model 2000 -- -- V ESDCDM ESD Protection Charged Device Model 500 -- -- V MSL θJA Moisture Sensitivity Level Thermal Resistance; 1.6 x 3.0 mm 18L STQFN 1 Determined using 1 in2, 1 oz. copper pads under each VIN and VOUT terminal and FR4 pcb material. -- 40 -- °C/W Determined using 0.25 in2, 1 oz. copper pads under each VIN and VOUT terminal and FR4 pcb material. -- 77 -- °C/W Determined using 0.008 in2, 1 oz. copper pads under each VIN and VOUT terminal and FR4 pcb material. -- 125 -- °C/W MOSFET IDSCONT Continuous Current from VIN to VOUT TJ < 150 °C -- -- 4 A MOSFET IDSPEAK Peak Current from VIN to VOUT Maximum pulsed switch current, pulse width < 1 ms -- -- 6 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics 4.5 V ≤ VIN ≤ 13.2 V; CIN = 22 µF, TA = -40 °C to 85 °C, unless otherwise noted. Typical values are at TA = 25 °C Parameter VIN VIN(OVLO) Description Min. Typ. Max. Unit Operating Input Voltage Conditions 4.5 -- 13.2 V VIN Overvoltage Lockout Threshold VIN ↑; SEL= 0 13.5 14.4 15.2 V -- 2 -- % 2.4 -- 3.8 V VIN(OVLOHYST) VIN Overvoltage Lockout Hysteresis VIN(UVLO) VIN Undervoltage Lockout Threshold VIN ↓ IQ Quiescent Supply Current ON = HIGH; IDS = 0 A -- 0.5 0.6 mA ISHDN OFF Mode Supply Current ON = LOW; IDS = 0 A -- 1 3 µA TA = 25°C; IDS = 0.1 A -- 15 18 mΩ TA = 85°C; IDS = 0.1 A -- 22 24 mΩ Continuous -- -- 4 A RDSON MOSFET IDS Datasheet CFR0011-120-01 ON Resistance Current from VIN to VOUT Revision 1.03 Page 3 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Electrical Characteristics (continued) 4.5 V ≤ VIN ≤ 13.2 V; CIN = 22 µF, TA = -40 °C to 85 °C, unless otherwise noted. Typical values are at TA = 25 °C Parameter ILIMIT TACL RDISCHRG CLOAD TON_Delay Description Conditions Min. Typ. Max. Unit Active Current Limit, IACL VOUT > 0.5 V; RSET = 30.1 kΩ 2.8 3.2 3.6 A Short-circuit Current Limit, ISCL VOUT < 0.5 V -- 0.5 -- A -- 120 -- µs 3.5 4.4 5.3 kΩ CLOAD connected from VOUT to GND -- 22 -- µF 50% ON to 10% VOUT ↑; VIN = 4.5 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF -- 0.4 0.5 ms 50% ON to 10% VOUT ↑; VIN = 12 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10µF -- 0.7 0.9 ms Active Current Limit Response Time Output Discharge Resistance Output Load Capacitance ON Delay Time 50% ON to 90% VOUT ↑ TTotal_ON Total Turn ON Time Set by External CSLEW1 ms 50% ON to 90% VOUT ↑; VIN = 4.5 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF -- 1.6 2.1 ms 50% ON to 90% VOUT ↑; VIN = 12 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF -- 4 6 ms 10% VOUT to 90% VOUT ↑ 10% VOUT to 90% VOUT ↑; VIN = 4.5 V to 12 V; CSLEW = 10 nF; RLOAD = 100 Ω, CLOAD = 10 µF VOUT(SR) VOUT Slew rate TOFF_Delay OFF Delay Time 50% ON to VOUT Fall Start ↓; VIN = 4.5 V to 12 V; RLOAD = 100 Ω, No CLOAD TFALL VOUT Fall Time 90% VOUT ↓ to 10% VOUT ↓ VIN = 4.5 V to 12 V; RLOAD = 100 Ω, No CLOAD FAULT Assertion Time Set by External CSLEW1 V/ms 2.7 3.2 3.9 V/ms -- 15 -- µs 10.4 12.7 25 µs Abnormal Step Load Current event to Fault↓ IACL = 1 A; VIN = 12 V; RSET = 91 kΩ; switch in 10 Ω load; -- 80 -- µs FAULT De-assertion Time Delay to FAULT↑ after fault condition is removed; IACL = 1 A; VIN = 12 V; RSET = 91 kΩ; switch out 10 Ω load -- 180 -- µs FAULTVOL FAULT Output Low Voltage IFAULT = 1 mA -- 0.2 -- V VPG(OL) PG Pin Output Low Voltage VLOGIC = 5 V, IPG(OL) = -0.1 mA -- -- 0.4 V VPG(OH) PG Pin Output High Voltage VLOGIC = 5 V, IPG(OH) = 0.1 mA VLOGIC - 0.4 -- VLOGIC V Power Good Threshold Voltage Level VOUT % of VIN 86 90 94 % TFAULTLOW TFAULTHIGH PGTRIGGER Datasheet CFR0011-120-01 Revision 1.03 Page 4 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Electrical Characteristics (continued) 4.5 V ≤ VIN ≤ 13.2 V; CIN = 22 µF, TA = -40 °C to 85 °C, unless otherwise noted. Typical values are at TA = 25 °C Parameter Description Conditions Min. Typ. Max. Unit Power Good Hysteresis ↓ VOUT ↓ % of VIN 81 85 89 % TPGHIGH PG Assertion Time Delay to PG↑ after PGTRIGGER threshold is crossed. 1 1.25 1.5 ms TPGLOW PG De-assertion Time Delay to PG↓ after PGTRIGGER threshold is crossed. -- 7 -- µs ON_VIH ON Pin Input High Voltage 0.9 -- 5 V ON_VIL ON Pin Input Low Voltage -0.3 0 0.3 V ION(Leakage) ON Pin Leakage Current -- -- 1 µA THERMON Thermal Protection Shutdown Threshold -- 125 -- °C THERMOFF Thermal Protection Restart Threshold -- 100 -- °C PGHYS 1 V ≤ ON ≤ 5 V or ON = GND Notes: 1. Refer to typical Timing Parameter vs. CSLEW performance charts for additional information when available. Datasheet CFR0011-120-01 Revision 1.03 Page 5 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output TTotal_ON, TON_Delay and Slew Rate Measurement Timing Details ON* 50% ON 50% ON TOFF_Delay 90% VOUT 90% VOUT TON_Delay VOUT 10% VOUT VOUT(SR) (V/ms) 10% VOUT TFALL TTotal_ON * Rise and Fall times of the ON signal are 100 ns PG Timing Details VIN = 12 V VIN ON = 0.9 V ON VOUT 90% VIN = ~11 V 10 µs PG = 5 V PG Datasheet CFR0011-120-01 1.25 ms Revision 1.03 Page 6 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Typical Performance Characteristics RDSON vs. Temperature and VIN IACL vs. Temperature, RSET, and VIN Datasheet CFR0011-120-01 Revision 1.03 Page 7 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output IACL vs. RSET, and VIN VOUT Slew Rate vs. Temperature, VIN, and CSLEW Datasheet CFR0011-120-01 Revision 1.03 Page 8 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output TTotal_ON vs. CSLEW, VIN, and Temperature Datasheet CFR0011-120-01 Revision 1.03 Page 9 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Case Measurement Case Temperature vs. Ambient Temperature (each VIN and VOUT square is 0.008 in2, no airflow) Case Temperature vs. Ambient Temperature (each VIN and VOUT square is 0.25 in2, no airflow) Datasheet CFR0011-120-01 Revision 1.03 Page 10 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Timing Diagram - Basic Operation including Active Current Limit Protection HIGH VIN LOW Time ON TRISE HIGH VOUT 90% TON_Delay 10% IACL Abnormal Step Load Current Event IACL Active Current Limit Operation IDS ISCL ISCL FAULT TFAULTLOW TFAULTHIGH Nominal Steady State Operation Resumes ACL Threshold Triggered Datasheet CFR0011-120-01 Revision 1.03 Page 11 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Timing Diagram - Active Current Limit & Thermal Protection Operation HIGH VIN LOW Time Nominal Steady State Operation Resumes ON TTotal_ON Active Current Limit Operation TRISE VOUT Thermal Protection Operation 90% TON_Delay 10% Abnormal Step Load Current Event IACL IACL IDS ISCL ISCL FAULT TFAULTLOW TFAULTHIGH Die temp > THERMON Datasheet CFR0011-120-01 Revision 1.03 Page 12 of 32 Die temp < THERMOFF 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Timing Diagram - Basic Operation including Active Current + Internal FET SOA Protection HIGH VIN LOW Time ON ACL Threshold Triggered Decreasing RLOAD drops VOUT TRISE HIGH VOUT 90% TON_Delay SOA Threshold 10% IACL Abnormal Step Load Current Event Active Current Limit Operation IACL SOA Protection IDS ISCL ISCL 0.2s FAULT TFAULTLOW ACL Threshold Triggered TFAULTHIGH Nominal Steady State Operation resumes once overload condition is removed FET SOA Threshold Triggered and FET is turned off Datasheet CFR0011-120-01 Revision 1.03 Page 13 of 32 Automatic restart after 0.2s “cool off” delay and normal operation resumes if overload condition is removed 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output SLG59H1127V Application Diagram Figure 1. Test setup Application Diagram Typical Turn-on Waveforms Figure 2. Typical Turn ON operation waveform for VIN = 4.5 V, CSLEW = 10 nF, CLOAD = 10 μF, RLOAD = 100 Ω Datasheet CFR0011-120-01 Revision 1.03 Page 14 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Figure 3. Typical Turn ON operation waveform for VIN = 4.5 V, CSLEW = 18 nF, CLOAD = 10 μF, RLOAD = 100 Ω Figure 4. Typical Turn ON operation waveform for VIN = 12 V, CSLEW = 10 nF, CLOAD = 10 μF, RLOAD = 100 Ω Datasheet CFR0011-120-01 Revision 1.03 Page 15 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Figure 5. Typical Turn ON operation waveform for VIN = 12 V, CSLEW = 18 nF, CLOAD = 10 μF, RLOAD = 100 Ω Typical Turn-off Waveforms Figure 6. Typical Turn OFF operation waveform for VIN = 4.5 V, CSLEW = 10 nF, no CLOAD , RLOAD = 100 Ω Datasheet CFR0011-120-01 Revision 1.03 Page 16 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Figure 7. Typical Turn OFF operation waveform for VIN = 4.5 V, CSLEW = 10 nF, CLOAD = 10 μF, RLOAD = 100 Ω Figure 8. Typical Turn OFF operation waveform for VIN = 12 V, CSLEW = 10 nF, no CLOAD , RLOAD = 100 Ω Datasheet CFR0011-120-01 Revision 1.03 Page 17 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Figure 9. Typical Turn OFF operation waveform for VIN = 12 V, CSLEW = 10 nF, CLOAD = 10 μF, RLOAD = 100 Ω Typical ACL Operation Waveforms Figure 10. Typical ACL operation waveform for VIN = 4.5 V, CLOAD = 10 μF, IACL = 1 A, RSET = 95.3 kΩ Datasheet CFR0011-120-01 Revision 1.03 Page 18 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Figure 11. Typical ACL operation waveform for VIN = 12 V, CLOAD = 10 μF, IACL = 1 A, RSET = 95.3 kΩ Typical FAULT Operation Waveforms Figure 12. Typical FAULT assertion waveform for VIN = 4.5 V, CLOAD = 10 μF, IACL = 1 A, RSET = 95.3 kΩ, switch on 3.3 Ω load Datasheet CFR0011-120-01 Revision 1.03 Page 19 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Figure 13. Typical FAULT de-assertion waveform for VIN = 4.5 V, CLOAD = 10 μF, IACL = 1 A, RSET = 95.3 kΩ, switch out 3.3 Ω load Figure 14. Typical FAULT assertion waveform for VIN = 12 V, CLOAD = 10 μF, IACL = 1 A, RSET = 95.3 kΩ, switch on 10 Ω load Datasheet CFR0011-120-01 Revision 1.03 Page 20 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Figure 15. Typical FAULT de-assertion waveform for VIN = 12 V, CLOAD = 10 μF, IACL = 1 A, RSET = 95.3 kΩ, switch out 10 Ω load Typical Power Good Waveform Figure 16. Typical Power Good operation waveform for VIN = 12 V, CLOAD = 10 μF, no RLOAD Datasheet CFR0011-120-01 Revision 1.03 Page 21 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Typical SOA Waveforms Figure 17. Typical SOA waveform during power up under heavy load for VIN = 12 V, CLOAD = 10 μF, RSET = 30.1 kΩ, RLOAD = 5 Ω Figure 18. Extended typical SOA waveform during power up under heavy load for VIN = 12 V, CLOAD = 10 μF, RSET = 30.1 kΩ, RLOAD = 5 Ω Datasheet CFR0011-120-01 Revision 1.03 Page 22 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Applications Information High Voltage GreenFET Safe Operating Area Explained Renesas’s High Voltage GreenFET load switches incorporate a number of internal protection features that prevents them from damaging themselves or any other circuit or subcircuit downstream of them. One particular protection feature is their Safe Operation Area (SOA) protection. SOA protection is automatically activated under overpower and, in some cases, under overcurrent conditions. Overpower SOA is activated if package power dissipation exceeds an internal 5 W threshold longer than 2.5 ms. High Voltage GreenFET devices will quickly switch off (open circuit) upon overpower detection and automatically resume (close) nominal operation once overpower condition no longer exists. One of the possible ways to have an overpower condition trigger SOA protection is when High Voltage GreenFET products are enabled into heavy output resistive loads and/or into large load capacitors. It is under these conditions to follow carefully the “Safe Start-up Loading” guidance in the Applications section of the datasheet. During an overcurrent condition, High Voltage GreenFET devices will try to limit the output current to the level set by the external RSET resistor. Limiting the output current, however, causes an increased voltage drop across the FET’s channel because the FET’s RDSON increased as well. Since the FET’s RDSON is larger, package power dissipation also increases. If the resultant increase in package power dissipation is higher/equal than 5 W for longer than 2.5 ms, internal SOA protection will be triggered and the FET will open circuit (switch off). Every time SOA protection is triggered, all High Voltage GreenFET devices will automatically attempt to resume nominal operation after 160 ms. Safe Start-up Condition SLG59H1127V has built-in protection to prevent over-heating during start-up into a heavy load. Overloading the VOUT pin with a capacitor and a resistor may result in non-monotonic VOUT ramping or repeated restarts (Figure 17 and Figure 18). In general, under light loading on VOUT, VOUT ramping can be controlled with CSLEW value. The following equation serves as a guide: CSLEW = TRISE 20 x 4.9 μA x VIN 3 where TRISE = Total rise time from 10% VOUT to 90% VOUT VIN = Input Voltage CSLEW = Capacitor value for CAP pin When capacitor and resistor loading on VOUT during start up, the following tables will ensure VOUT ramping is monotonic without triggering internal protection: Safe Start-up Loading for VIN = 12 V (Monotonic Ramp) Slew Rate (V/ms) CSLEW (nF)2 CLOAD (μF) RLOAD (Ω) 1 33.3 500 20 2 16.7 250 20 3 11.1 160 20 4 8.3 120 20 5 6.7 100 20 Note 2: Select the closest-value tolerance capacitor. Datasheet CFR0011-120-01 Revision 1.03 Page 23 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Setting the SLG59H1127V’s Active Current Limit RSET (kΩ) Active Current Limit (A)3 91 1 45 2 30 3 18 5 Note 3: Active Current Limit accuracy is ±15% over voltage range and temperature range Setting the SLG59H1127V’s Input Overvoltage Lockout Threshold As shown in the table below, SEL selects the VIN overvoltage threshold at which the SLG59H1127V’s internal state machine will turn OFF (open circuit) the power MOSFET if VIN exceeds the selected threshold. SEL VIN(OVLO) (Typ) 0 14.4 V With an activated SLG59H1127V (ON=HIGH) and at any time VIN crosses the programmed VIN overvoltage threshold, the state machine opens the load switch and asserts the FAULT pin within TFAULTLOW. In applications with a deactivated or inactive SLG59H1127V (VIN > VIN(UVLO) and ON=LOW) and if the applied VIN is higher than the programmed VIN(OVLO) threshold, the SLG59H1127V’s state machine will keep the load switch open circuited if the ON pin is toggled LOW-to-HIGH. In these cases, the FAULT pin will also be asserted within TFAULTLOW and will remain asserted until VIN resumes nominal, steady-state operation. In all cases, the SLG59H1127V’s VIN undervoltage lockout threshold is fixed at VIN(UVLO). Power Dissipation The junction temperature of the SLG59H1127V depends on different factors such as board layout, ambient temperature, and other environmental factors. The primary contributor to the increase in the junction temperature of the SLG59H1127V is the power dissipation of its power MOSFET. Its power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations: PD = RDSON x IDS2 where: PD = Power dissipation, in Watts (W) RDSON = Power MOSFET ON resistance, in Ohms (Ω) IDS = MOSFET current, in Amps (A) and TJ = PD x θJA + TA where: TJ = Junction temperature, in Celsius degrees (°C) θJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) TA = Ambient temperature, in Celsius degrees (°C) Datasheet CFR0011-120-01 Revision 1.03 Page 24 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Power Dissipation (continued) In current-limit mode, the SLG59H1127V’s power dissipation can be calculated by taking into account the voltage drop across the load switch (VIN - VOUT) and the magnitude of the output current in current-limit mode (IACL): PD = (VIN-VOUT) x IACL or PD = (VIN – (RLOAD x IACL)) x IACL where: PD = Power dissipation, in Watts (W) VIN = Input Voltage, in Volts (V) RLOAD = Load Resistance, in Ohms (Ω) IACL = Output limited current, in Amps (A) VOUT = RLOAD x IACL Datasheet CFR0011-120-01 Revision 1.03 Page 25 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Layout Guidelines: 1. Since the VIN and VOUT pins dissipate most of the heat generated during high-load current operation, it is highly recommended to make power traces as short, direct, and wide as possible. A good practice is to make power traces with absolute minimum widths of 15 mils (0.381 mm) per Ampere. A representative layout, shown in Figure 19, illustrates proper techniques for heat to transfer as efficiently as possible out of the device; 2. To minimize the effects of parasitic trace inductance on normal operation, it is recommended to connect input CIN and output CLOAD low-ESR capacitors as close as possible to the SLG59H1127V's VIN and VOUT pins; 3. The GND pin should be connected to system analog or power ground plane. 4. 2 oz. copper is recommended for high current operation. SLG59H1127V Evaluation Board: А High Voltage GreenFET Evaluation Board for SLG59H1127V is designed according to the statements above and is illustrated on Figure 19. Please note that evaluation board has D_Sense and S_Sense pads. They cannot carry high currents and dedicated only for RDSON evaluation. Figure 19. SLG59H1127V Evaluation Board Datasheet CFR0011-120-01 Revision 1.03 Page 26 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V GND 1 1 VLOGIC 1 IOUT/POUT R7 100k PDS/CAP FAULT# 1 GND 1 GND 1 1 2 3 SEL1 1 2 3 ON R6 5V1 SEL0 1 2 3 A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output R5 10k R3 30.1k VLOGIC circuit C4 10nF R4 N.P. R2 100k R1 N.P. C3 N.P. U1 D_SENSE 18 17 16 15 14 13 12 11 10 9 CAP Array DRAIN SOURCE 1 3 5 7 9 2 4 6 8 10 1 C2 22uF 1 ON SEL GND VIN VIN VIN VIN VIN RSET NC CAP FAULT PG VOUT VOUT VOUT VOUT VOUT 1 1 C1 22u F 1 2 3 4 5 6 7 8 S_SENSE 1 2 3 4 1 2 3 4 GND D/VIN GND 1 2 3 4 1 2 3 4 RSET Array S/VOUT 1 3 5 7 9 2 4 6 8 10 Figure 20. SLG59H1127V Evaluation Board Connection Circuit Basic Test Setup and Connections Figure 21. SLG59H1127V Evaluation Board Connection Circuit EVB Configuration 1. Set SEL0 to GND to configure OVLO; 2. Connect oscilloscope probes to D/VIN, S/VOUT, ON, etc.; 3. Turn on Power Supply and set desired VIN from 4.5 V…12 V range; 4. Toggle the ON signal High or Low to observe SLG59H1127V operation. 5. Use central SEL1 header pin for PG monitor. Datasheet CFR0011-120-01 Revision 1.03 Page 27 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Package Top Marking System Definition Pin 1 Identifier 1127V WWNNN ARR Part Code Date Code + LOT Code Assembly + Rev. Code 1127V - Part ID Field WW - Date Code Field1 NNN - Lot Traceability Code Field1 A - Assembly Site Code Field 2 RR - Part Revision Code Field2 Note 1: Each character in code field can be alphanumeric A-Z and 0-9 Note 2: Character in code field can be alphabetic A-Z Datasheet CFR0011-120-01 Revision 1.03 Page 28 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Package Drawing and Dimensions 18 Lead TQFN Package 1.6 x 3 mm (Fused Lead) JEDEC MO-220, Variation WCEE Datasheet CFR0011-120-01 Revision 1.03 Page 29 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output SLG59H1127V 18-pin STQFN PCB Landing Pattern Note: All dimensions shown in micrometers (µm) Datasheet CFR0011-120-01 Revision 1.03 Page 30 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Tape and Reel Specifications Max Units Leader (min) Nominal Reel & Package # of Package Size Hub Size Length Type Pins per Reel per Box Pockets [mm] [mm] [mm] STQFN 18L 0.4P FC Green 18 1.6 x 3 x 0.55 3,000 3,000 178 / 60 100 400 Trailer (min) Pockets Length [mm] Tape Width [mm] 100 400 8 Part Pitch [mm] 4 Carrier Tape Drawing and Dimensionss Package Type Pocket BTM Pocket BTM Length Width STQFN 18L 0.4P FC Green Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole Index Hole to Tape to Pocket Tape Width Edge Center A0 B0 K0 P0 P1 D0 E F W 1.78 3.18 0.76 4 4 1.5 1.75 3.5 8 Refer to EIA-481 specification Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.64 mm3 (nominal). More information can be found at www.jedec.org. Datasheet CFR0011-120-01 Revision 1.03 Page 31 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59H1127V A 12 V, 15 mΩ, 4 A Load Switch with VIN Lockout Select and Power Good Output Revision History Date Version Change 2/2/2022 1.03 Updated Company name and logo Added SOA Protection Threshold to Features Fixed typos Updated EVB image 12/12/2018 1.02 Updated style and formatting Updated Charts and Scopeshots Fixed typos 1/16/2018 1.01 Updated RDSON vs VIN and Temp Chart 2/24/2017 1.00 Production Release Datasheet CFR0011-120-01 Revision 1.03 Page 32 of 32 2-Feb-2022 ©2022 Renesas Electronics Corporation IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2021 Renesas Electronics Corporation. All rights reserved.