SLG59M1440V

 SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge General Description Pin Configuration ON 1 The product is packaged in an ultra-small 1.0 x 1.0 mm package. D 2 Features • • • • • • • One 40 mΩ, 1 A MOSFET One integrated VGS Charge Pump User selectable ramp rate with external resistor Integrated Discharge Resistor Over Temperature Protection Pb-Free / Halogen-Free / RoHS compliant STDFN 4L, 1.0 x 1.0 x 0.55 mm SLG59M1440V The SLG59M1440V is designed for load switching applications. The part comes with one 40 mΩ, 1 A rated MOSFET controlled by a single ON control pin. The MOSFET’s ramp rate is adjustable depending on the input current level of the ON pin. 4 GND 3 S 4-pin STDFN (Top View) Block Diagram 1.0 A S D CIN CLOAD Charge Pump Out Current Detect Slew Rate Control ON Datasheet CFR0011-120-01 CMOS Input Revision 1.14 Page 1 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Pin Description Pin # Pin Name Type Pin Description A low-to-high transition on this pin closes the load switch. ON is an asserted-HIGH, level-sensitive CMOS input with ON_VIL < 0.3 V and ON_VIH_INI > 1.2 V. Connect this pin to the output of a general-purpose output (GPO) from a microcontroller or other application processor. A resistor connected in series to ON signal sets the VS Slew Rate. Please read more information on Adjustable Slew Rate description. 1 ON Input 2 D MOSFET Drain/Input terminal of Power MOSFET. Connect a 10 μF (or larger) low ESR capacitor from this pin to GND. Capacitors used at D should be rated at 10 V or higher. 3 S MOSFET Source/Output terminal of Power MOSFET. Connect a 10 μF (or larger) low ESR capacitor from this pin to GND. Capacitors used at S should be rated at 10 V or higher. 4 GND GND Ground connection. Connect this pin to system analog or power ground plane. Ordering Information Part Number Type Production Flow SLG59M1440V STDFN 4L Industrial, -40 °C to 85 °C SLG59M1440VTR STDFN 4L (Tape and Reel) Industrial, -40 °C to 85 °C Application Diagram Current Controls Ramp Rate ON 3.3 V R1 SLG59M1440V Control IC GND VOUT VIN Adjustable Ramp Rate vs. ON Pin Current (5.5 V, 25 °C) ON Pin Current VS(SR) (typ) 20 µA 0.56 V/ms 50 µA 1.34 V/ms 100 µA 2.53 V/ms 150 µA 3.71 V/ms 200 µA 4.68 V/ms 250 µA 5.63 V/ms Adjustable Slew Rate (ON Pin 1) SLG59M1440V has a built in configurable slew control feature. The configurable slew control uses current detection method on Pin 1. When ON voltage rises above ON_VIH_INI (1.2 V typical), the slew control circuit will measure the current flowing into Pin 1. Based on the current flowing into pin 1, different slew rates will be selected by the internal control circuit. See ON Pin Curent vs. VS(SR) table. The slew rate is configurable by selecting a different R1 resistor value as shown on application diagram. Calculating the R1 value depends on both the desired slew rate, and the GPIO_VOH level of the device driving the ON Pin 1. ON Pin Current = (GPIO_VOH – ON_VREF (1.05 V typical)) / R1 Datasheet CFR0011-120-01 Revision 1.14 Page 2 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Absolute Maximum Ratings Parameter Description Conditions VD Load Switch Input Voltage TS Storage Temperature ESDHBM ESD Protection MSL Moisture Sensitivity Level WDIS Package Power Dissipation MOSFET IDSPK Human Body Model Min. Typ. Max. Unit -- -- 6 V -65 -- 150 °C 2000 -- -- V -- -- 0.5 W -- -- 1.5 A 1 Peak Current from Drain to Source For no more than 1 ms with 1% duty cycle Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics TA = -40 °C to 85 °C unless otherwise noted. Typical values are at TA = 25 °C. Parameter Description Conditions VD Load Switch Input Voltage -40 °C to 85 °C ID Load Switch Current (PIN 2) RDSON ON Resistance MOSFET IDS Current from D to S TON_Delay ON Delay Time Min. Typ. Max. Unit 2.5 -- 5.5 V when OFF -- 0.1 1 μA when ON, No load -- 18 30 μA TA = 25 °C; IDS = 100 mA -- 40 50 mΩ TA = 70 °C; IDS = 100 mA -- 50 55 mΩ TA = 85 °C; IDS = 100 mA -- 55 65 mΩ Continuous -- -- 1.0 A 50% ON to VS Ramp Start; ON Pin Current (PIN1) = 20 μA; VD = 5 V; CLOAD = 10 μF; RLOAD = 20 Ω -- 2.4 4.0 ms 50% ON to 90% VS TTotal_ON Total Turn On Time Example: ON Pin Current (PIN1) = 20 μA; VD = 5 V; CLOAD = 10 μF; RLOAD = 20 Ω 10% VS to 90% VS VS(SR) RDISCHRG CLOAD ON_VREF Example: ON Pin Current (PIN1) = 20 μA; VD = 5 V; CLOAD = 10 μF; RLOAD = 20 Ω VS Slew Rate Discharge Resistance VD = 2.5 V to 5.5 V; VS = 0.4 V Input bias Output Load Capacitance CLOAD connected from S to GND ON Pin Reference Voltage2 Set by External Resistor1 -- 11.7 -- Set by External Resistor1 ms ms V/ms -- 0.56 -- V/ms 100 150 300 Ω -- -- 100 μF 0.99 1.05 1.10 V Internal Charge Pump ON 1.2 -- VD V Internal Charge Pump OFF -0.3 0 0.3 V 100 -- -- MΩ Thermal shutoff turn-on temperature -- 120 -- °C THERMOFF Thermal shutoff turn-off temperature -- 100 -- °C ON_VIH_INI Initial Turn On Voltage ON_VIL Low Input Voltage on ON pin ON_R Input Impedance on ON pin THERMON Datasheet CFR0011-120-01 Revision 1.14 Page 3 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Electrical Characteristics (continued) TA = -40 °C to 85 °C unless otherwise noted. Typical values are at TA = 25 °C. Parameter Description Conditions THERMTIME Thermal shutoff time TOFF_Delay TFALL Min. Typ. Max. Unit -- -- 1 ms OFF Delay Time 50% ON to VS Fall Start; VD = 5 V; RLOAD = 20 Ω, no CLOAD -- 6.5 20 μs VS Fall Time 90% VS to 10% VS; VD = 5 V; RLOAD = 20 Ω; no CLOAD -- 1.2 2 μs Notes: 1. Refer to table for configuration details. 2. Voltage before ON pin resistor needs to be higher than 1.2 V to generate required ION TON_Delay, VS(SR), and TTotal_ON Timing Details ON* 50% ON 50% ON TOFF_Delay 90% VS VS 90% VS TON_Delay 10% VS 10% VS VS(SR) (V/ms) TFALL TTotal_ON Note: * Rise and Fall times of the ON signal are 100 ns Datasheet CFR0011-120-01 Revision 1.14 Page 4 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Typical Performance Characteristics Slew Rate vs. ON Pin Current TTotal_ON vs. ON Pin Current Datasheet CFR0011-120-01 Revision 1.14 Page 5 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge SLG59M1440V Power-Up/Power-Down Sequence Considerations A nominal power-up sequence is to apply VD and toggle the ON pin LOW-to-HIGH after VD is at least 90% of its final value. A nominal power-down sequence is the power-up sequence in reverse order. If VD ramp is too fast, a voltage glitch may appear on the output pin at S. To prevent glitches at the output, it is recommended to connect at least 0.1uF capacitor from the S pin to GND and to keep the VD ramp time higher than 2 ms. Power Dissipation Considerations The junction temperature of the SLG59M1440V depends on factors such as board layout, ambient temperature, external air flow over the package, load current, and the RDSON-generated voltage drop across the power MOSFET. While the primary contributor to the increase in the junction temperature of the SLG59M1440V is the power dissipation of its power MOSFETs, its power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations: PDTOTAL = RDSON x IDS2 where: PDTOTAL = Total package power dissipation, in Watts (W) RDSON = Power MOSFET ON resistance, in Ohms (Ω) IDS = Output current, in Amps (A) and TJ = PDTOTAL x θJA + TA where: TJ = Die junction temperature, in Celsius degrees (°C) θJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) – highly dependent on pcb layout TA = Ambient temperature, in Celsius degrees (°C) In nominal operating mode, the SLG59M1440V’s power dissipation can also be calculated by taking into account the voltage drop across the switch (VD - VS) and the magnitude of the switch’s output current (IDS): PDTOTAL = (VD - VS) x IDS or PDTOTAL = (VD – (RLOAD x IDS)) x IDS where: PDTOTAL = Total package power dissipation, in Watts (W) VD = Switch input Voltage, in Volts (V) RLOAD = Output Load Resistance, in Ohms (Ω) IDS = Switch output current, in Amps (A) VS = Switch output voltage, or RLOAD x IDS Datasheet CFR0011-120-01 Revision 1.14 Page 6 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Layout Guidelines: 1. Since the D and S pins dissipate most of the heat generated during high-load current operation, it is highly recommended to make power traces as short, direct, and wide as possible. A good practice is to make power traces with an absolute minimum width of 15 mils (0.381 mm) per Ampere. A representative layout, shown in Figure 1, illustrates proper techniques for heat to transfer as efficiently as possible out of the device; 2.To minimize the effects of parasitic trace inductance on normal operation, it is recommended to connect input CIN and output CLOAD low-ESR capacitors as close as possible to the SLG59M1440V's D and S pins; 4. The GND pin should be connected to system analog or power ground plane. 4. 2 oz. copper is recommended for high current operation. SLG59M1440V Evaluation Board: А GreenFET Evaluation Board for SLG59M1440V is designed according to the statements above and is illustrated on Figure 1. Please note that evaluation board has D_Sense and S_Sense pads. They cannot carry high currents and dedicated only for RDSON evaluation. Please solder your SLG59M1440V here Figure 1. SLG59M1440V Evaluation Board. Datasheet CFR0011-120-01 Revision 1.14 Page 7 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge 1 1 VDD C2 1 2 3 4 5 VDD CAP2 GND CAP1 ON1 S2 ON2 S1 D1 D2 C1 10 9 8 7 6 CAP/RILIM ON D_Sense1 1 1 2 3 1 2 3 4 U1 VDD ON D D C3 C4 R_Array 1 3 5 7 9 8 7 6 5 GND PG S S 1 3 5 7 9 S_Sense1 1 C5 R1 C6 2 4 6 8 10 R2 R3 R4 C7 100n 2 4 6 8 10 9 1 2 3 4 D_Sense2 1 U2 ON VDD D D D 8 7 6 5 GND CAP S S S_Sense2 1 C8 100n 1 2 3 4 D_Sense3 1 U3 ON VDD D D 8 7 6 5 GND CAP S S S_Sense3 1 C9 100n 9 1 2 3 4 D_Sense4 1 1 2 3 4 D_Sense5 1 1 2 U4 ON VDD D D D 8 7 6 5 GND S S S U5 ON VIN VIN VIN U6 ON D 8 7 6 5 GND VOUT VOUT VOUT GND S S_Sense4 1 S_Sense5 1 4 3 D_Sense6 1 D/VIN D/VIN 1 1 1 1 S_Sense6 1 S/VOUT S/VOUT Figure 2. SLG59M1440V Evaluation Board Connection Circuit. Datasheet CFR0011-120-01 Revision 1.14 Page 8 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Basic Test Setup and Connections Figure 3. Typical connections for GreenFET Evaluation. EVB Configuration 1. Connect oscilloscope probes to D/VIN, S/VOUT, ON, etc.; 2. Turn on Power Supply 1 and set desired VD from 2.5 V…5.5 V range; 3. Toggle the ON signal High or Low to observe SLG59M1440V operation. Datasheet CFR0011-120-01 Revision 1.14 Page 9 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge SLG59M1440V Layout Suggestion Note: All dimensions shown in micrometers (µm) Datasheet CFR0011-120-01 Revision 1.14 Page 10 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Package Top Marking System Definition NN Pin 1 Identifier + Serial Number Line 1 Serial Number Line 2 NN -Part Serial Number Field Line 1 where each “N” character can be A-Z and 0-9 + - Part Serial Number Field Line 2 where “+” character can be +, -, =, or blank Datasheet CFR0011-120-01 Revision 1.14 Page 11 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Package Drawing and Dimensions 4 Lead STDFN Package 1.0 x 1.0 mm Datasheet CFR0011-120-01 Revision 1.14 Page 12 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Tape and Reel Specifications Max Units Leader (min) Nominal Reel & Package # of Package Size Hub Size Length Type Pins per Reel per Box Pockets [mm] [mm] [mm] STDFN 4L Green 4 1.0 x 1.0 x 0.55 8000 8000 178 / 60 200 400 Trailer (min) Pockets Length [mm] Tape Width [mm] 200 400 8 Part Pitch [mm] 2 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Pocket BTM Length Width STDFN 4L Green Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole Index Hole to Tape to Pocket Tape Width Edge Center A0 B0 K0 P0 P1 D0 E F W 1.16 1.16 0.63 4 2 1.5 1.75 3.5 8 Refer to EIA-481 specification Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 0.55 mm3 (nominal). More information can be found at www.jedec.org. Datasheet CFR0011-120-01 Revision 1.14 Page 13 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1440V An Ultra-small 40 mΩ, 1 A, Load Switch with Discharge Revision History Date Version 2/3/2022 1.14 Updated Company name and logo Fixed typos 9/1/2020 1.13 Updated Style and Formatting Updated Charts Added Layout Guidelines 11/20/2017 1.12 Updated Package Marking Definition Updated Layout Suggestion 12/11/2013 1.11 changed temp range to -40 to 85C Datasheet CFR0011-120-01 Change Revision 1.14 Page 14 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2021 Renesas Electronics Corporation. All rights reserved.