SLG59M1448V

 SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge General Description Pin Configuration The SLG59M1448V is a 17 mΩ 2.5 A single-channel load switch that is able to switch 0.9 V to 5.5 V power rails. The product is packaged in an ultra-small 1.0 x 1.6 mm package. • 1.0 x 1.6 x 0.55 mm STDFN package (2 fused pins for drain and 2 fused pins for source) • Logic level ON pin capable of supporting 0.85 V CMOS Logic • User selectable ramp rate with external capacitor • 17 mΩ RDSON while supporting 2.5 A • Discharges load when off • Two Over Current Protection Modes • Short Circuit Current Limit • Active Current Limit • Over Temperature Protection • Pb-Free / Halogen-Free / RoHS compliant • Operating Temperature: -40 °C to 85 °C • Operating Voltage: 2.5 V to 5.5 V Industrial VDD 1 ON 2 D 3 D 4 SLG59M1448V Features 8 GND 7 CAP 6 S 5 S 8-pin STDFN (Top View) Applications • Notebook Power Rail Switching • Tablet Power Rail Switching • Smartphone Power Rail Switching Block Diagram 2.5 A @ 17 mΩ D CIN VDD +2.5 to 5.5 V CAP S CLOAD Charge Pump Linear Ramp Control CSLEW 4 nF Over Current and Over Temperature Protection ON Datasheet CFR0011-120-01 CMOS Input Revision 1.08 Page 1 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Pin Description Pin # Pin Name Type Pin Description 1 VDD PWR VDD supplies the power for the operation of the load switch and internal control circuitry. Bypass the VDD pin to GND with a 0.1 µF (or larger) capacitor. 2 ON Input A low-to-high transition on this pin initiates the operation of the SLG59M1448V’s state machine. ON is a CMOS input with ON_VIL < 0.3 V and ON_VIH > 0.85 V thresholds. While there is an internal pull-down circuit to GND (~4 MΩ), connect this pin directly to a general-purpose output (GPO) of a microcontroller, an application processor, or a system controller. 3, 4 D MOSFET Drain terminal connection of the n-channel MOSFET (2 pins fused for D). Connect at least a low-ESR 0.1 µF capacitor from this pin to ground. Capacitors used at D should be rated at a voltage higher than the maximum input voltage ever present. 5, 6 S MOSFET Source terminal connection of the n-channel MOSFET (2 pins fused for S). Connect a low-ESR capacitor from this pin to ground and consult the Electrical Characteristics table for recommended CLOAD range. Capacitors used at S should be rated at a voltage higher than the maximum output voltage ever present. 7 CAP Input A low-ESR, stable dielectric, ceramic surface-mount capacitor connected from CAP pin to GND sets the VS slew rate and overall turn-on time of the SLG59M1448V. For best performance CSLEW value should be ≥ 1.5 nF and voltage level should be rated at 10 V or higher. 8 GND GND Ground connection. Connect this pin to system analog or power ground plane. Ordering Information Part Number Type Production Flow SLG59M1448V STDFN 8L Industrial, -40 °C to 85 °C SLG59M1448VTR STDFN 8L (Tape and Reel) Industrial, -40 °C to 85 °C Datasheet CFR0011-120-01 Revision 1.08 Page 2 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Absolute Maximum Ratings Parameter VDD TS ESDHBM Description Conditions Min. Typ. Max. Unit -- -- 7 V -65 -- 150 °C 8000 -- -- V Power Supply Storage Temperature ESD Protection MSL Moisture Sensitivity Level WDIS Package Power Dissipation Human Body Model 1 MOSFET IDSPK Peak Current from Drain to Source For no more than 1 ms with 1% duty cycle -- -- 0.4 W -- -- 3.5 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics TA = -40 °C to 85 °C (unless otherwise stated) Parameter Description Conditions VDD Power Supply Voltage -40 °C to 85 °C IDD Power Supply Current (PIN 1) RDSON ON Resistance MOSFET IDS Operating Current VD TON_Delay Total Turn On Time Max. Unit 2.5 -- 5.5 V -- -- 1 µA when ON, No CLOAD -- 70 100 µA TA = 25 °C; IDS = 100 mA -- 17 19 mΩ TA = 70 °C; IDS = 100 mA -- 18.5 20 mΩ TA = 85 °C; IDS = 100 mA -- 22 24 mΩ VD = 1.0 V to 5.5 V -- -- 2.5 A 0.9 -- VDD V -- 300 500 µs 50% ON to VS Ramp Start; CLOAD = 10 μF, RLOAD = 20 Ω 50% ON to 90% VS TTotal_ON Typ. when OFF Drain Voltage ON Delay Time Min. Example: CSLEW = 4 nF, VDD = VD = 5 V, CLOAD = 10 μF, RLOAD = 20 Ω 10% VS to 90% VS VS(SR) Slew Rate Example: CSLEW = 4 nF, VDD = VD = 5 V, CLOAD = 10 μF, RLOAD = 20 Ω CLOAD Output Load Capacitance CLOAD connected from VS to GND Set by External CSLEW1 -- 1.96 -- Set by External CSLEW1 ms ms V/ms -- 3.0 -- V/ms -- -- 500 µF Discharge Resistance 100 150 300 Ω ON_VIH High Input Voltage on ON pin 0.85 -- VDD V ON_VIL Low Input Voltage on ON pin -0.3 0 0.3 V RDISCHRGE Active Current Limit MOSFET will automatically limit current when VS > 250 mV -- 3.7 -- A Short Circuit Current Limit MOSFET will automatically limit current when VS < 250 mV -- 0.9 -- A Thermal shutoff turn-on temperature -- 125 -- °C THERMOFF Thermal shutoff turn-off temperature -- 100 -- °C THERMTIME Thermal shutoff time -- -- 1 ms ILIMIT THERMON Datasheet CFR0011-120-01 Revision 1.08 Page 3 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Electrical Characteristics (continued) TA = -40 °C to 85 °C (unless otherwise stated) Parameter Description Conditions TOFF_Delay OFF Delay Time VS Fall Time TFALL Min. Typ. Max. Unit 50% ON to VS Fall Start; VDD = VD = 5 V; RLOAD = 20 Ω, no CLOAD -- 8 -- µs 90% VS to 10% VS, VDD = VD = 5 V; RLOAD = 20 Ω, no CLOAD -- 3.8 -- µs Notes: 1. Refer to typical timing parameter vs. CSLEW performance charts for additional information when available. TON_Delay, VS(SR), and TTotal_ON Timing Details ON* 50% ON 50% ON TOFF_Delay 90% VS VS 90% VS TON_Delay 10% VS 10% VS VS(SR) (V/ms) TFALL TTotal_ON Note: * Rise and Fall times of the ON signal are 100 ns Datasheet CFR0011-120-01 Revision 1.08 Page 4 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Typical Performance Characteristics TTotal_ON vs CSLEW, VD, VDD, and Temperature VS Slew Rate vs. CSLEW, VDD, and Temperature Datasheet CFR0011-120-01 Revision 1.08 Page 5 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge SLG59M1448V Power-Up/Power-Down Sequence Considerations To ensure glitch-free power-up under all conditions, apply VDD first, followed by VD after VDD exceeds 1 V. Then allow VD to reach 90% of its max value before toggling the ON pin from Low-to-High. Likewise, power-down in reverse order. If VDD and VD need to be powered up simultaneously, glitching can be minimized by having a suitable load capacitor. A 10 µF CLOAD will prevent glitches for rise times of VDD and VD higher than 2 ms. If the ON pin is toggled HIGH before VDD and VD have reached their steady-state values, the load switch timing parameters may differ from datasheet specifications. The slew rate of output VS follows a linear ramp set by a capacitor connected to the CAP pin. A larger capacitor value at the CAP pin produces a slower ramp, reducing inrush current from capacitive loads. SLG59M1448V Current Limiting Operation The SLG59M1448V has two types of current limiting triggered by the output S pin voltage. 1. Standard Current Limiting Mode (with Thermal Shutdown Protection) When the VS voltage > 250 mV, the output current is initially limited to the Active Current Limit (IACL) specification listed in the Electrical Characteristics table. The ACL monitor’s response time is very fast and is triggered within a few microseconds to sudden (transient) changes in load current. When a load current overload is detected, the ACL monitor increases the FET resistance to keep the current from exceeding the load switch’s IACL threshold. However, if a load-current overload condition persists where the die temperature rises because of the increased FET resistance, the load switch’s internal Thermal Shutdown Protection circuit can be activated. If the die temperature exceeds the listed THERMON specification, the FET is shut OFF completely, thereby allowing the die to cool. When the die cools to the listed THERMOFF temperature threshold, the FET is allowed to turn back on. This process may repeat as long as the output current overload condition persists. 2. Short Circuit Current Limiting Mode (with Thermal Shutdown Protection) When the VS voltage < 250 mV (which is the case with a hard short, such as a solder bridge on the power rail), the load switch’s internal Short-circuit Current Limit (SCL) monitor limits the FET current to approximately 900 mA (the ISCL threshold). While the internal Thermal Shutdown Protection circuit remains enabled and since the ISCL threshold is much lower than the IACL threshold, thermal shutdown protection may become activated only at higher ambient temperatures. Datasheet CFR0011-120-01 Revision 1.08 Page 6 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Power Dissipation The junction temperature of the SLG59M1448V depends on different factors such as board layout, ambient temperature, and other environmental factors. The primary contributor to the increase in the junction temperature of the SLG59M1448V is the power dissipation of its power MOSFET. Its power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations: PD = RDSON x IDS2 where: PD = Power dissipation, in Watts (W) RDSON = Power MOSFET ON resistance, in Ohms (Ω) IDS = Output current, in Amps (A) and TJ = PD x θJA + TA where: TJ = Junction temperature, in Celsius degrees (°C) θJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) TA = Ambient temperature, in Celsius degrees (°C) During active current-limit operation, the SLG59M1448V’s power dissipation can be calculated by taking into account the voltage drop across the load switch (VD - VS) and the magnitude of the output current in active current-limit operation (IACL): PD = (VD - VS) x IACL or PD = (VD – (RLOAD x IACL)) x IACL where: PD = Power dissipation, in Watts (W) VD = Input Voltage, in Volts (V) RLOAD = Load Resistance, in Ohms (Ω) IACL = Output limited current, in Amps (A) VS = RLOAD x IACL For more information on GreenFET load switch features, please visit our website and see App Note “AN-1068 GreenFET and High Voltage GreenFET Load Switch Basics”. Datasheet CFR0011-120-01 Revision 1.08 Page 7 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Layout Guidelines: 1.The VDD pin needs a 0.1 µF and 10 µF external capacitors to smooth pulses from the power supply. Locate these capacitors as close as possible to the SLG59M1448V's PIN1. 2. Since the D and S pins dissipate most of the heat generated during high-load current operation, it is highly recommended to make power traces as short, direct, and wide as possible. A good practice is to make power traces with absolute minimum widths of 15 mils (0.381 mm) per Ampere. A representative layout, shown in Figure 1, illustrates proper techniques for heat to transfer as efficiently as possible out of the device; 3. To minimize the effects of parasitic trace inductance on normal operation, it is recommended to connect input CIN and output CLOAD low-ESR capacitors as close as possible to the SLG59M1448V's D and S pins; 4. The GND pin should be connected to system analog or power ground plane. 5. 2 oz. copper is recommended for high current operation. SLG59M1448V Evaluation Board: А GreenFET Evaluation Board for SLG59M1448V is designed according to the statements above and is illustrated on Figure 1. Please note that evaluation board has D_Sense and S_Sense pads. They cannot carry high currents and dedicated only for RDSON evaluation. Please solder your SLG59M1448V here Figure 1. SLG59M1448V Evaluation Board. Datasheet CFR0011-120-01 Revision 1.08 Page 8 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge 1 1 VDD C2 1 2 3 4 5 VDD CAP2 GND CAP1 ON1 S2 ON2 S1 D1 D2 C1 10 9 8 7 6 CAP/RILIM ON U1 1 2 3 D_Sense1 1 2 3 4 1 VDD ON D D C3 C4 1 3 5 7 9 S_Sense1 1 C5 C6 R1 2 4 6 8 10 R2 R3 R4 C7 1 00 n R_Array 1 3 5 7 9 8 7 6 5 GND CAP S S 2 4 6 8 10 U2 9 1 2 3 4 D_Sense2 ON VDD D D D 8 7 6 5 GND CAP S S S_Sense2 1 1 C8 1 00 n U3 1 2 3 4 D_Sense3 ON VDD D D 8 7 6 5 GND CAP S S S_Sense3 1 1 C9 1 00 n U4 9 1 2 3 4 D_Sense4 1 ON VDD D D D 8 7 6 5 GND S S S S_Sense4 1 U5 1 2 3 4 D_Sense5 1 ON VIN VIN VIN 8 7 6 5 GND VOUT VOUT VOUT S_Sense5 1 U6 1 2 ON D GND S 4 3 D_Sense6 1 1 1 D/VIN D/VIN 1 S_Sense6 1 1 S/VOUT S/VOUT Figure 2. SLG59M1448V Evaluation Board Connection Circuit. Datasheet CFR0011-120-01 Revision 1.08 Page 9 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Basic Test Setup and Connections Figure 3. Typical connections for GreenFET Evaluation. EVB Configuration 1. Connect oscilloscope probes to D/VIN, S/VOUT, ON, etc.; 2.Turn on Power Supply 1 and set desired VDD from 2.5 V…5.5 V range; 3.Turn on Power Supply 2 and set desired VD from 0.9 V…5.5 V range; 4.Toggle the ON signal High or Low to observe SLG59M1448V operation. Datasheet CFR0011-120-01 Revision 1.08 Page 10 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Package Top Marking System Definition ABC Serial Number Pin 1 Identifier ABC - 3 alphanumeric Part Serial Number where A, B, or C can be A-Z and 0-9 Datasheet CFR0011-120-01 Revision 1.08 Page 11 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Package Drawing and Dimensions 8 Lead STDFN Package 1.0 x 1.6 mm (Fused Lead) Datasheet CFR0011-120-01 Revision 1.08 Page 12 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Tape and Reel Specifications Max Units Leader (min) Nominal Reel & Package # of Package Size Hub Size Length Type Pins per Reel per Box Pockets [mm] [mm] [mm] STDFN 8L 1x1.6mm 0.4P FC Green 8 1.0 x 1.6 x 0.55 3,000 3,000 178 / 60 100 400 Trailer (min) Pockets Length [mm] Tape Width [mm] 100 400 8 Part Pitch [mm] 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Pocket BTM Pocket Length Width Depth STDFN 8L 1x1.6mm 0.4P FC Green Index Hole Pitch Pocket Pitch Index Hole to Index Hole Index Hole to Tape Pocket CenDiameter Tape Edge Width ter A0 B0 K0 P0 P1 D0 E F W 1.12 1.72 0.7 4 4 1.55 1.75 3.5 8 Direction of Feed Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 0.88 mm3 (nominal). More information can be found at www.jedec.org. Datasheet CFR0011-120-01 Revision 1.08 Page 13 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1448V An Ultra-small, 17 mΩ, 2.5 A Load Switch with Discharge Revision History Date Version 2/3/2022 1.08 Updated Company name and logo Fixed typos 4/15/2021 1.07 Updated Style and Formatting Updated charts Fixed typos 8/31/2016 1.06 Updated Power up/down Sequencing Considerations 5/10/2016 1.05 Updated Power up/down Sequence section Updated Parameter names for clarity Datasheet CFR0011-120-01 Change Revision 1.08 Page 14 of 14 3-Feb-2022 ©2022 Renesas Electronics Corporation IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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