SLG59M1446V

 SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge General Description Pin Configuration Features • • • • • • • D2 1 ON2 2 ON1 3 D1 4 Two 40 mΩ 1.0 A MOSFETs Two integrated VGS Charge Pumps User selectable ramp rate with external resistor Protected by thermal shutdown Integrated Discharge Resistor Pb-Free / Halogen-Free / RoHS compliant STDFN 8L, 1.0 x 1.6 mm SLG59M1446V The SLG59M1446V is designed for load switching applications. The part comes with two 40 mΩ 1.0 A rated MOSFETs, each controlled by an ON control pin. Each MOSFET’s ramp rate is adjustable depending on the input current level of the ON pin. The product is packaged in an ultra-small 1.6 x 1.0 mm package. 8 S2 7 GND 6 VDD 5 S1 8-pin STDFN (Top View) Applications • Power-Rail Switching: • Notebook/Laptop/Tablet PCs • Smartphones/Wireless Handsets • High-definition Digital Cameras • Set-top Boxes • Point of Sales Pins • GPS Navigation Devices Block Diagram S1 D1 D2 S2 1.0 A 1.0 A VDD 2.5 V to 5.5 V Charge Pump Out Charge Pump Out ON1 ON2 CMOS Input GND Datasheet CFR0011-120-01 Revision 1.07 Page 1 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Pin Description Pin # Pin Name Type 1 D2 MOSFET Drain/Input terminal of Power MOSFET Channel 2. Connect a 10 μF (or larger) low ESR capacitor from this pin to GND. Capacitors used at D2 should be rated at 10 V or higher. Input A low-to-high transition on this pin closes the Channel 2 of load switch. ON is an asserted-HIGH, level-sensitive CMOS input with ON_VIL < 0.3 V and ON_VIH_INI > 1.2 V. Connect this pin to the output of a general-purpose output (GPO) from a microcontroller or other application processor. A resistor connected in series to ON2 signal sets the VS2 Slew Rate. Please read more information on Adjustable Slew Rate description. 2 ON2 Pin Description 3 ON1 Input A low-to-high transition on this pin closes the Channel 1 of load switch. ON is an asserted-HIGH, level-sensitive CMOS input with ON_VIL < 0.3 V and ON_VIH_INI > 1.2 V. Connect this pin to the output of a general-purpose output (GPO) from a microcontroller or other application processor. A resistor connected in series to ON1 signal sets the VS1 Slew Rate. Please read more information on Adjustable Slew Rate description. 4 D1 MOSFET Drain/Input terminal of Power MOSFET Channel 1. Connect a 10 μF (or larger) low ESR capacitor from this pin to GND. Capacitors used at D1 should be rated at 10 V or higher. 5 S1 MOSFET Source/Output terminal of Power MOSFET Channel1. Connect a 10 μF (or larger) low ESR capacitor from this pin to GND. Capacitors used at S1 should be rated at 10 V or higher. 6 VDD PWR VDD supplies the power for the operation of the load switch and internal control circuitry where its range is 2.5 V ≤ VDD ≤ 5.5 V. Bypass the VDD pin to GND with a 0.1 μF (or larger) capacitor. 7 GND GND Ground connection. Connect this pin to system analog or power ground plane. 8 S2 MOSFET Source/Output terminal of Power MOSFET Channel2. Connect a 10 μF (or larger) low ESR capacitor from this pin to GND. Capacitors used at S2 should be rated at 10 V or higher. Ordering Information Part Number Type Production Flow SLG59M1446V STDFN 8L Industrial, -40 °C to 85 °C SLG59M1446VTR STDFN 8L (Tape and Reel) Industrial, -40 °C to 85 °C Datasheet CFR0011-120-01 Revision 1.07 Page 2 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Application Diagram Current Controls Ramp Rate S2 3.3 V R2 ON2 Current Controls Ramp Rate Control IC ON1 3.3 V SLG59M1446V Control IC D2 GND VDD R1 D1 S1 Adjustable Ramp Rate vs. ON Pin Current (5.5 V, 25 °C) ON Pin Current VS(SR) (typ) 20 µA 0.56 V/ms 50 µA 1.34 V/ms 100 µA 2.53 V/ms 150 µA 3.71 V/ms 200 µA 4.68 V/ms 250 µA 5.63 V/ms 400 µA 8.4 V/ms Adjustable Slew Rate (ON2 Pin 2 and ON1 Pin3) SLG59M1446V has a built in configurable slew control feature. The configurable slew control uses current detection method on ON1/ON2. When ON voltage rises above ON_VIH_INI (1.2 V typical), the slew control circuit will measure the current flowing into ON1/ON2. Based on the current flowing into ON1/ON2, different slew rates will be selected by the internal control circuit. See ON Pin Curent vs. VS(SR) table. The slew rate is configurable by selecting a different R1/R2 resistor value as shown on application diagram. Calculating the R1/R2 value depends on both the desired slew rate, and the VOH level of the device driving the ON1/ON2 pin. ON Pin Current = (GPIO_VOH – ON_VREF (1.05 V typical)) / R By driving the ON pin without any series resistor, the Slew Rate will be around 8.4 V/ms and max ON pin Current will be approximately 400 µA. Datasheet CFR0011-120-01 Revision 1.07 Page 3 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Absolute Maximum Ratings Parameter Description VDD Power Supply Voltage TS Storage Temperature Conditions Min. Typ. Max. Unit -- -- 6 V -65 -- 150 °C ESDHBM ESD Protection Human Body Model 2000 -- -- V ESDCDM ESD Protection Charged Device Model 1000 -- -- V -- °C/W MSL θJA WDIS Moisture Sensitivity Level Thermal Resistance, 1 1 x 1.6mm STDFN; Determined using 1 in2, 1 oz. copper pads under each Dx and Sx terminal and FR4 pcb material -- Package Power Dissipation MOSFET IDSPK Peak Current from Drain to Source For no more than 1 ms with 1% duty cycle 72 -- -- 0.4 W -- -- 1.5 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics TA = -40 °C to 85 °C (unless otherwise stated) Parameter Description Conditions Min. Typ. Max. Unit VDD Power Supply Voltage Pin 6 2.5 -- 5.5 V VD1 Load Switch Input Voltage of Channel 1 Pin 4 0.85 -- VDD V VD2 Load Switch Input Voltage of Channel 2 Pin 1 0.85 -- VDD V IDD Power Supply Current (PIN 6) when OFF -- 0.1 1 µA when ON, No load -- 35 50 µA TA = 25 °C, IDS = 100 mA -- 40 50 mΩ TA = 70 °C, IDS = 100 mA -- 50 55 mΩ TA = 85 °C, IDS = 100 mA -- 55 65 mΩ Continuous -- -- 1.0 A 50% ON to VS[1,2] Ramp Start; ON Pin Current (PIN2, PIN3) = 20 µA; VDD = VD[1,2] = 5 V; CLOAD = 10 μF; RLOAD = 20 Ω -- 2.4 4.0 ms RDSON[1,2] ON Resistance MOSFET IDS Current from D[1,2] to S[1,2] TON_Delay ON Delay Time Configurable1 50% ON to 90% VS[1,2] TTotal_ON Total Turn On Time Example: ON Pin Current (PIN2, PIN3) = 20 μA; VDD = VD[1,2] = 5 V; CLOAD = 10 μF; RLOAD = 20 Ω -- RDISCHRG Datasheet CFR0011-120-01 VS[1,2] Slew Rate Discharge Resistance -- Configurable1 10% VS [1,2] to 90% VS[1,2] VS(SR) 11.7 ms ms V/ms Example: ON Pin Current (PIN2, PIN3) = 20 μA; VDD = VD[1,2] = 5 V; CLOAD = 10 μF; RLOAD = 20 Ω -- 0.56 -- V/ms VDD = 2.5 V to 5.5 V; VS[1,2] = 0.4 V Input bias 100 150 300 Ω Revision 1.07 Page 4 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Electrical Characteristics (continued) TA = -40 °C to 85 °C (unless otherwise stated) Parameter Min. Typ. Max. Unit -- -- 100 µF 0.99 1.05 1.10 V Internal Charge Pump ON 1.2 -- VDD V Internal Charge Pump OFF -0.3 0 0.3 V 100 -- -- MΩ Thermal shutoff turn-on temperature -- 125 -- °C THERMOFF Thermal shutoff turn-off temperature -- 100 -- °C CLOAD ON_VREF Description Conditions Output Load Capacitance CLOAD connected from S[1,2] to GND ON Pin Reference Voltage 2 ON_VIH_INI Initial Turn On Voltage ON_VIL Low Input Voltage on ON pin ON_R Input Impedance on ON pin THERMON THERMTIME Thermal shutoff time TOFF_Delay OFF Delay Time 50% ON to VS[1,2] Fall Start; VD[1,2] = 5 V; RLOAD = 20 Ω; no CLOAD TFALL VS[1,2] Fall Time 90% VS[1,2] to 10% VS[1,2]; VD[1,2] = 5 V; RLOAD = 20 Ω; no CLOAD -- -- 1 ms -- 55 70 µs -- 32 -- μs Notes: 1. Refer to table for configuration details. 2. Voltage before ON pin resistor needs to be higher than 1.2 V to generate required ION TON_Delay, VS(SR), and TTotal_ON Timing Details ON[1,2]* 50% ON 50% ON TOFF_Delay 90% VS VS[1,2] 90% VS TON_Delay 10% VS 10% VS VS(SR) (V/ms) TFALL TTotal_ON *Rise and Fall Times of the ON Signal are 100 ns Datasheet CFR0011-120-01 Revision 1.07 Page 5 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Typical Performance Characteristics Slew Rate vs. ON Current TTotal_ON vs. ON Current Datasheet CFR0011-120-01 Revision 1.07 Page 6 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Power Dissipation The junction temperature of the SLG59M1446V depends on factors such as board layout, ambient temperature, external air flow over the package, load current, and the RDSON-generated voltage drop across each power MOSFET. While the primary contributor to the increase in the junction temperature of the SLG59M1446V is the power dissipation of its power MOSFETs, its power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations: PDTOTAL = (RDSON1 x IDS12) + (RDSON2 x IDS22) where: PDTOTAL = Total package power dissipation, in Watts (W) RDSON[1,2] = Channel 1 and Channel 2 Power MOSFET ON resistance, in Ohms (Ω), respectively IDS[1,2] = Channel 1 and Channel 2 Output current, in Amps (A), respectively and TJ = PDTOTAL x θJA + TA where: TJ = Die junction temperature, in Celsius degrees (°C) θJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) – highly dependent on pcb layout TA = Ambient temperature, in Celsius degrees (°C) In nominal operating mode, the SLG59M1446V’s power dissipation can also be calculated by taking into account the voltage drop across each switch (VDx - VSx) and the magnitude of that channel’s output current (IDSx): PDTOTAL = [(VD1-VS1) x IDS1] + [(VD2-VS2) x IDS2] or PDTOTAL = [(VD1 – (RLOAD1 x IDS1)) x IDS1] + [(VD2 – (RLOAD2 x IDS2)) x IDS2] where: PDTOTAL = Total package power dissipation, in Watts (W) VD[1,2] = Channel 1 and Channel 2 Input Voltage, in Volts (V), respectively RLOAD[1,2] = Channel 1 and Channel 2 Output Load Resistance, in Ohms (Ω), respectively IDS[1,2] = Channel 1 and Channel 2 output current, in Amps (A), respectively VS[1,2] = Channel 1 and Channel 2 output voltage, or RLOAD[1,2] x IDS[1,2] , respectively Datasheet CFR0011-120-01 Revision 1.07 Page 7 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Layout Guidelines: 1. The VDD pin needs a 0.1 µF external capacitor to smooth pulses from the power supply. Locate this capacitor as close as possible to the SLG59M1446V's PIN6. 2. Since the D1, D2, S1 and S2 pins dissipate most of the heat generated during high-load current operation, it is highly recommended to make power traces as short, direct, and wide as possible. A good practice is to make power traces with absolute minimum widths of 15 mils (0.381 mm) per Ampere. A representative layout, shown in Figure 1, illustrates proper techniques for heat to transfer as efficiently as possible out of the device; 3. To minimize the effects of parasitic trace inductance on normal operation, it is recommended to connect input CIN and output CLOAD low-ESR capacitors as close as possible to the SLG59M1446V's D1, D2, S1 and S2 pins; 4. The GND pin should be connected to system analog or power ground plane. 5. 2 oz. copper is recommended for high current operation. SLG59M1446V Evaluation Board: А GreenFET Evaluation Board for SLG59M1446V is designed according to the statements above and is illustrated on Figure 1. Please note that evaluation board has D_Sense and S_Sense pads. They cannot carry high currents and dedicated only for RDSON evaluation. Please solder your SLG59M1446V here Figure 1. SLG59M1446V Evaluation Board. Datasheet CFR0011-120-01 Revision 1.07 Page 8 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge 1 2 3 4 5 Dual 1 1 VDD C1 10 9 8 7 6 VDD CAP2 GND CAP1 ON1 S2 ON2 S1 D1 D2 CAP Array 1 S Sense1.1 1 C2 D Sense1.1 1 D Sense1.2 1 R2_Array 1 3 5 7 9 ON2 2 4 6 8 10 U1 1 2 3 4 5 6 7 1 3 5 7 9 D1 D1 ON1 VDD ON2 D2 D2 S1 S1 CAP1 GND CAP2 S2 S2 14 13 12 11 10 9 8 2 4 6 8 10 CAP Array 2 1 3 5 7 9 S Sense1.2 1 C3 2 4 6 8 10 C5 C7 D Sense2.2 1 3 2 1 D Sense2.1 1 RL1 U2 1 2 3 4 D2 ON2 ON1 D1 S2 GND VDD S1 S Sense2.2 1 S Sense2.1 1 RL2 C4 RL1 8 7 6 5 RL2 C6 ON4 S1 S1 1 1 1 1 D1 D1 3 2 1 3 2 1 1 1 D2 S2 S2 1 1 2 3 4 5 D Sense3 1 2 3 4 5 Quad V_IN GND ON1 ON2 ON3 V4_OUT V3_OUT V2_OUT V1_OUT ON4 U3 VO1 ON1 ON2 VO2 VIN GND VO4 ON4 ON3 VO3 S Sense3.1 10 9 8 7 6 1 S Sense3.2 1 S Sense3.3 1 1 10 9 8 7 6 VO3 S Sense3.4 1 ON3 D2 1 ON1 2 4 6 8 10 1 1 3 5 7 9 1 R1_Array VO4 RL3 C8 RL4 C9 3 2 1 Figure 2. SLG59M1446V Evaluation Board Connection Circuit. Datasheet CFR0011-120-01 Revision 1.07 Page 9 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Basic Test Setup and Connections Figure 3. Typical connections for GreenFET Evaluation. EVB Configuration 1.Connect oscilloscope probes to D1/VIN, D2, S1/VO1, S2/VO2, ON1, ON2 etc.; 2.Turn on Power Supply 1 and set desired VDD from 2.5 V…5.5 V range; 3.Turn on Power Supply 2, 3 and set desired VD[1,2] from 0.85 V…VDD range; 4.Toggle the ON[1,2] signal High or Low to observe SLG59M1446V operation. Datasheet CFR0011-120-01 Revision 1.07 Page 10 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge SLG59M1446V Layout Suggestion Package Top Marking System Definition ABC Serial Number Pin 1 Identifier ABC - 3 alphanumeric Part Serial Number where A, B, or C can be A-Z and 0-9 Datasheet CFR0011-120-01 Revision 1.07 Page 11 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Package Drawing and Dimensions 8 Lead STDFN Package 1.0 x 1.6 mm Datasheet CFR0011-120-01 Revision 1.07 Page 12 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Tape and Reel Specifications Max Units Leader (min) Nominal Reel & Package # of Package Size Hub Size Length Type Pins per Reel per Box Pockets [mm] [mm] [mm] STDFN 8L 1x1.6mm 0.4P Green 8 1.0 x 1.6 x 0.55 3,000 3,000 178 / 60 100 400 Trailer (min) Pockets Length [mm] Tape Width [mm] 100 400 8 Part Pitch [mm] 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Pocket BTM Pocket Length Width Depth STDFN 8L 1x1.6mm 0.4P Green Index Hole Pitch Pocket Pitch Index Hole to Index Hole Index Hole to Tape Pocket CenDiameter Tape Edge Width ter A0 B0 K0 P0 P1 D0 E F W 1.12 1.72 0.7 4 4 1.55 1.75 3.5 8 Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 0.88 mm3 (nominal). More information can be found at www.jedec.org. Datasheet CFR0011-120-01 Revision 1.07 Page 13 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1446V Ultra-small Dual 40 mΩ, 1.0 A Load Switch with Discharge Revision History Date Version 2/2/2022 1.07 Updated Company name and logo Fixed typos 3/10/2021 1.06 Updated Slew Rate vs. ON Pin Current table 9/13/2019 1.05 Updated Pin Descriptions Updated style and formatting Updated Charts Added Power Dissipation Updated POD Fixed typos 12/4/2015 1.04 Updated Block Diagram 11/20/2015 1.03 Added ESDCDM, MSL, and θJA specs Datasheet CFR0011-120-01 Change Revision 1.07 Page 14 of 14 2-Feb-2022 ©2022 Renesas Electronics Corporation IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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