IS31FL3239
24-CHANNEL LED DRIVER
August 2019
GENERAL DESCRIPTION
FEATURES
The IS31FL3239 is an LED driver with 24 constant
current channels. Each channel can be pulse width
modulated (PWM) by 16 bits for smooth LED
brightness control. In addition, each channel has an
8-bit output current control register which allows fine
tuning the current for rich RGB color mixing, e.g., a
pure white color LED application. The maximum output
current of each channel is 38mA, which can be
adjusted by one 8-bit global control register.
Proprietary programmable technology is used to
minimize audible noise caused by MLCC decoupling
capacitors. All registers can be programmed via a high
speed I2C (1MHz).
The IS31FL3239 can be shut down with minimum
current consumption by either pulling the SDB pin low
or by using the software shutdown feature.
The IS31FL3239 is available in QFN-32 (4mm×4mm)
package. It operates from 2.7V to 5.5V over the
temperature range of -40°C to +125°C.
2.7V to 5.5V VCC supply
1MHz I2C interface, automatic address increment
function with readout function
Four selectable I2C addresses
Accurate Color Rendition
- Selectable 16-bit PWM 256/1024/4096/65536
- 8-bit Dot correction
- 8-bit Global current adjust
Open/short detect function
62kHz PWM frequency (8-bit PWM)
Temperature detect function
EMI Reduction Technology
- Spread spectrum
- Selectable 6 phase delay
- 180 degree phase delay
-40°C to +125°C temperature range
QFN-32 (4mm×4mm) package
APPLICATIONS
AI-speakers and smart home devices
LED in home appliances
LED display for hand-held devices
TYPICAL APPLICATION CIRCUIT
Figure 1
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Rev. A, 07/29/2019
Typical Application Circuit
1
IS31FL3239
Figure 2
Typical Application Circuit (VCC=5V)
Note 1: VLED+ should be same as VCC voltage.
Note 2: VIH is the high level voltage for IS31FL3239, which is usually same as VCC of Micro Controller, e.g. if VCC of Micro Controller is 3.3V,
VIH=3.3V. If VCC=5V and VIH is lower than 2.8V, recommend to add a level shift circuit.
Note 3: These resistors are optional to help reduce the power of IS31FL3239 only (values are for VLED+=5V).
Note 4: The output current is set up to 23mA when RISET = 3.3kΩ. The maximum global output current can be set by external resistor, RISET.
Please refer to the detail application information in RISET section.
Note 5: The IC should be placed far away from the antenna in order to prevent the EMI.
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2
IS31FL3239
PIN CONFIGURATION
Package
Pin Configuration (Top View)
QFN-32
PIN DESCRIPTION
No.
Pin
Description
1~12
OUT1 ~ OUT12
Output channel 1~12 for LEDs.
13,29
GND
Ground.
14~25
OUT13 ~ OUT24
Output channel 13~24 for LEDs.
26
SDB
Shutdown the chip when pulled low.
27
AD
I2C address setting.
28
VCC
Power supply.
30
ISET
Input terminal used to connect an external resistor.
This regulates the global output current. When
RISET=3.3kΩ, IOUT=23mA.
31
SDA
I2C serial data.
32
SCL
I2C serial clock.
Thermal Pad
Need to connect to GND.
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3
IS31FL3239
ORDERING INFORMATION
Industrial Range: -40°C to +125°C
Order Part No.
Package
QTY/Reel
IS31FL3239-QFLS4-TR
QFN-32, Lead-free
2500
Copyright © 2019 Lumissil Microsystems. All rights reserved. Lumissil Microsystems reserves the right to make changes to this specification and its
products at any time without notice. Lumissil Microsystems assumes no liability arising out of the application or use of any information, products or
services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and
before placing orders for products.
Lumissil Microsystems does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in
such applications unless Lumissil Microsystems receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Lumissil Microsystems is adequately protected under the circumstances
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4
IS31FL3239
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at SCL, SDA, SDB, OUT1 to OUT24
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA=TJ
Package thermal resistance, junction to ambient (4 layer
standard test PCB based on JESD 51-2A), θJA
ESD (HBM)
ESD (CDM)
-0.3V ~ +6.0V
-0.3V ~ VCC+0.3V
+150°C
-65°C ~ +150°C
-40°C ~ +125°C
51.5°C/W
±8kV
±750V
Note 6: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Typical values are TA = 25°C, VCC = 5V.
Symbol
VCC
Parameter
Condition
Supply voltage
VCC= 5V, VOUT= 0.8V, RISET= 2kΩ,
GCC= 0xFF, Scaling= 0xFF (Note 7)
Output current
VCC= 5V, VOUT= 0.6V, RISET= 3.3kΩ,
GCC= 0xFF, Scaling= 0xFF
∆IMAT
Channel mismatch
RISET= 3.3kΩ, GCC= 0xFF,
Scaling= 0xFF, IOUT= 23mA
VHR
Headroom voltage
RISET= 3.3kΩ, GCC= 0xFF,
Scaling= 0xFF, IOUT= 23mA
ICC
ISD
Quiescent power supply
current
Shutdown current
Typ.
2.7
Maximum output current
IOUT
Min.
Max.
Unit
5.5
V
38
21.39
23
mA
24.61
mA
7
%
0.3
0.5
V
RISET= 3.3kΩ, GCC= 0xFF, Scaling=
0xFF, IOUT= 23mA,PWM= 0x00,
VCC=3.6V
4.7
7
mA
RISET= 3.3kΩ, GCC= 0xFF, Scaling=
0xFF, IOUT= 23mA,PWM= 0x00,
VCC=5V
5.7
8
mA
RISET= 3.3kΩ, VSDB= 0V or software
shutdown, VCC= 3.6V
0.8
1.6
μA
RISET= 3.3kΩ, VSDB= 0V or software
shutdown, VCC= 5V
1.8
3
μA
-7
fOUT
PWM frequency of output
OSC= 8MHz, PWM Resolution= 8bit
31.5
kHz
TSD
Thermal shutdown
(Note 8)
165
°C
Thermal shutdown hysteresis
(Note 8)
20
°C
TSD_HY
Logic Electrical Characteristics (SDA, SCL, SDB, AD)
VIL
Logic “0” input voltage
VCC= 2.7V~5.5V
VIH
Logic “1” input voltage
VCC= 2.7V~5.5V
IIL
Logic “0” input current
VINPUT= 0V (Note 8)
5
nA
IIH
Logic “1” input current
VINPUT= VCC (Note 8)
5
nA
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0.4
1.4
V
V
5
IS31FL3239
DIGITAL INPUT SWITCHING CHARACTERISTICS (NOTE 8)
Symbol
Parameter
fSCL
Serial-clock frequency
tBUF
Bus free time between a STOP and a START
condition
Fast Mode
Min.
Typ.
Fast Mode Plus
Max. Min.
Typ.
Max.
Units
-
400
-
1000 kHz
1.3
-
0.5
-
μs
tHD, STA Hold time (repeated) START condition
0.6
-
0.26
-
μs
tSU, STA Repeated START condition setup time
0.6
-
0.26
-
μs
tSU, STO STOP condition setup time
0.6
-
0.26
-
μs
tHD, DAT Data hold time
-
-
-
-
μs
tSU, DAT Data setup time
100
-
50
-
ns
tLOW
SCL clock low period
1.3
-
0.5
-
μs
tHIGH
SCL clock high period
0.7
-
0.26
-
μs
tR
Rise time of both SDA and SCL signals,
receiving
-
300
-
120
ns
tF
Fall time of both SDA and SCL signals,
receiving
-
300
-
120
ns
Note 7: The recommended minimum value of RISET is 2kΩ.
Note 8: Guaranteed by design.
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6
IS31FL3239
FUNCTIONAL BLOCK DIAGRAM
VCC
PWM
Control
SDA
SCL
Output
Driver
I2C
Interface
OUT1~OUT24
Register
Bias
AD
ISET
6 Group
CNT
Bandgap
MUX
SD_Chip
SDB
OSC
Spread
Spectrum
GND
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IS31FL3239
DETAILED DESCRIPTION
Then the master sends an SCL pulse. If the
IS31FL3239 has received the address correctly, then it
holds the SDA line low during the SCL pulse. If the
SDA line is not low, then the master should send a
“STOP” signal (discussed later) and abort the transfer.
I2C INTERFACE
The IS31FL3239 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31FL3239 has a 7-bit
slave address (A7:A1), followed by the R/W bit, A0. Set
A0 to “0” for a write command and set A0 to “1” for a
read command. The value of bits A1 and A2 are
decided by the connection of the AD pin. The complete
slave address is:
Following acknowledge of IS31FL3239, the register
address byte is sent, most significant bit first.
IS31FL3239 must generate another acknowledge
indicating that the register address has been received.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31FL3239 must generate another acknowledge to
indicate that the data was received.
Table 1 Slave Address
Bit
A7:A3
A2:A1
Value
01101
AD
AD connected to GND, AD = 00;
AD connected to VCC, AD = 11;
AD connected to SCL, AD = 01;
AD connected to SDA, AD = 10;
A0
0/1
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
ADDRESS AUTO INCREMENT
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 2kΩ). The maximum clock frequency
specified by the I2C standard is 1MHz. In this
discussion, the master is the microcontroller and the
slave is the IS31FL3239.
To write multiple bytes of data into IS31FL3239, load
the address of the data register that the first data byte
is intended for. During the IS31FL3239 acknowledge
of receiving the data byte, the internal address pointer
will increment by one. The next data byte sent to
IS31FL3239 will be placed in the new address, and so
on. The auto increment of the address will continue as
long as data continues to be written to IS31FL3239
(Figure 6).
The timing diagram for the I2C is shown in Figure 3.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
READING OPERATION
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
Most of the registers can be read.
To read the register, after I2C start condition, the bus
master must send the IS31FL3239 device address
____
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
with the R/W bit set to “0”, followed by the register
address which determines which register is accessed.
Then restart I2C, the bus master should send the
After the last bit of the chip address is sent, the master
checks for the IS31FL3239’s acknowledge. The master
releases the SDA line high (through a pull-up resistor).
IS31FL3239 device address with the R/W bit set to
“1”. Data from the register defined by the command
byte is then sent from the IS31FL3239 to the master
(Figure 7).
Figure 3
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____
Interface Timing
8
IS31FL3239
Figure 4
Figure 5
Figure 6
Bit Transfer
Writing to IS31FL3239 (Typical)
Writing to IS31FL3239 (Automatic Address Increment)
Figure 7
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Reading from IS31FL3239
9
IS31FL3239
REGISTER DEFINITIONS
Table 2 Register Function
Address
Name
00h
Function
Control Register
R/W
Table Default
Power control register
R/W
3
Channel [24:1] PWM register byte
R/W
5
Update Register
Update the PWM and Scaling data
W
-
LED Scaling Register
Control each channel’s DC current
R/W
7
6Eh
Global Current Control Register
Control Global DC current/SSD
R/W
8
70h
Phase Delay and Clock Phase
Register
Phase Delay and Clock Phase
R/W
9
71h
Open Short Detect Enable Register
Open short detect enable
R/W
10
LED Open/Short Register
Open short information
R/W
11
77h
Temperature Sensor Register
Temperature information
R/W
12
78h
Spread Spectrum Register
Spread spectrum control register
R/W
13
7Fh
Reset Register
Reset all registers
W
-
05h~0Ch
11h~18h
1Dh~2Ch PWM Register
31h~38h
3Dh~44h
49h
4Ch~4Fh
52h~55h
58h~5Fh
62h~65h
68h~6Bh
72h~76h
Table 3 00h Control Register
Bit
D7
D6:D4
D3
D2:D1
D0
Name
-
OSC
-
PMS
SSD
Default
0
000
0
00
0
The Control Register sets software shutdown mode,
internal oscillator clock frequency and PWM resolution.
The internal oscillator clock frequency and the PWM
resolution will decide the output PWM frequency.
Recommend selecting PWM frequency lower than
500Hz or higher than 20kHz to avoid MLCC audible
noise as shown in Table 4.
SSD
0
1
Software Shutdown Enable
Software shutdown mode
Normal operation
OSC
000
001
010
011
100
101
110
111
Oscillator Clock Frequency Selection
16MHz
8MHz
1MHz
500kHz
250kHz
125MHz
62kHz
31kHz
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PMS
00
01
10
11
0000
0000
PWM Resolution
8-bit
10-bit
12-bit
16-bit
Table 4 PWM Frequency
PWM
16M
Resolution
8M
1M
500k 250k 125k 62k
31k
8-bit
62k
32k
4k
2k
1k
0.5k
244
122
10-bit
16k
8k
1k
0.5k
244
122
NA
NA
12-bit
4k
2k
244
122
NA
NA
NA
NA
16-bit
244
122
NA
NA
NA
NA
NA
NA
Table 5
05h~0Ch,11h~18h,1Dh~2Ch,31h~38h,3Dh~44h
PWM Register (OUT1~OUT24)
Reg
05h, 07h, 09h…
06h, 08h, 0Ah…
Bit
D7:D0
D7:D0
Name
PWM_H
PWM_L
Default
0000 0000
0000 0000
Each output has 2 bytes to modulate the PWM duty in
256/1024/4096/65536 steps. If using 8 bit PWM
resolution, only PWM_L bits need to be set.
10
IS31FL3239
The value of the SL (Scaling Register) decides the
peak current of each LED noted IOUT.
IOUT and the value of the PWM Registers decide the
average current of each LED noted ILED.
IOUT is computed by Formula (1):
I OUT I OUT ( MAX )
GCC
SL
256
256
Table 6 PWM and Scaling Register Map
PWM
OUT
PWM_H
PWM_L
1
06h
05h
4Ch
2
08h
07h
4Dh
3
0Ah
09h
4Eh
4
0Ch
0Bh
4Fh
5
12h
11h
52h
6
14h
13h
53h
7
16h
15h
54h
8
18h
17h
55h
9
1Eh
1Dh
58h
10
20h
1Fh
59h
11
22h
21h
5Ah
12
24h
23h
5Bh
13
26h
25h
5Ch
14
28h
27h
5Dh
15
2Ah
29h
5Eh
16
2Ch
2Bh
5Fh
17
32h
31h
62h
18
34h
33h
63h
19
36h
35h
64h
20
38h
37h
65h
21
3Eh
3Dh
68h
22
40h
3Fh
69h
23
42h
41h
6Ah
24
44h
43h
6Bh
(1)
ILED computed by Formula (2):
I LED
PWM
I OUT
N
PWM
(2)
15
D[ n ] 2
n
(3)
n0
Where IOUT(MAX) is the maximum output current decided
by RISET (Check RISET section for more information),
GCC is the global current setting (6Eh), and SL is the
scaling of each output (4Ch~4Fh, 52h~55h, 58h~5Fh,
62h~65h, 68h~6Bh),
N=256/1024/4096/65536(8/10/12/16
bit
PWM
resolution).
For example: RISET=3.3kΩ, GCC=0xFF, SL=0xFF,
PMS=“11” (16-bit PWM resolution), PWM_H=0xFF,
PWM_L=0xFF, IOUT(MAX) = 23.18mA
I OUT I OUT ( MAX )
PWM
255 255
23 mA (1)
256 256
15
D[ n ] 2
n
65535
(3)
n0
N= 65536
I LED
65535
23 mA 23 mA
65536
(2)
Where IOUT(MAX) is the maximum output current decided
by RISET (Check RISET section for more information)
The IOUT of each channel is setting by the SL bits of
LED Scaling Register (4Ch~4Fh, 52h~55h, 58h~5Fh,
62h~65h, 68h~6Bh). Please refer to the detail
information in Table 7.
If RISET=3.3kΩ, GCC=0xFF, SL=0xFF, PMS= “00” (8-bit
PWM resolution, only use the PWM_L, the PWM_H
will be ignored), PWM_H=0x77, PWM_L=0xAA,
IOUT(MAX) = 23.18mA
I OUT
255 255
I OUT ( MAX )
23 mA (1)
256 256
PWM
8
D[ n ] 2 n 170
(3)
n0
N= 256
I LED
170
23 mA
256
(2)
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SL
49h Update Register
When SDB= “H” and SSD= “1”, a write of “0000 0000”
to 49h to update PWM registers (05h~0Ch, 11h~18h,
1Dh~2Ch, 31h~38h, 3Dh~44h).
Table 7
4Ch~4Fh, 52h~55h, 58h~5Fh, 62h~65h, 68h~6Bh
LED Scaling Register (OUT1~OUT24)
Bit
D7:D0
Name
SL
Default
0000 0000
Each output has 8 bits to modulate DC current in 256
steps.
The value of the SL Registers decides the DC peak
current of each LED noted IOUT.
IOUT is computed by Formula (1):
11
IS31FL3239
I OUT I OUT ( MAX )
SL
GCC
SL
256
256
OSDE
00
01
10
11
(1)
7
D[ n ] 2
n
(4)
n0
Where IOUT(MAX) is the maximum output current decided
by RISET. GCC is the global current setting (6Eh) and
4Ch~4Fh, 52h~55h, 58h~5Fh, 62h~65h, 68h~6Bh
don’t need to update by 49h, each register will be
updated immediately when it is written.
Table 8 6Eh Global Current Control Register
Bit
D7:D0
Name
GCC
Default
0000 0000
7
D[ n ] 2
n
n0
(5)
If GCC=0xFF, SL=0xFF, IOUT=IOUT(MAX)
If GCC=0x01, SL=0xFF,
I OUT I OUT ( MAX )
1
255
256 256
Table 9 70h Phase Delay and Clock Phase
Register
D7
Name
PDE
-
Default
0
0
72h
D7:D6
D5:D2
D1:D0
Name
-
OP/ST[4:1]
-
Default
00
0000
00
72h
D7:D6
D5:D4
D3:D0
Name
OP/ST[10:9]
-
OP/ST[8:5]
Default
00
00
0000
Table 11-3 74h LED Open/Short Register
Bit
D7:D6
D5:D0
Name
-
OP/ST[16:11]
Default
00
00 0000
Table 11-4 75h LED Open/Short Register
Where IOUT(MAX) is the maximum output current decided
by RISET (Check RISET section for more information).
Bit
Table 11-1 72h LED Open/Short Register
Table 11-2 73h LED Open/Short Register
GCC and SL control the IOUT as shown in Formula (1).
GCC
Open Detect Enable
Detect disable
Detect disable
Short detect enable
Open detect enable
72h
D7:D6
D5:D4
D3:D0
Name
OP/ST[22:21]
-
OP/ST[20:17]
Default
00
00
0000
Table 11-5 76h LED Open/Short Register
D4
D3
D2
D1
D0
Bit
D7:D3
D2:D0
PS
PS
PS
PS
PS
PS
Name
-
OP/ST[24:23]
0
0
0
0
0
0
Default
0000 00
00
D6 D5
IS31FL3239 features a 6 phase delay function, when
this bit is set, the phase delay function is enabled.
PDE
0
1
Phase Delay Enable
Phase delay disable
Phase delay enable
PS
0
1
Phase Select
Phase delay 0 Degree
Phase delay 180 Degree
Open or short status is stored in 72h to 76h.
OP[24:1]
0
1
Open Information of OUT24:OUT1
Open not detected
Open detected
ST[24:1]
0
1
Short Information of OUT24:OUT1
Short not detected
Short detected
Table 12 77h Temperature Sensor Register
Table 10 71h Open Short Detect Enable Register
Bit
D7:D2
D1:D0
Name
-
OSDE
Default
0000 00
00
OSDE enables the detection with the result stored in
72h~76h, notice either open or short information is
saved not both
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Bit
D7:D6
D5
D4
D3:D2
D1:D0
Name
TROF
-
T_Flag
-
TS
Default
00
0
0
00
00
TS stores the temperature/thermal roll-off point. TROF
stores percentage of output current of the thermal
rool-off function.
Read T_Flag=1 indicates die temperature exceeds the
setting point (TS). Before each reading of 77h register,
TROF and TS need to be re-written.
12
IS31FL3239
TROF
00
01
10
11
Thermal roll off percentage of output
current
100%
75%
55%
30%
00
01
10
11
Temperature Point, Thermal roll off start
point
140°C
120°C
100°C
90°C
T_Flag
0
1
Temperature Flag
Temperature point not exceeded
Temperature point exceeded
TS
Table 13 78h Spread Spectrum Register
Bit
D7:D5
D4
D3:D2
D1:D0
Name
DCPWM
SSP
RNG
CLT
Default
000
0
00
00
When DCPWM is set to “0”, the PWM outputs are
decided
by
PWM
Register
(05h~0Ch,11h~18h,1Dh~2Ch,31h~38h,3Dh~44h),
and the PWM range is 0/256~255/256, still the 1/256
can’t be turned on. When the DCPWM is set to “1”, no
matter what the values in PWM Registers are, the
output will be turned on 256/256, the output will open
totally.
Spread spectrum register configures the spread
spectrum function, adjust the cycle time and range.
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Rev. A, 07/29/2019
DCPWM
xx0
xx1
x0x
x1x
0xx
1xx
Setting the output to work in DC mode
Output 1~8 PWM data set by registers
05h~0Ch,11h~18h
Output 1~8 set to 256/256 turn on
(PWM=256)
Output 9~16 PWM data set by registers
1Dh~2Ch
Output 9~16 set to 256/256 turn on
(PWM=256)
Output 17~24 PWM data set by
registers 31h~38h,3Dh~44h
Output 17~24 set to 256/256 turn on
(PWM=256)
SSP
0
1
Spread Spectrum Enable
Disable
Enable
CLT
00
01
10
11
Spread Spectrum Cycle Time
1980μs
1200μs
820μs
660μs
RNG
00
01
10
11
Spread Spectrum Range
±5%
±15%
±24%
±34%
7Fh Reset Register
A write of “0000 0000” to 7Fh will reset all registers to
their default values.
13
IS31FL3239
APPLICATION INFORMATION
RISET
The maximum output current IOUT(MAX) of OUT1~OUT24
can be adjusted by the external resistor, RISET, as
described in Formula (6).
I OUT ( MAX ) x
V ISET
R ISET
(6)
x = 58.84, VISET = 1.3V.
The recommended minimum value of RISET is 2kΩ.
When RISET=3.3kΩ, IOUT(MAX)=23.18mA
When RISET=2kΩ, IOUT(MAX)=38.25mA
CURRENT SETTING
The maximum output current is set by the external
register RISET. The current of each output can also be
set independently by the SL 8 bits of LED Scaling
Register (4Ch~4Fh, 52h~55h, 58h~5Fh, 62h~65h,
68h~6Bh).
surges when the OUTx channels turn ON. These
current surges will generate an AC ripple on the power
supply which cause stress to the decoupling
capacitors. When the AC ripple is applied to a
monolithic ceramic capacitor chip (MLCC) it will
expand and contract causing the PCB to flex and
generate audible hum in the range of between 300Hz
to 18kHz, To avoid this hum, there are many
countermeasures, such as selecting the capacitor type
and value which will not cause the PCB to flex and
contract.
An additional option for avoiding audible hum is to set
the
IS31FL3239’s
output
PWM
frequency
above/below the audible range. The Control Register
(00h) can be used to set the switching frequency to
122Hz~62kHz as shown in Table 4, some combine
setting of the OSC and PMS bits will get different
output PWM frequency, and higher than 20kHz or
lower than 500Hz is out of the audible range.
OPEN/SHORT DETECT FUNCTION
Some applications may require the IOUT of each
channel need to be adjusted independently. For
example, if OUT1 drives 1 LED and OUT2 drives 2
parallel LEDs, and they should have the same average
current like 18mA, we can set the IOUT(Max) to 36mA, and
GCC=0xFF, 4Ch=0x80, 4Dh=0xFF, the OUT1 sinks
about 18mA and OUT2 sinks 36mA which can have
two LEDs in parallel.
IS31FL3239 has open and short detect bit for each
LED.
Another example, OUT1, OUT2 and OUT3 drive an
RGB LED, OUT1 is Red LED, OUT2 is Green LED and
OUT 3 is Blue LED, with same RISET, GCC and same
SL bits, when OUT1 OUT2 and OUT3 have the same
PWM value, the LED may looks a litter pink, or not so
white, in this case, the SL bits can be used to adjust the
single IOUTx of some output and make it pure white
color. We call this SL bits another name: white balance
registers.
The Global Current Control Register (6Eh) needs to
set to 0x01 in order to get the right open/short data.
PWM CONTROL
The PWM Registers (05h~0Ch, 11h~18h, 1Dh~2Ch,
31h~38h, 3Dh~44h) can modulate LED brightness of
each 24 channels with 256/1024/4096/65536 steps.
For example, if the data in PWM_H register is “0000
0000” and in PWM_L register is “0000 0100”, then the
PWM is the fourth step.
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
PWM FREQUENCY SELECT
The IS31FL3239 output channels operate with a
default 8 bit PWM resolution and the PWM frequency
of 62kHz (the oscillator frequency is 16MHz). Because
all the OUTx channels are synchronized, the DC power
supply will experience large instantaneous current
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Rev. A, 07/29/2019
By setting the OSDE bit of Open Short Detect Enable
Register (71h) from “00” to “10” (store short
information) or “11” (store open information), the LED
Open/Short Register will store the open/short
information immediately the MCU can get the
open/short information by reading the 72h~76h.
SPREAD SPECTRUM FUNCTION
PWM current switching of LED outputs can be
particularly troublesome when the EMI is concerned.
To optimize the EMI performance, the IS31FL3239
includes a spread spectrum function. By setting the
RNG bit of Spread Spectrum Register (78h), Spread
Spectrum range can be choose from ±5% /±15%
/±24% /±34%. The spread spectrum can spread the
total electromagnetic emitting energy into a wider
range that significantly degrades the peak energy of
EMI. With spread spectrum, the EMI test can be
passed with smaller size and lower cost filter circuit.
OPERATING MODE
IS31FL3239 can only operate in PWM Mode. The
brightness of each LED can be modulated with
256/1024/4096/65536 steps by PWM registers. For
example, if the data in PWM Register is “0000 0100”,
then the PWM is the fourth step.
Writing new data continuously to the registers can
modulate the brightness of the LEDs to achieve a
breathing effect.
14
IS31FL3239
SHUTDOWN MODE
Shutdown mode can be used as a means of reducing
power consumption. During shutdown mode all
registers retain their data.
Software Shutdown
By setting the SSD bit of the Control Register (00h) to
“0”, the IS31FL3239 will operate in software shutdown
mode. When the IS31FL3239 is in software shutdown,
all current sources are switched off, so the LEDs are
OFF but all registers accessible. Typical current
consume is 0.8μA (VCC=3.6V).
Hardware Shutdown
The chip enters hardware shutdown when the SDB pin
is pulled low. All analog circuits are disabled during
hardware shutdown, typical the current consumption is
0.8μA (VCC=3.6V).
The chip releases hardware shutdown when the SDB
pin is pulled high. The rising edge of SDB pin will reset
the I2C module, but the register information retains.
During hardware shutdown the registers are
accessible.
If the VCC supply drops below 1.75V but remains
above 0.1V during SDB pulled low, please re-initialize
all Function Registers before SDB pulled high.
LAYOUT
The IS31FL3239 consumes lots of power so good PCB
layout will help improve the reliability of the chip.
Please consider below factors when layout the PCB.
Power Supply Lines
When designing the PCB layout pattern, the first step
should consider about the supply line and GND
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Rev. A, 07/29/2019
connection, especially those traces with high current,
also the digital and analog blocks’ supply line and
GND should be separated to avoid the noise from
digital block affect the analog block.
At least one 0.1μF capacitor, if possible with a 1μF
capacitor is recommended to connected to the ground
at power supply pin of the chip, and it needs to close to
the chip and the ground net of the capacitor should be
well connected to the GND plane.
RISET
RISET should be close to the chip and the ground side
should well connect to the GND plane.
Thermal Consideration
The over temperature of the chip may result in
deterioration of the properties of the chip. The thermal
pad of IS31FL3239 should connect to GND net and
need to use 9 or 16 vias connect to GND copper area,
the GND area should be as large area as possible to
help radiate the heat from the IS31FL3239.
Current Rating Example
For a RISET=3.3kΩ application, the current rating for
each net is as follows:
• VCC pin maximum current is 8mA when VCC=5V, but
the VLED+ net is provide total current of all outputs, its
current can as much as 23mA×24=552mA,
recommend trace width for VCC pin: 0.20mm~0.3mm,
recommend
trace
width
for
VLED+
net:
0.30mm~0.5mm
• Output pins=23mA, recommend trace width is
0.2mm~0.254mm
• All other pins
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