SLG59M1639V

 SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking General Description Pin Configuration VIN2 1 ON2 2 ON1 3 VIN1 4 Designed to operate over a -40°C to 85°C range, the SLG59M1639V is available in a RoHS-compliant, ultra-small 1.6 x 1.0 mm STDFN package. SLG59M1639V The SLG59M1639V is a dual-channel, 45 mΩ pFET load switch designed to switch 1.5 to 5.5 V power rails up to 2 A in each channel. When either channel is enabled, reverse-current protection will quickly open the switch in the event of a reverse-voltage condition is detected (a VOUT > VIN + 50 mV condition opens the switch). In the event that the channel’s VIN voltage is too low, the load switch also contains an internal VIN(UVLO) threshold monitor to keep or to turn the switch OFF. Each load switch is independently controlled via its own low-voltage compatible CMOS input. 8 VOUT2 7 GND 6 NC 5 VOUT1 8-pin STDFN (Top View) Features • Integrated 2-Channel pFET Load Switch • 2 A Maximum Continuous Switch Current per Channel • Low Typical RDSON: • 45 mΩ at VIN = 5 V • 60 mΩ at VIN = 2.5 V • 80 mΩ at VIN = 1.5 V • Operating Voltage: 1.5 V to 5.5 V • Reverse-current/voltage Protection • Low-voltage CMOS Logic Compatible Switch Control • Operating temperature range: -40°C to 85°C • Pb-Free / Halogen-Free / RoHS compliant packaging Applications • Power-Rail Switching: • Notebook/Laptop/Tablet PCs • Smartphones/Wireless Handsets • High-definition Digital Cameras • Set-top Boxes • Point of Sales Pins • GPS Navigation Devices Block Diagram VIN1 ILOAD1 ILOAD2 Reverse Voltage Protection Reverse Voltage Protection VOUT1 VIN2 VOUT2 Logic Control Logic Control SW Closed SW Closed ON1 ON2 CMOS Input CMOS Input SW Open SW Open GND Datasheet CFR0011-120-01 Revision 1.08 Page 1 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Pin Description Pin # Pin Name Type 1 VIN2 MOSFET 2 ON2 Input ON2 turns Channel 2 MOSFET ON and is a low logic-level CMOS input with ON_VIL < 0.3 V and ON_VIH > 1 V. As the ON2 input circuit does not have an internal pull-down resistor, connect ON2 pin directly to a GPIO controller – do not allow this pin to be open circuited. 3 ON1 Input ON1 turns Channel 1 MOSFET ON and is a low-logic level CMOS input with ON_VIL < 0.3 V and ON_VIH > 1 V. As the ON1 input circuit does not have an internal pull-down resistor, connect ON1 pin directly to a GPIO controller – do not allow this pin to be open circuited. 4 VIN1 MOSFET Input and source terminal of MOSFET #1. Bypass the VIN1 pin to GND with a 1 µF (or larger), low-ESR capacitor. 5 VOUT1 MOSFET Output and drain terminal of MOSFET #1. 6 NC 7 GND GND 8 VOUT2 MOSFET Pin Description Input and source terminal of MOSFET #2. Bypass the VIN2 pin to GND with a 1 µF (or larger), low-ESR capacitor. No Connect No connection. Do not make connection to any other pin - leave Pin 6 as an open circuit. Ground connection. Connect this pin to system analog or power ground plane. Output and drain terminal of MOSFET #2. Ordering Information Part Number Type Production Flow SLG59M1639V STDFN Industrial, -40 °C to 85 °C SLG59M1639VTR STDFN (Tape and Reel) Industrial, -40 °C to 85 °C Datasheet CFR0011-120-01 Revision 1.08 Page 2 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Absolute Maximum Ratings Parameter VIN[1,2] TS Description Conditions Load Switch Input Voltage Min. Typ. Max. Unit -0.3 -- 6 V -65 -- 150 °C ESDHBM Storage Temperature ESD Protection Human Body Model 2000 -- -- V ESDCDM ESD Protection Charged Device Model 1000 -- -- V MSL Moisture Sensitivity Level θJA Thermal Resistance TJ,MAX Maximum Junction Temperature MOSFET IDSCONT Continuous Current from VIN to VOUT MOSFET IDSPK Peak Current from Drain to Source 1 1.0 x 1.6 mm 8L STDFN -- 82 -- °C/W -- 150 -- °C Each channel, TJ< 150°C -- -- 2 A Maximum pulsed switch current, pulse width < 1 ms, 1% duty cycle -- -- 2.5 A Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics 1.5 V ≤ VIN[1,2] ≤ 5.5 V; CIN = 1 µF, TA =-40 °C to 85 °C, unless otherwise noted. Typical values are at TA = 25°C (unless otherwise stated) Parameter VIN[1,2] VIN(UVLO) Description VIN Undervoltage Lockout Threshold IIN Quiescent Supply Current, Both Channels IIN(OFF) OFF Mode Supply Current, Both Channels RDSON ON Resistance VREVERSE Reverse-current Voltage Threshold IREVERSE Reverse-current Leakage Current after Reverse Current Event VON[1,2] Conditions Min. Typ. Max. Unit 1.5 -- 5.5 V VIN ↑, VON = 0 V, RLOAD = 10 Ω -- -- 1.2 V VIN ↓, VON = 0 V, RLOAD = 10 Ω 0.5 -- -- V VIN = 5.25V, VON = HIGH, no Load -- 3.5 5.3 µA VIN = 1.5 V, VON = HIGH, no Load -- 2.5 4 µA VIN = 5.25 V, VON = LOW, RLOAD = 1 MΩ -- 1 1.5 µA VIN = 1.5 V, VON = LOW, RLOAD = 1 MΩ -- 0.4 1.0 µA TA = 25°C, VIN = 5.0 V, IDS = -200 mA -- 45 55 mΩ TA = 25°C, VIN = 2.5 V, IDS = -200 mA -- 60 72 mΩ TA = 25°C, VIN = 1.5 V, IDS = -200 mA -- 80 96 mΩ -- 50 -- mV -- 0.6 -- µA 0 -- VIN[1,2] V -- -- 1 µA -- VIN[1,2] V Load Switch Input Voltage VOUT – VIN > VREVERSE; TA = 25°C; ON1, ON2 = GND ON[1,2] Pin Voltage Range ION(Leakage) ON[1,2] Pin Leakage Current 1.4 V ≤ VON ≤ VIN or VON = GND ON_VIH ON[1,2] Pin Input High Voltage 1 ON_VIL ON[1,2] Pin Input Low Voltage -0.3 0 0.3 V ONHYS ON[1,2] Hysteresis -- 60 -- mV Datasheet CFR0011-120-01 Revision 1.08 Page 3 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Electrical Characteristics (continued) 1.5 V ≤ VIN[1,2] ≤ 5.5 V; CIN = 1 µF, TA =-40 °C to 85 °C, unless otherwise noted. Typical values are at TA = 25°C (unless otherwise stated) Parameter TREV TREARM TON_Delay TVOUTx(R) TVOUTx(F) TOFF_Delay Description Conditions Reverse-current Detect Response Delay Min. Typ. Max. Unit VIN = 5 V -- 10 -- µs -- 0.6 -- ms 50% ONx to 50% VOUTx ↑; TA = 25°C, VINx = 5 V; RLOAD = 10 Ω , CLOAD = 0.1 µF -- 1.1 1.65 ms 50% ONx to 50% VOUTx ↑; TA = 25°C, VINx = 1.5 V; RLOAD = 10 Ω, CLOAD = 0.1 µF -- 0.8 1.2 ms 10% to 90% VOUTx ↑; TA = 25°C, VINx = 5 V; RLOAD = 10 Ω, CLOAD = 0.1 µF -- 1.0 1.4 ms 10% to 90% VOUTx ↑; TA = 25°C, VINx = 1.5 V; RLOAD = 10 Ω, CLOAD = 0.1 µF -- 0.5 0.71 ms 90% to 10% VOUTx ↓; TA = 25°C, VINx = 5 V; RLOAD = 10 Ω, CLOAD = 0.1 µF -- 2.3 3 µs 90% to 10% VOUTx ↓; TA = 25°C, VINx = 1.5 V; RLOAD = 10 Ω, CLOAD = 0.1 µF -- 2.3 3 µs 50% ONx to 50% VOUTx ↓; TA = 25°C, VINx = 5 V; RLOAD = 10 Ω, CLOAD = 0.1 µF -- 3.1 4.1 µs 50% ONx to 50% VOUTx ↓; TA = 25°C, VINx = 1.5 V; RLOAD = 10 Ω, CLOAD = 0.1 µF -- 5 6.5 µs Reverse Detect Rearm Time ON[1,2] Delay Time VOUT[1,2] Rise Time VOUT[1,2] Fall Time OFF Delay Time TON_Delay, VS(SR), and TTotal_ON Timing Details ON[1,2] 50% ON 50% ON TVOUT(R) 90% VOUT VOUT[1,2] 50% VOUT(R) TON_Delay 10% VOUT 90% VOUT TOFF_Delay 50% VOUT(F) 10% VOUT TVOUT(F) Datasheet CFR0011-120-01 Revision 1.08 Page 4 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Typical Performance Characteristics RDSON vs. VIN[1,2] and Temperature RDSON vs.Temperature and VIN[1,2] Datasheet CFR0011-120-01 Revision 1.08 Page 5 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking VIN[1,2] Inrush Current Details When either channel of the SLG59M1639V is enabled with ON[1,2] ↑, the load switch closes to charge the VOUT[1,2] output capacitor to VIN[1,2] . The charging current drawn from VIN[1,2] is commonly referred to as “VIN inrush current” and can cause the input power source to collapse if the VIN inrush current is too high. Since the VOUT[1,2] rise time of the SLG59M1639V is fixed, VIN[1,2] inrush current is then a function of the output capacitance at VOUT[1,2]. The expression relating VIN[1,2] inrush current, the SLG59M1639V VOUT[1,2] rise time, and CLOAD[1,2] is: VIN[1,2] Inrush Current = CLOAD[1,2] x ΔVOUT[1,2] VOUT[1,2] Rise Time where in this expression Δ VOUT[1,2] is equivalent to VIN[1,2] if the initial SLG59M1639V’s output voltages are zero. In the table below are examples of VIN[1,2] inrush currents assuming zero initial charge on CLOAD[1,2] as a function of VIN[1,2]. VIN[1,2] VOUT[1,2] Rise Time CLOAD[1,2] Inrush Current 1.5 V 0.5 µs 0.1 µF 0.3 mA 5V 1 µs 0.1 µF 0.5 mA Since the relationship is linear and If CLOAD[1,2] were increased to 1 µF, then the VIN[1,2] inrush currents would be 10x higher in either example. If a large CLOAD[1,2] capacitor is required in the application and depending upon the strength of the input power source, it may very well be necessary to increase the CIN-to-CLOAD ratio to minimize VIN[1,2] droop during turn-on. For other VOUT[1,2] rise time options, please contact Renesas for additional information. Power Dissipation The junction temperature of the SLG59M1639V depends on factors such as board layout, ambient temperature, external air flow over the package, load current, and the RDSON-generated voltage drop across each power MOSFET. While the primary contributor to the increase in the junction temperature of the SLG59M1639V is the power dissipation of its power MOSFETs, its power dissipation and the junction temperature in nominal operating mode can be calculated using the following equations: PDTOTAL = (RDSON1 x IDS12) + (RDSON2 x IDS22) where: PDTOTAL = Total package power dissipation, in Watts (W) RDSON[1,2] = Channel 1 and Channel 2 Power MOSFET ON resistance, in Ohms (Ω), respectively IDS[1,2] = Channel 1 and Channel 2 Output current, in Amps (A), respectively and TJ= PDTOTAL x θJA + TA where: TJ = Die junction temperature, in Celsius degrees (°C) θJA = Package thermal resistance, in Celsius degrees per Watt (°C/W) – highly dependent on pcb layout TA = Ambient temperature, in Celsius degrees (°C) Datasheet CFR0011-120-01 Revision 1.08 Page 6 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Power Dissipation (continued) In nominal operating mode, the SLG59M1639V’s power dissipation can also be calculated by taking into account the voltage drop across each switch (VINx-VOUTx) and the magnitude of that channel’s output current (IOUTx): PDTOTAL = [(VIN1-VOUT1) x IDS1] + [(VIN2-VOUT2) x IDS2] or PDTOTAL = [(VIN1 – (RLOAD1 x IDS1)) x IDS1] + [(VIN2 – (RLOAD2 x IDS2)) x IDS2] where: PDTOTAL = Total package power dissipation, in Watts (W) VIN[1,2] = Channel 1 and Channel 2 Input Voltage, in Volts (V), respectively RLOAD[1,2] = Channel 1 and Channel 2 Output Load Resistance, in Ohms (Ω), respectively IDS[1,2] = Channel 1 and Channel 2 output current, in Amps (A), respectively VOUT[1,2] = Channel 1 and Channel 2 output voltage, or RLOAD[1,2] x IDS[1,2] , respectively Power Dissipation Derating Curve Maximum Power Dissipation (W) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Ambient Temperature °(C) Note: Each VIN, VOUT = 1 in2 1.2 oz. copper on FR4 Datasheet CFR0011-120-01 Revision 1.08 Page 7 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Layout Guidelines: 1.Since the VIN[1,2] and VOUT[1,2] pins dissipate most of the heat generated during high-load current operation, it is highly recommended to make power traces as short, direct, and wide as possible. A good practice is to make power traces with an absolute minimum widths of 15 mils (0.381 mm) per Ampere. A representative layout, shown in Figure 1, illustrates proper techniques for heat to transfer as efficiently as possible out of the device; 2.To minimize the effects of parasitic trace inductance on normal operation, it is recommended to connect input CIN and output CLOAD low-ESR capacitors as close as possible to the SLG59M1639V's VIN[1,2] and VOUT[1,2] pins; 3.The GND pin should be connected to system analog or power ground plane. 4. 2 oz. copper is recommended for high current operation. SLG59M1639V Evaluation Board: А GreenFET Evaluation Board for SLG59M1639V is designed according to the statements above and is illustrated on Figure 1. Please note that evaluation board has D_Sense and S_Sense pads. They cannot carry high currents and dedicated only for RDSON evaluation. Please solder your SLG59M1639V here Figure 1. SLG59M1639V Evaluation Board Datasheet CFR0011-120-01 Revision 1.08 Page 8 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking 1 1 V DD C1 1 2 3 4 5 D ual 10 9 8 7 6 V D D C A P2 GN D C A P1 ON 1 S2 ON 2 S1 D1 D2 C A P Ar ra y 1 1 3 5 7 9 S S e n se 1 . 1 1 C2 D Se n s e1 . 1 1 2 4 6 8 10 U1 1 2 3 4 5 6 7 D Se n s e1 . 2 1 R 2 _ Array 1 3 5 7 9 2 4 6 8 10 D1 D1 ON 1 V DD ON 2 D2 D2 S1 S1 C AP 1 GN D C AP 2 S2 S2 14 13 12 11 10 9 8 C A P Ar ra y 2 1 3 5 7 9 S Se n s e 1 .2 1 C3 2 4 6 8 10 C5 D Se n s e2 . 2 C7 RL1 RL1 1 ON 2 S Se n s e 2. 2 1 U2 3 2 1 1 2 3 4 D Se n s e2 . 1 1 V IN 2 ON 2 ON 1 V IN 1 V OU T2 GN D NC V OU T1 8 7 6 5 S Sen s e2 .1 1 RL2 C4 RL2 C6 D1 3 2 1 3 2 1 D1 S1 S1 S2 1 1 1 1 1 1 D2 S2 1 U3 1 2 3 4 5 D S e ns e3 VO1 ON 1 ON 2 VO2 VI N GN D V O4 ON 4 ON 3 V O3 S Se n s e3. 1 10 9 8 7 6 1 S Se n s e3. 2 1 S Se n s e3. 3 1 1 Qu a d 1 2 3 4 5 V_I N GN D ON 1 ON 2 ON 3 V4 _ OU T V3 _ OU T V2 _ OU T V1 _ OU T ON 4 10 9 8 7 6 VO3 S Se n s e3. 4 1 ON 3 D2 1 ON 1 2 4 6 8 10 1 1 3 5 7 9 1 R 1 _ Array V O4 RL3 C8 RL4 C9 ON 4 3 2 1 Figure 2. SLG59M1639V Evaluation Board Connection Circuit Datasheet CFR0011-120-01 Revision 1.08 Page 9 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Basic Test Setup and Connections Figure 3. SLG59M1639V Evaluation Board Connection Circuit EVB Configuration 1. Connect oscilloscope probes to D1/VIN, D2, S1/VO1, S2/VO2, ON1, ON2 etc.; 2. Turn on Power Supply 1 and set desired VIN1 from 1.5 V…5.5 V range; 3. Turn on Power Supply 2 and set desired VIN2 from 1.5 V…5.5 V range; 4. Toggle the ON[1,2] signal High or Low to observe SLG59M1639V operation. Datasheet CFR0011-120-01 Revision 1.08 Page 10 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking SLG59M1639V Layout Suggestion Note: All dimensions shown in micrometers (µm) Package Top Marking System Definition ABC Serial Number Pin 1 Identifier ABC - 3 alphanumeric Part Serial Number where A, B, or C can be A-Z and 0-9 Datasheet CFR0011-120-01 Revision 1.08 Page 11 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Package Drawing and Dimensions 8 Lead STDFN Package 1.0 x 1.6 mm Datasheet CFR0011-120-01 Revision 1.08 Page 12 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Tape and Reel Specifications Max Units Leader (min) Nominal Reel & Package # of Package Size Hub Size Length Type Pins per Reel per Box Pockets [mm] [mm] [mm] STDFN 8L 1x1.6mm 0.4P FCD Green 8 1.0 x 1.6 x 0.55 3,000 3,000 178 / 60 100 400 Trailer (min) Pockets Length [mm] Tape Width [mm] 100 400 8 Part Pitch [mm] 4 Carrier Tape Drawing and Dimensions Package Type Pocket BTM Pocket BTM Pocket Length Width Depth STDFN 8L 1x1.6mm 0.4P FCD Green Index Hole Pitch Pocket Pitch Index Hole to Index Hole Index Hole to Tape Pocket CenDiameter Tape Edge Width ter A0 B0 K0 P0 P1 D0 E F W 1.12 1.72 0.7 4 4 1.55 1.75 3.5 8 Recommended Reflow Soldering Profile Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 0.88 mm3 (nominal). More information can be found at www.jedec.org. Datasheet CFR0011-120-01 Revision 1.08 Page 13 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation  SLG59M1639V Ultra-small 2-Channel 45 mΩ/2 A Load Switch with Reverse-Current Blocking Revision History Date Version Change 2/4/2022 1.08 Updated Company name and logo Fixed typos Added Layout Guidelines 9/17/2018 1.07 Updated style and formatting Updated Charts 8/29/2017 1.06 Updated Inrush Current Details Fixed typos 4/13/2017 1.05 Fixed Reverse Voltage Detection equation 4/18/2016 1.04 Updated Electrical Characteristics 4/1/2016 1.03 Fixed typo in Pin Configuration 2/17/2016 1.02 Updated POD and Landing Pattern 2/9/2016 1.01 Updated Electrical Characteristics 2/3/2016 1.00 Production Release Datasheet CFR0011-120-01 Revision 1.08 Page 14 of 14 4-Feb-2022 ©2022 Renesas Electronics Corporation IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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