TSM1N45CT B0G

TSM1N45 Taiwan Semiconductor N-Channel Power MOSFET 450V, 0.5A, 4.25Ω FEATURES KEY PERFORMANCE PARAMETERS ● Low gate charge @typical 6.5nC PARAMETER VALUE UNIT VDS 450 V RDS(on) (max) 4.25 Ω Qg 6.5 nC ● Low Crss @ typical 6.5pF ● Avalanche energy specified ● Improved dV/dt capability ● Pb-free plating ● Compliant to RoHS Directive 2011/65/EU and in accordance to WEE 2002/96/EC ● Halogen-free according to IEC 61249-2-21 d definition de APPLICATION ● Power Supply en ● Lighting TO-92 e co mm SOT-223 tR Notes: MSL 3 (Moisture Sensitivity Level) per J-STD-020 ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) SYMBOL Limit UNIT Drain-Source Voltage VDS 450 V Gate-Source Voltage VGS ±30 V ID 0.5 A IDM 4 A No PARAMETER Continuous Drain Current Pulsed Drain Current (Note 1) TC = 25°C (Note 2) Total Power Dissipation @ TC = 25°C TO-92 PDTOT SOT-223 2 15 W Single Pulsed Avalanche Energy (Note 3) EAS 108 mJ Single Pulsed Avalanche Current (Note 3) IAS 1.6 A Repetitive Avalanche Energy (Note 3) EAR 0.25 mJ Repetitive Avalanche Current (Note 3) IAR 0.5 A TJ, TSTG - 55 to +150 °C Operating Junction and Storage Temperature Range Document Number: DS_P0000035 1 Version: E15 TSM1N45 Taiwan Semiconductor THERMAL PERFORMANCE PARAMETER SYMBOL Limit Junction to Lead Thermal Resistance TO-92 RӨJL 50 Junction to Case Thermal Resistance SOT-223 RӨJC 8.5 TO-92 Junction to Ambient Thermal Resistance UNIT °C/W 140 RӨJA SOT-223 60 Notes: RӨJA is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined at the solder mounting surface of the drain pins. R ӨJA is guaranteed by design while RӨCA is determined by the user’s board No tR e co mm en de d design. RӨJA shown below for single device operation on FR-4 PCB with minimum recommended footprint in still air. Document Number: DS_P0000035 2 Version: E15 TSM1N45 Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (TA = 25°C unless otherwise noted) PARAMETER Static CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 4) Drain-Source Breakdown Voltage VGS = 0V, ID = 250µA BVDSS 450 -- -- V Gate Threshold Voltage VDS = VGS, ID = 250µA VGS(TH) 2.3 -- 4.25 V Gate Body Leakage VGS = ±30V, VDS = 0V IGSS -- -- ±100 nA Zero Gate Voltage Drain Current VDS = 450V, VGS = 0V IDSS -- -- 10 µA Drain-Source On-State Resistance VGS = 10V, ID = 0.25A RDS(on) -- 3.7 4.25 Ω Qg -- 6.5 10 Qgs -- 1.3 -- Qgd -- 3.2 -- Ciss -- 235 -- Coss -- 29 -- Total Gate Charge VDS = 360V, ID = 0.5A, Gate-Source Charge VGS = 10V d Gate-Drain Charge Input Capacitance VDS = 25V, VGS = 0V, Reverse Transfer Capacitance Crss (Note 6) mm Switching f = 1.0MHz en Output Capacitance de Dynamic (Note 5) Turn-On Delay Time nC pF 6.5 td(on) -- 14.7 -- tr -- 32.8 -- td(off) -- 25.2 -- tf -- 23.7 -- Maximum Continuous Drain-Source Diode Forward Current IS -- -- 0.5 A Maximum Pulsed Drain-Source Diode Forward Current ISM -- -- 4 A Forward On Voltage VSD -- -- 1.4 V VDD = 225V, Turn-On Rise Time RGEN = 25Ω, Turn-Off Delay Time e co ID = 0.5A, VGS = 10V, Turn-Off Fall Time tR IS = 0.5A, VGS = 0V No Source-Drain Diode (Note 4) ns Reverse Recovery Time VGS = 0V, IS = 1A trr -- 110 -- ns Reverse Recovery Charge dIF/dt = 100A/μs Qrr -- 0.35 -- μC Notes: 1. Current limited by package. 2. Pulse width limited by the maximum junction temperature. 3. L = 75mH, IAS = 1.6A, VDD = 50V, RG = 25Ω, Starting TJ = 25°C 4. Pulse test: PW ≤ 300µs, duty cycle ≤ 2%. 5. For DESIGN AID ONLY, not subject to production testing. 6. Switching time is essentially independent of operating temperature. Document Number: DS_P0000035 3 Version: E15 TSM1N45 Taiwan Semiconductor ORDERING INFORMATION PACKAGE PACKING TSM1N45CT B0G TO-92 1,000pcs / Bulk TSM1N45CT A3G TO-92 2,000pcs / Ammo TSM1N45CW RPG SOT-223 2,500pcs / 13” Reel No tR e co mm en de d PART NO. Document Number: DS_P0000035 4 Version: E15 TSM1N45 Taiwan Semiconductor CHARACTERISTICS CURVES (TC = 25°C unless otherwise noted) Transfer Characteristics de VGS, Gate to Source Voltage (V) en VDS, Drain to Source Voltage (V) Gate-Source Voltage vs. Gate Charge No tR e co mm VGS, Gate to Source Voltage (V) On-Resistance vs. Drain Current RDS(on), On-Resistance ( Ω) d ID, Continuous Drain Current (A) ID, Continuous Drain Current (A) Output Characteristics Qg, Gate Charge (nC) ID, Continuous Drain Current (A) Source-Drain Diode Forward Current vs. Voltage IS, Body Diode Forward Current (A) RDS(on), Drain-Source On-Resistance (Normalized) On-Resistance vs. Junction Temperature VSD, Body Diode Forward Voltage (V) TJ, Junction Temperature (°C) Continuous Drain Current (A) Document Number: DS_P0000035 5 Version: E15 TSM1N45 Taiwan Semiconductor CHARACTERISTICS CURVES (TC = 25°C unless otherwise noted) Threshold Voltage Maximum Safe Operating Area d No tR e co mm ID, Continuous Drain Current (A) TJ, Junction Temperature (°C) en VGS, Gate to Source Voltage (V) de RDS(on), On-Resistance ( Ω) (Normalized) Normalized Gate Threshold Voltage (V) On-Resistance vs. Gate-Source Voltage VDS, Drain to Source Voltage (V) Thermal Transient Impedance, Junction-to-Ambient RDS(on), On-Resistance ( Ω) 10 1 0.1 0.01 Document Number: DS_P0000035 Square Wave Pulse Duration (sec) 6 Version: E15 TSM1N45 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) tR MARKING DIAGRAM e co mm en de d TO-92 No Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code Document Number: DS_P0000035 7 Version: E15 TSM1N45 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) mm en de d TO-92 e co MARKING DIAGRAM No tR Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code Document Number: DS_P0000035 8 Version: E15 TSM1N45 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) No tR e co SUGGESTED PAD LAYOUT mm en de d SOT-223 MARKING DIAGRAM Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code Document Number: DS_P0000035 9 Version: E15 TSM1N45 No tR e co mm en de d Taiwan Semiconductor Notice Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC’s terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such improper use or sale. Document Number: DS_P0000035 10 Version: E15