GA50SICP12-227

GA50SICP12-227 Silicon Carbide Junction Transistor/Schottky Diode Co-Pack Features VDS RDS(ON) ID (@ 25°C) ID (@ 115°C) hFE (@ 25°C) = = = = = 1200 V 20 m 80 A 50 A 100 Package 175 °C Maximum Operating Temperature Gate Oxide Free SiC Switch Optional Gate Return Pin Exceptional Safe Operating Area Integrated SiC Schottky Rectifier Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of RDS,ON Suitable for Connecting an Anti-parallel Diode D S GR D G G GR Isolated Baseplate SOT-227 Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Reduced cooling requirements Reduced system size S Pin D - Drain Pin S - Source Pin GR - Gate Return Pin G - Gate Please note: The Source and Gate Return pins are not exchangeable. Their exchange might lead to malfunction. Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Table of Contents Section I: Absolute Maximum Ratings .......................................................................................................... 1 Section II: Static Electrical Characteristics................................................................................................... 2 Section III: Dynamic Electrical Characteristics ............................................................................................ 2 Section IV: Figures .......................................................................................................................................... 4 Section V: Driving the GA50SICP12-227 ....................................................................................................... 8 Section VI: Package Dimensions ................................................................................................................. 12 Section VII: SPICE Model Parameters ......................................................................................................... 13 Section I: Absolute Maximum Ratings Parameter Symbol Conditions Value Unit V DS ID ID IG IGR VGS = 0 V TC = 25°C TC = 115°C 1200 80 50 3.5 3.5 ID,max = 50 @ VDS DSmax V A A A A >20 µs 30 25 265 / 106 -55 to 175 V V W °C Notes SiC Junction Transistor Drain – Source Voltage Continuous Drain Current Continuous Drain Current Continuous Gate Current Continuous Gate Return Current Turn-Off Safe Operating Area Short Circuit Safe Operating Area Reverse Gate – Source Voltage Reverse Drain – Source Voltage Power Dissipation Operating and storage temperature Dec 2015 RBSOA SCSOA V SG VSD Ptot Tstg TVJ TVJ = 175 oC, Clamped Inductive Load = 175 oC, IG = 1 A, VDS = 800 V, Non Repetitive TC = 25 °C / 115 °C, tp > 100 ms Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ A Fig. 17 Fig. 17 Fig. 19 Fig. 16 Pg 1 of 12 GA50SICP12-227 Parameter Symbol Conditions Value Unit V A A Notes Free-Wheeling SiC Diode Repetitive peak reverse voltage Continuous forward current RMS forward current Surge non-repetitive forward current, Half Sine Wave Non-repetitive peak forward current 2 VRRM IF IF(RMS) i dt TC = 25 °C, tP = 10 ms TC = 115 °C, tP = 10 ms 1200 50 87 350 313 1625 450 300 RthJC RthJC SiC Junction Transistor SiC Diode 0.57 0.53 115 °C TC 5 °C TC = 25 °C, tP = 10 ms TC = 115 °C, tP = 10 ms IFSM IF,max TC = 25 °C, tP = 10 µs 2 I t value TC A A A2s Thermal Characteristics Thermal resistance, junction - case Thermal resistance, junction - case °C/W °C/W Fig. 20 Fig. 21 Unit Notes Section II: Static Electrical Characteristics Parameter Symbol Conditions Drain – Source On Resistance RDS(ON) ID = 50 A, Tj = 25 °C ID = 50 A, Tj = 150 °C ID = 50 A, Tj = 175 °C Gate – Source Saturation Voltage VGS,SAT ID = 50 A, ID/IG = 40, Tj = 25 °C ID = 50 A, ID/IG = 30, Tj = 175 °C DC Current Gain hFE VDS = 8 V, ID = 50 A, Tj = 25 °C VDS = 8 V, ID = 50 A, Tj = 125 °C VDS = 8 V, ID = 50 A, Tj = 175 °C FWD forward voltage VF IF = 50 A, Tj = 25 °C IF = 50 A, Tj = 175 °C Min. Value Typical Max. A: On State 20 36 42 3.42 3.23 100 65 58 1.4 2.1 Fig. 5 1.8 3.0 V Fig. 7 – Fig. 4 V B: Off State Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, Tj = 25 °C VDS = 1200 V, VGS = 0 V, Tj = 150 °C VDS = 1200 V, VGS = 0 V, Tj = 175 °C Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C 100 200 500 20 A Fig. 8 nA Section III: Dynamic Electrical Characteristics Parameter Symbol Conditions Ciss VGS = 0 V, VDS = 800 V, f = 1 MHz Crss/Coss VDS = 1 V, f = 1 MHz VDS = 400 V, f = 1 MHz VDS = 800 V, f = 1 MHz Min. Value Typical Max. Unit Notes pF Fig. 9 pF Fig. 9 A: Capacitance and Gate Charge Input Capacitance Reverse Transfer/Output Capacitance Total Output Capacitance Charge Qoss Output Capacitance Stored Energy Effective Output Capacitance, time related Effective Output Capacitance, energy related Gate-Source Charge Gate-Drain Charge Gate Charge - Total E OSS Dec 2015 Coss,tr VR = 400 V VR = 800 V VGS = 0 V, VDS = 800 V, f = 1 MHz ID = constant, VGS = 0 V, VDS = 0…800 V 7770 3370 335 250 230 345 100 nC µJ 430 pF Coss,er VGS = 0 V, VDS = 0…800 V 315 pF QGS QGD QG VGS = -5…3 V VGS = 0 V, VDS = 0…800 V 65 345 410 nC nC nC Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Fig. 10 Pg 2 of 12 GA50SICP12-227 Parameter B: SJT Switching Conditions RG(INT-ON) td(on) tf td(off) tr td(on) tf td(off) tr Eon Eoff E tot Eon Eoff E tot VGS > 2.5 V, V DS = 0 V, Tj = 175 ºC Min. Value Typical Max. Unit Notes 1 Internal Gate Resistance – ON Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy 1 Symbol Tj = 25 ºC, V DS = 800 V, ID = 50 A, Resistive Load Refer to Section V for additional driving information. Tj = 175 ºC, VDS = 800 V, ID = 50 A, Resistive Load Tj = 25 ºC, V DS = 800 V, ID = 50 A, Inductive Load Refer to Section V. Tj = 175 ºC, VDS = 800 V, ID = 50 A, Inductive Load 50 10 35 35 20 10 35 65 15 1450 400 1850 1410 400 1810 m ns ns ns ns ns ns ns ns µJ µJ µJ µJ µJ µJ Fig. 11, 13 Fig. 12, 14 Fig. 11 Fig. 12 Fig. 11, 13 Fig. 12, 14 Fig. 11 Fig. 12 – All times are relative to the Drain-Source Voltage VDS Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 3 of 12 GA50SICP12-227 Section IV: Figures A: Static Characteristics Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 150 °C Figure 3: Typical Output Characteristics at 175 °C Figure 4: DC Current Gain vs. Drain Current Figure 5: On-Resistance vs. Gate Current Figure 6: Normalized On-Resistance vs. Temperature Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 4 of 12 GA50SICP12-227 Figure 7: Typical Gate – Source Saturation Voltage Figure 8: Typical Blocking Characteristics B: Dynamic Characteristics Figure 9: Input, Output, and Reverse Transfer Capacitance Figure 10: Energy Stored in Output Capacitance Figure 11: Typical Switching Times and Turn On Energy Losses vs. Temperature Figure 12: Typical Switching Times and Turn Off Energy Losses vs. Temperature Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 5 of 12 GA50SICP12-227 Figure 13: Typical Switching Times and Turn On Energy Losses vs. Drain Current Figure 14: Typical Switching Times and Turn Off Energy Losses vs. Drain Current C: Current and Power Derating 2 Figure 15: Typical Hard Switched Device Power Loss vs. Switching Frequency 2 Figure 16: Power Derating Curve Figure 17: Drain Current Derating vs. Temperature Figure 18: Forward Bias Safe Operating Area at T c= 25 C o – Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology. Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 6 of 12 GA50SICP12-227 Figure 19: Turn-Off Safe Operating Area Figure 20: SJT Transient Thermal Impedance Figure 21: FWD Transient Thermal Impedance Figure 22: Typical FWD Forward Characteristics Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 7 of 12 GA50SICP12-227 Section V: Driving the GA50SICP12-227 Drive Topology TTL Logic Constant Current High Speed – Boost Capacitor High Speed – Boost Inductor Proportional Pulsed Power Gate Drive Power Consumption High Medium Medium Low Lowest Medium Switching Frequency Low Medium High High High N/A Application Emphasis Availability Wide Temperature Range Wide Temperature Range Fast Switching Ultra Fast Switching Wide Drain Current Range Pulse Power Coming Soon Coming Soon Production Coming Soon Coming Soon Coming Soon A: Static TTL Logic Driving The GA50SICP12-227 may be driven with direct (5 V) TTL logic and current amplification. The amplified current level of the supply must meet or exceed the steady state gate current (I G,steady) required to operate the GA50SICP12-227. Minimum I G,steady is dependent on the anticipated drain current ID through the SJT and the DC current gain h FE, it may be calculated from the following equation. An accurate value of the h FE may be read from Figure 4. An optional resistor RG may be used in series with the gate pin to trim IG,steady, also an optional capacitor CG may be added in parallel with RG to facilitate faster SJT switching if desired, further details on these options are given in the following section. , ( , ) 5V 1.5 D CG TTL Gate Signal RG G IG,steady 5/0V TTL i/p GR S Figure 23: TTL Gate Drive Schematic B: High Speed Driving The SJT is a current controlled transistor which requires a positive gate current for turn-on and to remain in on-state. An idealized gate current waveform for ultra-fast switching of the SJT while maintaining low gate drive losses is shown in Figure 24, it features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current during on-state. Figure 24: An idealized gate current waveform for fast switching of an SJT. An SJT is rapidly switched from its blocking state to on-state when the necessary gate charge, Q G, for turn-on is supplied by a burst of high gate current, IG,on, until the SJT gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. = , 1 + Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 8 of 12 GA50SICP12-227 Ideally, IG,on should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady onstate. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, L s, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V GS,sat (see Figure 7) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. Turn off can be achieved with V GS = 0 V, however a negative gate voltage VGS may be used in order to speed up the turn-off transition. Gate Return Pin The optional gate return (GR) pin allows for a reduction of source path inductive and resistive coupling in the gate driver connection to the GA50SICP12-227. Drain currents through the source pin during transient and steady state operation induce an undesirable source voltage in all power transistors due to unavoidable source pin inductance and resistance. This voltage can negatively affect gate driving performance, however the gate return pin allows for decoupling from these source current path effects which results in faster switching and higher efficiency gate driving. B:1: High Speed, Low Loss Drive with Boost Capacitor, GA15IDDJT22-FR4 The GA50SICP12-227 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in on-state. An evaluation gate drive board (GA15IDDJT22-FR4) utilizing this topology is commercially available low-side driving, its datasheet provides additional details. GA15IDDJT22-FR4 Gate Driver Board CG1 VGL Signal Gate Signal VGH VGL R2 R1 U4 U1 CG2 U2 VEE C9 VEE C10 C2 VEE R3 VGL VCC High +12 V X2 R6 VCC Low RTN G U3 RG2 D1 GR VEE C8 S VGH VCC Low C1 IG RG1 R4 C5 D C7 VGL VCC High RTN +12 V R5 C6 Signal RTN X1 C21 C4 VEE Figure 25: Topology of the GA15IDDJT22-FR4 Two Voltage Source gate driver. The GA15IDDJT22-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective 3 gate resistance of RG = 0.7 /or RG2 under high drain current conditions for safe operation of the GA50SICP12-227. The steady state current supplied to the gate pin of the GA50SICP12-227 with on-board RG = 0.7 shown in Figure 26. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 27. For the GA50SICP12-227, RG must be reduced or shorted for I D 60 A for safe operation with the GA15IDDJT22-FR4. For operation at ID 60 A, RG may be calculated from the following equation, which contains the DC current gain hFE and the gate-source saturation voltage V GS,sat (Figure 7). , Dec 2015 = 4.7 ( , , 1.5 ) 0.1 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 9 of 12 GA50SICP12-227 Figure 26: Typical steady state gate current supplied by the GA15IDDJT22-FR4 board for the GA50SICP12-227 with the on board resistance of 0.7 Figure 27: Maximum gate resistance for safe operation of the GA50SICP12-227 at different drain currents using the GA15IDDJT22-FR4 board. B:2: High Speed, Low Loss Drive with Boost Inductor A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the GA50SICP12-227 at high-speed. It utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses I G,on and IG,off. During operation, inductor L is charged to a specified IG,on current value then made to discharge IL into the SJT gate pin using logic control of S 1, S2, S3, and S4, as shown in Figure 28. After turn on, while the device remains on the necessary steady state gate current IG,steady is supplied from source VCC through RG. Please refer to the article “A current-source concept for information on this driving topology.4 S1 VCC S2 L D VEE S3 G S4 RG VEE GR S Figure 28: Simplified Inductive Pulsed Drive Topology 3 – RG = (1/RG1 +1/RG2)-1. Driver is pre-installed with RG1 = 2.2 4 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013 Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 10 of 12 GA50SICP12-227 C: Proportional Gate Current Driving For applications in which the GA50SICP12-227 will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain current ID feedback to vary the steady state gate current I G,steady supplied to the GA100SICP2-227 C:1: Voltage Controlled Proportional Driver The voltage controlled proportional driver relies on a gate drive IC to detect the GA50SICP12-227 drain-source voltage V DS during on-state to sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A high voltage diode connected between the drain and sense protects the IC from high-voltage when the driver and GA50SICP12-227 are in off-state. A simplified version of this topology is shown in Figure 29, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junctiontransistors/ Gate Signal Signal D HV Diode Sense Proportional Gate Current Driver G Output IG,steady GR S Figure 29: Simplified Voltage Controlled Proportional Driver C:2: Current Controlled Proportional Driver The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback I D of the GA50SICP12-227 during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to I D at a fixed forced current gain which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA50SICP12-227 is initially turned-on using a gate current pulse supplied into an RC drive circuit to allow I D current to begin flowing. This topology allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 30, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/. N2 D G Gate Signal GR N3 N1 S N2 Figure 30: Simplified Current Controlled Proportional Driver Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 11 of 12 GA50SICP12-227 Section VI: Package Dimensions SOT-227 PACKAGE OUTLINE 0.472 (11.9) 0.480 (12.19) 0.372 (9.45) 0.378 (9.60) 1.240 (31.5) 1.255 (31.88) 0.310 (7.87) 0.322 (8.18) 0.108 (2.74) 0.124 (3.15) Ø 0.163 (4.14) 0.169 (4.29) R 3.97 1.049 (26.6) 1.059 (26.90) 0.163 (4.14) 0.169 (4.29) 0.990 (25.1) 1.000 (25.40) 0.495 (12.5) 0.506 (12.85) 0.172 (4.37) 0.186 (4.72) 0.191 (4.85) 0.234 (5.94) 0.080 (2.03) 0.084 (2.13) M4 0.165 (4.19) 0.169 (4.29) 0.164 (4.16) 0.174 (4.42) 0.030 (0.76) 0.033 (0.84) 0.588 (14.9) 0.594 (15.09) 1.186 (30.1) 1.192 (30.28) 1.494 (37.9) 1.504 (38.20) NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS Revision History Date Revision Comments 2015/12/07 1 Updated Electrical Characteristics 2015/03/26 0 Initial release Supersedes Published by GeneSiC Semiconductor, Inc. 43670 Trade Center Place Suite 155 Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 12 of 12 GA50SICP12-227 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/igbt_copack/GA50SICP12-227_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA50SICP12-227. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 2.0 $ * $Date: 07-DEC-2015 $ * * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * * COPYRIGHT (C) 2015 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * * Start of GA50SICP12-227 SPICE Model * .SUBCKT GA50SIPC12 DRAIN GATE SOURCE Q1 DRAIN GATE SOURCE GA50SIPC12_Q D1 SOURCE DRAIN GA50SIPC12_D1 D2 SOURCE DRAIN GA50SIPC12_D2 * .model GA50SIPC12_Q NPN + IS 9.833E-48 ISE 1.073E-26 EG 3.23 + BF 110 BR 0.55 IKF 9000 + NF 1 NE 2 RB 0.95 + RE 0.005 RC 0.014 CJC 2.120E-9 + VJC 2.8346 MJC 0.4846 CJE 6.026E-09 + VJE 3.1791 MJE 0.5295 XTI 3 + XTB -1.5 TRC1 9.0E-03 MFG GeneSiC_Semi + IRB 0.005 RBM 0.073 .MODEL GA50SIPC12_D1 D + IS 1.99E-16 RS 0.015652965 N 1 + IKF 1000 EG 1.2 XTI 3 + TRS1 0.0042 TRS2 1.3E-05 CJO 3.86E-09 + VJ 1.362328465 M 0.48198551 FC 0.5 + TT 1.00E-10 IAVE 50 .MODEL GA50SIPC12_D2 D + IS 1.54E-19 RS 0.1 N 3.941 + EG 3.23 TRS1 -0.004 IKF 19 TT 0 + XTI 0 FC 0.5 .ENDS * End of GA50SICP12-227 SPICE Model Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 1 of 1