PHK31NQ03LT,518

PHK31NQ03LT N-channel TrenchMOS logic level FET Rev. 3 — 11 March 2011 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits „ High efficiency due to low switching and conduction losses „ Suitable for logic level gate drive sources 1.3 Applications „ DC-to-DC converters „ Switched-mode power supplies „ Notebook computers „ Voltage regulators 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 30 ID drain current Tsp = 25 °C; VGS = 10 V; see Figure 1; see Figure 3 - - 30.4 A Ptot total power dissipation Tsp = 25 °C; see Figure 2 - - 6.9 VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 11 - 3.45 4.4 mΩ - 7.7 nC V W Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID = 25 A; VDS = 12 V; see Figure 12; see Figure 13 - PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 S source 2 S source 3 S source 4 G gate 5 D drain 6 D drain 7 D drain 8 D drain Simplified outline 8 Graphic symbol D 5 G 1 4 mbb076 S SOT96-1 (SO8) 3. Ordering information Table 3. Ordering information Type number PHK31NQ03LT PHK31NQ03LT Product data sheet Package Name Description Version SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 2 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 30 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage ID drain current -20 20 V Tsp = 25 °C; VGS = 10 V; see Figure 1; see Figure 3 - 30.4 A Tsp = 100 °C; VGS = 10 V; see Figure 1 - 17.2 A IDM peak drain current Tsp = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 - 121.8 A Ptot total power dissipation Tsp = 25 °C; see Figure 2 - 6.9 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Source-drain diode IS source current Tsp = 25 °C - 5.7 A ISM peak source current Tsp = 25 °C; pulsed; tp ≤ 10 µs - 23.1 A VGS = 10 V; Tj(init) = 25 °C; ID = 35 A; Vsup ≤ 25 V; unclamped; tp = 0.16 ms; RGS = 50 Ω - 120 mJ Avalanche ruggedness non-repetitive drain-source avalanche energy EDS(AL)S 03aa25 120 Ider (%) 03aa17 120 Pder (%) 80 80 40 40 0 0 0 50 100 150 200 0 50 100 150 Tsp (°C) Fig 1. Normalized continuous drain current as a function of mounting base temperature PHK31NQ03LT Product data sheet 200 Tsp (°C) Fig 2. Normalized total power dissipation as a function of solder point temperature All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 3 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET 003aaa690 103 ID (A) Limit RDSon = VDS / ID tp = 10 μ s 102 100 μ s 10 1 ms 10 ms DC 1 100 ms 10-1 10-1 1 10 102 VDS (V) Tsp = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Rth(j-sp) thermal resistance from junction to solder point Conditions Min Typ Max Unit - - 18 K/W 003aaa691 102 Zth(j-sp) (K/W) 10 δ = 0.5 0.2 0.1 1 0.05 0.02 δ= P tp T 10-1 single pulse 10 t tp T -2 Fig 4. 10-5 10-4 10-3 10-2 10-1 1 tp (s) 10 Transient thermal impedance from junction to solder point as a function of pulse duration PHK31NQ03LT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 4 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit - V Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 8; see Figure 9 1.3 1.7 2.15 V ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 8; see Figure 9 0.8 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 8; see Figure 9 - - 2.6 V IDSS drain leakage current VDS = 30 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 30 V; VGS = 0 V; Tj = 150 °C - - 100 µA IGSS gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 11 - 3.45 4.4 mΩ VGS = 10 V; ID = 25 A; Tj = 150 °C; see Figure 10 - 5.85 7.5 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 11 - 4.25 5.6 mΩ f = 1 MHz; VGSS(AC) = 150 mV - 1.2 - Ω ID = 25 A; VDS = 12 V; VGS = 4.5 V; see Figure 12; see Figure 13 - 33 - nC RDSon RG drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge - 13.6 - nC QGS1 pre-threshold gate-source charge - 6.5 - nC QGS2 post-threshold gate-source charge - 7.1 - nC QGD gate-drain charge - 7.7 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 12 V; see Figure 12 - 2.85 - V Ciss input capacitance VDS = 0 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C - 4900 - pF VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 - 4235 - pF - 840 - pF - 370 - pF - 37 - ns - 62 - ns Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time - 54 - ns tf fall time - 26 - ns PHK31NQ03LT Product data sheet VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V; RG(ext) = 5.6 Ω All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 5 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 15 - 0.94 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 30 V - 52 - ns Qr recovered charge IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V - 30 - nC 003aaa692 50 10 4.5 3.4 ID (A) ID (A) 3 40 003aaa693 40 3.2 30 30 2.8 20 2.6 10 20 Tj = 150 °C 25 °C 10 VGS (V) = 2.4 0 0 0 0.2 0.4 0.6 VDS (V) 0.8 0 Tj = 25 °C Fig 5. 1 2 3 4 VGS (V) Tj = 25 °C and 150 °C; VDS > ID x RDSon Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. 003aaa698 104 Ciss C (pF) Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aab272 3 VGS(th) (V) max 2 typ Crss 1.5 min 1 0.5 103 10-1 1 VGS (V) 0 -60 10 0 60 120 180 Tj (°C) VGS = 0 V; f = 1 MHz Fig 7. Input and reverse transfer capacitances as a function of gate-source voltage; typical values PHK31NQ03LT Product data sheet Fig 8. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 6 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET 003aab271 10-1 ID (A) 10-2 a 1.6 min typ max 10-3 1.2 10-4 0.8 10-5 0.4 10-6 0 Fig 9. 003aab467 2 1 2 VGS (V) 3 Sub-threshold drain current as a function of gate-source voltage 0 −60 0 60 120 180 Tj (°C) Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature 003aaa694 20 2.6 RDSon (mΩ) 2.8 VGS (V) = 3 VDS 16 ID 12 VGS(pl) 3.2 8 3.4 VGS(th) 4.5 10 VGS QGS1 4 QGS2 QGS QGD QG(tot) 0 0 10 20 30 40 ID (A) 50 003aaa508 Tj = 25 °C Fig 11. Drain-source on-state resistance as a function of drain current; typical values PHK31NQ03LT Product data sheet Fig 12. Gate charge waveform definitions All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 7 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET 003aaa695 10 003aaa697 104 ID = 25 A Tj = 25 °C VGS (V) 8 Ciss C (pF) 6 VDS = 19 V 12 V 103 4 Coss 2 Crss 102 10-1 0 0 20 40 60 QG (nC) 80 ID = 25 A; VDS = 12 V and 19 V 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig 13. Gate-source voltage as a function of gate charge; typical values Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aaa696 50 IS (A) 40 30 20 150 °C Tj = 25 °C 10 0 0 0.4 0.8 VSD (V) 1.2 Tj = 25 °C and 150 °C; VGS = 0 V Fig 15. Source current as a function of source-drain voltage; typical values PHK31NQ03LT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 8 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET 7. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 16. Package outline SOT96-1 (SO8) PHK31NQ03LT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 9 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PHK31NQ03LT v.3 20110311 Product data sheet - PHK31NQ03LT v.2 - PHK31NQ03LT v.1 Modifications: PHK31NQ03LT v.2 PHK31NQ03LT Product data sheet • Various changes to content. 20101220 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 10 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status [1] [2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective PHK31NQ03LT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 11 of 13 PHK31NQ03LT Nexperia N-channel TrenchMOS logic level FET agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. 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Export might require a prior authorization from national authorities. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the 10. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com PHK31NQ03LT Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 11 March 2011 © Nexperia B.V. 2017. All rights reserved 12 of 13 Nexperia PHK31NQ03LT N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 © Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 11 March 2011