GA20SICP12-247

GA20SICP12-247 Silicon Carbide Junction Transistor/Schottky Diode Co-Pack Features VDS RDS(ON) ID (@ 25°C) ID (@ 145°C) hFE (@ 25°C) = = = = = 1200 V 50 m 45 A 20 A 100 Package 175 °C Maximum Operating Temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Integrated SiC Schottky Rectifier Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of R DS,ON Suitable for Connecting an Anti-parallel Diode D D G G D S S TO-247AB Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Reduced cooling requirements Reduced system size Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Table of Contents Section I: Absolute Maximum Ratings .......................................................................................................... 1 Section II: Static Electrical Characteristics................................................................................................... 2 Section III: Dynamic Electrical Characteristics ............................................................................................ 2 Section IV: Figures .......................................................................................................................................... 4 Section V: Driving the GA20SICP12-247 ....................................................................................................... 7 Section VI: Package Dimensions ................................................................................................................. 11 Section VII: SPICE Model Parameters ......................................................................................................... 12 Section I: Absolute Maximum Ratings Parameter Symbol Conditions Value Unit Notes V DS ID ID IG VGS = 0 V TC = 25°C TC = 145°C 1200 45 20 1.3 ID,max = 20 @ VDS DSmax V A A A Fig. 11 Fig. 11 A Fig. 13 >20 µs 30 25 282 / 56 -55 to 175 V V W °C SiC Junction Transistor Drain – Source Voltage Continuous Drain Current Continuous Drain Current Continuous Gate Current Turn-Off Safe Operating Area RBSOA Short Circuit Safe Operating Area SCSOA Reverse Gate – Source Voltage Reverse Drain – Source Voltage Power Dissipation Operating and storage temperature Jun 2015 V SG VSD Ptot Tstg TVJ TVJ = 175 oC, Clamped Inductive Load = 175 oC, IG = 1 A, VDS = 800 V, Non Repetitive TC = 25 °C / 145 °C, t p > 100 ms Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Fig. 10 Pg 1 of 11 GA20SICP12-247 Parameter Symbol Conditions Value Unit V A A Notes Free-Wheeling SiC Diode Repetitive peak reverse voltage Continuous forward current RMS forward current Surge non-repetitive forward current, Half Sine Wave Non-repetitive peak forward current 2 VRRM IF IF(RMS) i dt TC = 25 °C, tP = 10 ms TC = 115 °C, tP = 10 ms 1200 10 17 65 55 280 21 15 RthJC RthJC SiC Junction Transistor SiC Diode 0.53 0.8 150 °C TC 50 °C TC = 25 °C, tP = 10 ms TC = 150 °C, tP = 10 ms IFSM IF,max TC = 25 °C, tP = 10 µs 2 I t value TC A A A2s Thermal Characteristics Thermal resistance, junction - case Thermal resistance, junction - case °C/W °C/W Section II: Static Electrical Characteristics Parameter Symbol Conditions Drain – Source On Resistance RDS(ON) ID = 20 A, Tj = 25 °C ID = 20 A, Tj = 150 °C ID = 20 A, Tj = 175 °C Gate – Source Saturation Voltage VGS,SAT ID = 20 A, ID/IG = 40, Tj = 25 °C ID = 20 A, ID/IG = 30, Tj = 175 °C DC Current Gain hFE VDS = 8 V, ID = 20 A, Tj = 25 °C VDS = 8 V, ID = 20 A, Tj = 125 °C VDS = 8 V, ID = 20 A, Tj = 175 °C FWD forward voltage VF IF = 10 A, Tj = 25 °C IF = 10 A, Tj = 175 °C Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, Tj = 25 °C VDS = 1200 V, VGS = 0 V, Tj = 125 °C VDS = 1200 V, VGS = 0 V, Tj = 175 °C Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C Min. Value Typical Max. Unit Notes A: On State 50 93 109 3.44 3.24 100 62 56 1.5 2.6 Fig. 4 1.8 3.0 V Fig. 7 – Fig. 5 V B: Off State 5 8 10 20 25 40 50 A Fig. 8 nA Section III: Dynamic Electrical Characteristics Parameter Symbol Conditions Input Capacitance Reverse Transfer Capacitance Ciss Crss VGS = 0 V, VDS = 800 V, f = 1 MHz VDS = 800 V, f = 1 MHz Total FWD capacitance CFWD VR = 1 V, f = 1 MHz, Tj = 25 °C VR = 400 V, f = 1 MHz, Tj = 25 °C VR = 1000 V, f = 1 MHz, Tj = 25 °C Gate-Source Charge Gate-Drain Charge Gate Charge - Total QGS QGD QG Min. Value Typical Max. Unit Notes pF pF Fig. 9 Fig. 9 A: Capacitance and Gate Charge Total FWD capacitive charge Jun 2015 QC,FWD VGS = -5…3 V VGS = 0 V, VDS = 0…800 V dIF IF IF,MAX Tj = 175 °C VR = 400 V VR = 960 V 3091 53 490 45 33 23 77 100 31 52 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ pF nC nC nC nC Pg 2 of 11 GA20SICP12-247 B: Switching1 Internal Gate Resistance – zero bias Internal Gate Resistance – ON Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn On Delay Time Fall Time, VDS Turn Off Delay Time Rise Time, VDS Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy Turn-On Energy Per Pulse Turn-Off Energy Per Pulse Total Switching Energy 1 f = 1 MHz, V = 50 mV, V = 0 V, DS RG(INT-ZERO) V = 0 V, T AC GS j = 175 ºC RG(INT-ON) VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC td(on) Tj = 25 ºC, V DS = 800 V, tf ID = 20 A, Resistive Load Refer to Section V for additional td(off) driving information. tr td(on) tf Tj = 175 ºC, VDS = 800 V, ID = 20 A, Resistive Load td(off) tr Eon Tj = 25 ºC, V DS = 800 V, ID = 20 A, Inductive Load Eoff Refer to Section V. E tot Eon Tj = 175 ºC, VDS = 800 V, Eoff ID = 20 A, Inductive Load E tot 1.7 0.13 12 14 24 12 15 13 30 10 316 40 356 298 28 326 ns ns ns ns ns ns ns ns µJ µJ µJ µJ µJ µJ – All times are relative to the Drain-Source Voltage VDS Jun 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 3 of 11 GA20SICP12-247 Section IV: Figures A: Static Characteristics Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 150 °C Figure 3: Typical Output Characteristics at 175 °C Figure 4: On-Resistance vs. Gate Current Figure 5: DC Current Gain and Normalized On-Resistance vs. Temperature Figure 6: DC Current Gain vs. Drain Current Jun 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 4 of 11 GA20SICP12-247 Figure 7: Typical Gate – Source Saturation Voltage Figure 8: Typical Blocking Characteristics B: Dynamic Characteristics Figure 9: Input and Reverse Transfer Capacitance C: Current and Power Derating Figure 10: Power Derating Curve Jun 2015 Figure 11: Drain Current Derating vs. Temperature Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 5 of 11 GA20SICP12-247 Figure 12: Forward Bias Safe Operating Area at Tc= 25 oC Figure 13: Turn-Off Safe Operating Area Figure 14: SJT Transient Thermal Impedance Figure 15: FWD Transient Thermal Impedance Figure 16: Drain Current Derating vs. Pulse Width Figure 17: Typical FWD Forward Characteristics Jun 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 6 of 11 GA20SICP12-247 Section V: Driving the GA20SICP12-247 Drive Topology TTL Logic Constant Current High Speed – Boost Capacitor High Speed – Boost Inductor Proportional Pulsed Power Gate Drive Power Consumption High Medium Medium Low Lowest Medium Switching Frequency Low Medium High High High N/A Application Emphasis Availability Wide Temperature Range Wide Temperature Range Fast Switching Ultra Fast Switching Wide Drain Current Range Pulse Power Coming Soon Coming Soon Production Coming Soon Coming Soon Coming Soon A: Static TTL Logic Driving The GA20SICP12-247 may be driven using direct (5 V) TTL logic after current amplification. The (amplified) current level of the supply must meet or exceed the steady state gate current (IG,steady) required to operate the GA20SICP12-247. The power level of the supply can be estimated from the target duty cycle of the particular application. I G,steady is dependent on the anticipated drain current ID through the SJT and the DC current gain hFE, it may be calculated from the following equation. An accurate value of the h FE may be read from Figure 6. , ( , ) 1.5 D 5V TTL Gate Signal G 5/0V TTL i/p IG,steady GR S Figure 18: TTL Gate Drive Schematic B: High Speed Driving The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 19 which features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on. Figure 19: An idealized gate current waveform for fast switching of an SJT. An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, Q G, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, C GS, and gate-drain capacitance, CGD, are fully charged. = , 1 + Jun 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 7 of 11 GA20SICP12-247 Ideally, IG,on should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady onstate. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, L s, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V GS,sat (see Figure 7) level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V GS = 0 V, a negative gate voltage VGS may be used in order to speed up the turn-off transition. Two high-speed drive topologies for the SiC SJTs are presented below. B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4 The GA20SICP12-247 may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and lowside driving, its datasheet provides additional details about this drive topology. C2 +12 V GA03IDDJT30-FR4 Gate Driver Board VGL VCC High C5 U3 VCC High RTN CG1 VGL VGH Signal R1 CG2 R2 U1 U5 R4 C9 VEE C6 Gate Signal VEE VGL VGL R3 U2 C1 VCC Low RTN IG G GR S C8 VGH VCC Low +12 V RG2 D1 VEE VEE Gate RG1 U6 Signal RTN D C10 C3 U4 Source C4 VEE Voltage Isolation Barrier Figure 20: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver. The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective 3 gate resistance of RG = 3.75 operation of the GA20SICP12-247. The steady state current supplied to the gate pin of the GA20SICP12-247 with on-board R G = 3.75 shown in Figure 21. The maximum allowable safe value of R G for the user’s required drain current can be read from Figure 22. For the GA20SICP12-247, RG must be reduced for ID A for safe operation with the GA03IDDJT30-FR4. For operation at ID A, RG may be calculated from the following equation, which contains the DC current gain hFE (Figure 6) and the gatesource saturation voltage V GS,sat (Figure 7). , Jun 2015 = 4.7 ( , , 1.5 ) 0.6 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 8 of 11 GA20SICP12-247 Figure 21: Typical steady state gate current supplied by the GA03IDDJT30-FR4 board for the GA20SICP12-247 with the on board resistance of 3.75 Figure 22: Maximum gate resistance for safe operation of the GA20SICP12-247 at different drain currents using the GA03IDDJT30-FR4 board. B:2: High Speed, Low Loss Drive with Boost Inductor A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the GA20SICP12-247 at high-speed. It utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses I G,on and IG,off. During operation, inductor L is charged to a specified IG,on current value then made to discharge IL into the SJT gate pin using logic control of S 1, S2, S3, and S4, as shown in Figure 23. After turn on, while the device remains on the necessary steady state gate current IG,steady is supplied from source VCC through RG. Please refer to the article “A currentinformation on this driving topology.4 S1 VCC S2 L D VEE S3 G S4 RG VEE GR S Figure 23: Simplified Inductive Pulsed Drive Topology 3 – RG = (1/RG1 +1/RG2) . Driver is pre-installed with RG1 = RG2 = 7.5 4 -1 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013 Jun 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 9 of 11 GA20SICP12-247 C: Proportional Gate Current Driving For applications in which the GA20SICP12-247 will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain current ID feedback to vary the steady state gate current I G,steady supplied to the GA20SICP12-247 C:1: Voltage Controlled Proportional Driver The voltage controlled proportional driver relies on a gate drive IC to detect the GA20SICP12-247 drain-source voltage V DS during on-state to sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A high voltage diode connected between the drain and sense protects the IC from high-voltage when the driver and GA20SICP12-247 are in off-state. A simplified version of this topology is shown in Figure 24, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junctiontransistors/ Gate Signal Proportional Gate Current Driver Signal D HV Diode Sense G Output IG,steady GR S Figure 24: Simplified Voltage Controlled Proportional Driver C:2: Current Controlled Proportional Driver The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback I D of the GA20SICP12-247 during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to I D at a fixed forced current gain which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA20SICP12-247 is initially tuned-on using a gate current pulse supplied into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady, and thus the gate drive power consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 25, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/. N2 D G Gate Signal GR N3 N1 S N2 Figure 25: Simplified Current Controlled Proportional Driver Jun 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 10 of 11 GA20SICP12-247 Section VI: Package Dimensions TO-247AB (4.318 REF.) 0.170 REF. (5.486) 0.216 PACKAGE OUTLINE (15.748) (16.256) 0.620 0.640 0.55 (13.97) 0.236 (5.99) 0.171 (4.699) 0.208 (5.283) 0.054 (1.36) 0.045 (1.14) 0.059 (1.498) 0.098 (2.489) 0.22 (5.59) 0.242 BSC. (6.147 BSC.) 0.819 0.844 (20.803) (21.438) 0.012 (0.3) 0.652 (16.56) Ø 0.140 (3.556) 0.143 (3.632) Ø 0.118 (3.00) Ø 0.283 (7.19) GA20SICP17-247 XXXXXX Lot code 0.780 0.800 (19.812) (20.320) 0.177 MAX (4.496) 0.065 (1.651) 0.083 (2.108) 0.040 (1.016) 0.055 (1.397) 0.2146 (5.451) BSC. 0.016 (0.406) 0.031 (0.787) 0.075 (1.905) 0.115 (2.921) NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS Revision History Date Revision Comments 2015/06/11 0 Initial release Supersedes Published by GeneSiC Semiconductor, Inc. 43670 Trade Center Place Suite 155 Dulles, VA 20166 GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Jun 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 11 of 11 GA20SICP12-247 Section VII: SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/igbt_copack/GA20SICP12-247_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA20SICP12-247. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 1.0 $ * $Date: 29-MAY-2015 $ * * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * * COPYRIGHT (C) 2015 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. * * Start of GA20SICP12-247 SPICE Model * .SUBCKT GA20SICP12 DRAIN GATE SOURCE Q1 DRAIN GATE SOURCE GA20SICP12_Q D1 SOURCE DRAIN GA20SICP12_D1 D2 SOURCE DRAIN GA20SICP12_D2 * .model GA20SICP12_Q NPN + IS 9.833E-48 ISE 1.073E-26 EG 3.23 + BF 100 BR 0.55 IKF 9000 + NF 1 NE 2 RB 3.09 + RE 0.005 RC 0.040 CJC 752E-12 + VJC 3.17 MJC 0.48 CJE 3.01E-09 + VJE 3.568 MJE 0.538 XTI 3 + XTB -1.5 TRC1 8.50E-03 MFG GeneSiC_Semi + IRB 0.006 RBM 0.101 .MODEL GA20SICP12_D1 D + IS 5.48E-17 RS 0.03214547 N 1 + IKF 1000 EG 1.2 XTI 3 + CJO 1.15E-09 VJ 0.44 M 1.5 + FC 0.5 TT 1.00E-10 IBV 1.00E-03 .MODEL GA20SICP12_D2 D + IS 1.54E-13 RS 0.23 N 3.941 0 + IKF 19 EG 3.23 XTI + FC 0.5 TT 0 IBV 1.00E-03 .ENDS * End of GA20SICP12-247 SPICE Model Jun 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 1 of 1