ASNT8141-KMC

Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT8141-KMC DC-23Gbps PRBS Generator with the (x7 + x6 + 1) Polynomial Additional output delayed by half of the sequence period  Asynchronous reset signal for elimination of the “all zeros” initial state  Fully differential CML input interface  Fully differential CML output interface with 400mV single-ended swing  Single +3.3V or -3.3V power supply  Power consumption: 530mW  Custom CQFP 24-pin package qp vee  vcc DC to 23Gbps output data rate qn  vcc Full-length (27-1) pseudo-random binary sequence (PRBS) generator vcc  vee vcc vcc rstn_p clk_p ASNT8141 vcc vcc rstn_n clk_n vcc vcc Rev. 1.7.2 1 vcc qxorp vcc qxorn vcc vee vee February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com DESCRIPTION Fig. 1. Functional Block Diagram The ASNT8141-KMC SiGe IC shown in Fig. 1 provides a full 127-bit long pseudo-random binary sequence (PRBS) signal according to the polynomial (x7 + x6 + 1), where xD represents a delay of D clock cycles. This is implemented as a linear feedback shift register (LFSR) in which the outputs of the seventh and sixth flip-flops are combined together by an XOR function and provided as an input to the first flipflop of the register. The LFSR-based PRBS generator produces 127 binary states, excluding the “all zeros” state that is illegal for the XOR-based configuration. To eliminate this state that locks the LFSR and prevents PRBS generation, an asynchronous external active-low preset signal rstn_p/rstn_n is implemented in the circuit. When the preset is asserted, LFSR is set to the “1000000” state containing one logic “1” value that is enough for the activation of the PRBS generation. When the preset is released, the chip delivers one consecutive bit of the PRBS signal to output pins qp/qn per each rising edge of clock clk_p/clk_n, starting from the above mentioned state. An additional copy of the same PRBS signal delayed by 63 bits (half of the sequence period) is delivered to pins qxorp/qxorn and can be used to double the frequency of the output signal using an external multiplexer (e.g. ASNT5150 part) as shown in Fig. 2. Fig. 2. PRBS Frequency Doubling Rev. 1.7.2 2 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com The simulated eyes for both signals are shown in Fig. 3. Fig. 3. 20Gbps PRBS Output Eye Diagram (Simulation, Slow Corner, 125oC) All I/O stages are back terminated to vcc with on-chip 50Ohm resistors and may be used in either DC or AC coupling modes (see also POWER SUPPLY CONFIGURATION). In the first mode, the input signal’s common mode voltage should comply with the specifications shown in ELECTRICAL CHARACTERISTICS. In the second mode, the input termination provides the required common mode voltage automatically. The differential DC signaling mode is recommended for optimal performance. POWER SUPPLY CONFIGURATION The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positive supply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be needed for each different power supply combination. All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V. Rev. 1.7.2 3 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ABSOLUTE MAXIMUM RATINGS Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead to reduced reliability. Functional performance is specified over the recommended operating conditions for power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vcc). Table 1. Absolute Maximum Ratings Parameter Supply Voltage (vee) Power Consumption RF Input Voltage Swing (SE) Case Temperature Storage Temperature Operational Humidity Storage Humidity Min -40 10 10 Max -3.6 0.58 1.0 +90 +100 98 98 Units V W V ºC ºC % % TERMINAL FUNCTIONS TERMINAL Name No. Type rstn_p rstn_n clk_p clk_n qp qn qxorp qxorn Name vcc vee Rev. 1.7.2 DESCRIPTION High-Speed I/Os Differential high-speed asynchronous reset (active low) inputs with internal SE 50Ohm termination to vcc Differential high-speed clock input signals with internal 50Ohm termination to vcc Differential high-speed data outputs. Require external SE 50Ohm termination to vcc Differential delayed sequence high-speed data outputs. Require external SE 50Ohm termination to vcc Supply and Termination Voltages Description Pin Number Positive power supply 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 (+3.3V or 0) Negative power supply 1, 7, 13, 19 (0V or -3.3V) 11 9 21 23 17 15 5 3 CML input CML input CML output CML output 4 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ELECTRICAL CHARACTERISTICS PARAMETER MIN TYP MAX UNIT COMMENTS General Parameters -3.1 -3.3 -3.5 V ±6% vee 0.0 V External ground vcc Ivee 160 mA Power consumption 530 mW Junction temperature -40 25 125 °C HS Input Clock (clk_p/clk_n) Frequency DC 23 GHz Swing 0.05 0.8 V Differential or SE, p-p CM Voltage Level vcc-0.8 vcc V Must match for both inputs HS Output Data (qp/qn, qxorp/qxorn) Swing (SE) 280 440 mV CM Voltage Level vcc-0.8 vcc V Output Jitter 2.5 ps Peak-to-peak Reset Signal (rstn_p/rstn_n) Frequency DC 15 GHz Rise time 20 % of the clock period Recovery time 36 ps Swing 0.05 0.8 V Differential p-p CM Voltage Level vcc-0.8 vcc V PACKAGE INFORMATION The chip die is housed in a custom 24-pin CQFP package shown in Fig. 4. The package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for this section to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive supply. The part’s identification label is ASNT8141-KMC. The first 8 characters of the name before the dash identify the bare die including general circuit family, fabrication technology, specific circuit type, and part version while the 3 characters after the dash represent the package’s manufacturer, type, and pin out count. This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten substances. Rev. 1.7.2 5 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com Fig. 4. CQFP 24-Pin Package Drawing (All Dimensions in mm) Rev. 1.7.2 6 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com REVISION HISTORY Revision 1.7.2 1.6.2 1.6.1 1.3.1 1.2.1 1.1.1 1.0.1 Rev. 1.7.2 Date Changes 02-2020 Updated Package Information 07-2019 Updated Letterhead 11-2015 Updated description Updated power supply configuration Updated absolute maximum ratings section Corrected electrical characteristics table Updated package information section 08-2013 Corrected description 02-2013 Corrected title Corrected description Corrected terminal functions table Updated electrical characteristics table Revised package information section 01-2013 Updated power and current consumption 01-2013 First release 7 February 2020