ASNT8142-KMC

Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT8142-KMC Generator of DC-to-23Gbps PRBS with Selectable Polynomials DC to 23Gbps output data rate  Additional output delayed by half of the sequence period  Asynchronous reset signal for elimination of the “all zeros” initial state  Fully differential CML input interface  Fully differential CML output interface with 400mV single-ended swing  Single +3.3V or -3.3V power supply  Power consumption: 740mW  Custom CQFP 24-pin package qp vee  vcc Selectable power of the Polynomial qn  vcc Full-length (215-1) or (27-1) pseudo-random binary sequence (PRBS) generator vcc  vee vcc vcc rstn_p clk_p ASNT8142 vcc vcc rstn_n clk_n vcc vcc Rev. 1.2.2 1 vcc qxorp vcc qxorn vcc vee off15 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com DESCRIPTION D D D D D D qp/n clkp/n off15 to all DFFs rstnp/n D D D D D qxorp/n Fig. 1. Functional Block Diagram The ASNT8142-KMC SiGe IC shown in Fig. 1 provides a selectable full 32767-bit or 127-bit long pseudo-random binary sequence (PRBS) signal according to either a (x15 + x14 + 1), or a (x7 + x6 + 1) polynomial respectively, where xD represents a delay of D clock cycles. This is implemented as a linear feedback shift register (LSFR) in which the outputs of either the fifteenth and fourteenth, or seventh and sixth flip-flops are combined together by an XOR function, and provided as an input to the first flip-flop of the register. The polynomial is selected through the external control signal off15. The LSFR-based PRBS generator produces binary states, excluding the “all zeros” state that is illegal for the XOR-based configuration. To eliminate this state that locks the LSFR and prevents PRBS generation, an asynchronous external active-low preset signal rstnp/rstnn is implemented in the circuit. When the preset is asserted, LSFR is set to the All-“1” state that is enough for activation of the PRBS generation. When the preset is released, the chip delivers one consecutive bit of the PRBS signal to output pins qp/qn per each rising edge of clock clkp/clkn, starting from the above mentioned state. An additional copy of the same PRBS signal delayed by half of the sequence period is delivered to pins qxorp/qxorn, and can be used to double the frequency of the output signal using an external multiplexer (e.g. ASNT5150 part) as shown in Fig. 2. Rev. 1.2.2 2 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT8142 qp qn clkp clkn Clk qxorp qxorn Main PRBS ASNT5150 20Gb/s MUX 2:1 PRBS 40Gb/s Delayed PRBS Fig. 2. PRBS Frequency Doubling The simulated eyes for both signals are shown in Fig. 3. Fig. 3. 20Gbps PRBS Output Eye Diagram (Simulation, Slow Corner, 125oC) All I/O stages are back terminated to vcc with on-chip 50Ohm resistors and may be used in either DC or AC coupling modes (see also POWER SUPPLY CONFIGURATION). In the first mode, the input signal’s common mode voltage should comply with the specifications shown in ELECTRICAL CHARACTERISTICS. In the second mode, the input termination provides the required common mode voltage automatically. The differential DC signaling mode is recommended for optimal performance. POWER SUPPLY CONFIGURATION The part can operate with either a negative supply (vcc = 0.0V = ground and vee = −3.3V), or a positive supply (vcc = +3.3V and vee = 0.0V = ground). In case of a positive supply, all I/Os need AC termination Rev. 1.2.2 3 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com when connected to any devices with 50Ohm termination to ground. Different PCB layouts will be needed for each different power supply combination. All the characteristics detailed below assume vcc = 0.0V and vee = -3.3V. ABSOLUTE MAXIMUM RATINGS Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead to reduced reliability. Functional performance is specified over the recommended operating conditions for power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground (assumed vcc). Table 1. Absolute Maximum Ratings Parameter Supply Voltage (vee) Power Consumption RF Input Voltage Swing (SE) Case Temperature Storage Temperature Operational Humidity Storage Humidity Min -40 10 10 Max -3.6 0.86 1.0 +90 +100 98 98 Units V W V ºC ºC % % TERMINAL FUNCTIONS TERMINAL Name No. Type rstn_p rstn_n clk_p clk_n qp qn qxorp qxorn off15 Name vcc vee Rev. 1.2.2 DESCRIPTION High-Speed I/Os 11 CML Differential high-speed asynchronous reset (active low) inputs input with internal SE 50Ohm termination to vcc 9 21 CML Differential clock input signals with internal 50Ohm input termination to vcc 23 17 CML Differential data outputs. Require external SE 50Ohm output termination to vcc 15 5 CML Differential delayed sequence data outputs. Require external SE output 50Ohm termination to vcc 3 Control Signal 7 CMOS 3.3V CMOS input with internal 1MOhm termination to vcc input Supply and Termination Voltages Description Pin Number Positive power supply 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 (+3.3V or 0) Negative power supply 1, 13, 19 (0V or -3.3V) February 2020 4 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ELECTRICAL CHARACTERISTICS PARAMETER MIN TYP MAX UNIT COMMENTS General Parameters -3.1 -3.3 -3.5 V ±6% vee 0.0 V External ground vcc Ivee 210 240 mA Power consumption 740 mW Junction temperature -40 25 125 °C HS Input Clock (clkp/clkn) Frequency DC 23 GHz Swing 0.05 0.8 V Differential or SE, p-p CM Voltage Level vcc-0.8 vcc V Must match for both inputs HS Output Data (qp/qn, qxorp/qxorn) Swing (SE) 280 440 mV CM Voltage Level vcc-0.8 vcc V Output Jitter 2.5 ps Peak-to-peak Reset Signal (rstnp/rstnn) Frequency DC 15 GHz Rise time 20 % of the clock period Recovery time 36 ps Swing 0.05 0.8 V Differential p-p CM Voltage Level vcc-0.8 vcc V PRBS Select Signal (off15) Input low level vee vee+0.4 V Do not apply voltages below vee! PACKAGE INFORMATION The chip die is housed in a custom 24-pin CQFP package shown in Fig. 4. The package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for this section to be soldered to the vcc plain, which is ground for a negative supply, or power for a positive supply. The part’s identification label is ASNT8142-KMC. The first 8 characters of the name before the dash identify the bare die including general circuit family, fabrication technology, specific circuit type, and part version while the 3 characters after the dash represent the package’s manufacturer, type, and pin out count. This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten substances. Rev. 1.2.2 5 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com Fig. 4. CQFP 24-Pin Package Drawing (All Dimensions in mm) Rev. 1.2.2 6 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com REVISION HISTORY Revision 1.2.2 1.1.2 1.1.1 1.0.1 1.0.0 Rev. 1.2.2 Date Changes 02-2020 Updated Package Information 07-2019 Updated Letterhead 10-2017 Corrected power and current consumption values Corrected absolute maximum power Added specification for the PRBS select input off15 11-2015 Initial Release 09-2014 Preliminary Release 7 February 2020