BUJ103AD
Silicon diffused power transistor
Rev. 3 — 18 October 2016
Product data sheet
1. Product profile
1.1 General description
High-voltage, high-speed planar-passivated NPN power switching transistor in a SOT428
(D-PAK) surface mounted package.
1.2 Features and benefits
Low thermal resistance
Fast switching
1.3 Applications
Electronic lighting ballasts
Inverters
DC-to-DC converters
Motor control systems
1.4 Quick reference data
VCESM 700 V
Ptot 80 W
IC 4 A
hFEsat = 12.5 (typ)
2. Pinning information
Table 1.
Pinning
Pin
Description
1
base
2
collector
3
emitter
mb
mounting base; connected to collector
Simplified outline
Symbol
mb
C
[1]
B
E
sym123
SOT428 (D-PAK)
[1]
It is not possible to make a connection to pin 2 of the SOT428 (D-PAK) package.
BUJ103AD
WeEn Semiconductors
Silicon diffused power transistor
3. Ordering information
Table 2.
Ordering information
Type number
BUJ103AD
Package
Name
Description
Version
D-PAK
plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT428
4. Limiting values
Limiting values
Table 3.
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCESM
peak collector-emitter voltage
VBE = 0 V
-
700
V
VCBO
collector-base voltage
open emitter
-
700
V
VCEO
collector-emitter voltage
open base
-
400
V
IC
collector current (DC)
-
4
A
ICM
peak collector current
-
8
A
IB
base current (DC)
-
2
A
IBM
peak base current
-
4
A
Ptot
total power dissipation
-
80
W
Tstg
storage temperature
65
+150
C
Tj
junction temperature
-
150
C
Tmb 25 C; see Figure 1
001aab993
120
Pder
(%)
80
40
0
0
40
80
120
160
Tmb (°C)
P tot
P der % = ------------------------- 100%
P tot 25 C
Fig 1.
Normalized total power dissipation as a function of mounting base temperature
BUJ103AD
Product data sheet
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BUJ103AD
WeEn Semiconductors
Silicon diffused power transistor
5. Thermal characteristics
Table 4.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-mb)
thermal resistance from junction to mounting base
see Figure 2
Rth(j-a)
[1]
thermal resistance from junction to ambient
Min
Typ
Max
Unit
-
-
1.56
K/W
-
75
-
K/W
Device mounted on a printed-circuit board; minimum footprint.
[1]
001aab998
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
0.05
0.02
10−1
δ=
Ptot
tp
T
0.01
t
tp
T
10−2
10−5
10−4
10−3
10−2
10−1
1
10
tp (s)
Fig 2.
Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Characteristics
Table 5.
Tmb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
ICES
ICBO
collector-emitter cut-off
current
VBE = 0 V; VCE = VCESMmax
[1]
-
-
1.0
mA
VBE = 0 V; VCE = VCESMmax; Tj = 125 C
[1]
-
-
2.0
mA
collector-base cut-off current
VBE = 0 V; VCE = VCESMmax
[1]
-
-
1.0
mA
[1]
-
-
0.1
mA
ICEO
collector-emitter cut-off
current
VCEO = VCEOMmax = 400 V
IEBO
emitter-base cut-off current
VEB = 7 V; IC = 0 A
-
-
0.1
mA
VCEOsus
collector-emitter sustaining
voltage
IB = 0 A; IC = 10 mA; L = 25 mH;
see Figure 3 and 4
400
-
-
V
VCEsat
collector-emitter saturation
voltage
IC = 3.0 A; IB = 0.6 A; see Figure 10
-
0.25
1.0
V
VBEsat
base-emitter saturation
voltage
IC = 3.0 A; IB = 0.6 A; see Figure 11
-
0.97
1.5
V
hFE
DC current gain
IC = 1 mA; VCE = 5 V; see Figure 9
10
17
32
IC = 500 mA; VCE = 5 V
13
22
32
BUJ103AD
Product data sheet
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BUJ103AD
WeEn Semiconductors
Silicon diffused power transistor
Table 5.
Characteristics …continued
Tmb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
hFEsat
DC saturation current gain
IC = 2.0 A; VCE = 5 V
11
16
22
IC = 3.0 A; VCE = 5 V
-
12.5
-
-
0.52
0.6
s
-
2.7
3.3
s
-
0.3
0.35
s
-
1.2
1.4
s
-
30
60
ns
-
-
1.8
s
-
-
120
ns
Dynamic characteristics
Switching times (resistive load); see Figure 5 and 6
ton
turn-on time
tstg
storage time
tf
fall time
ICon = 2.5 A; IBon = IBoff = 0.5 A;
RL = 75
Switching times (inductive load); see Figure 7 and 8
tstg
storage time
tf
fall time
ICon = 2 A; IBon = 0.4 A; LB = 1 H;
VBB = 5 V
Switching times (inductive load); see Figure 7 and 8
tstg
storage time
tf
fall time
[1]
ICon = 2 A; IBon = 0.4 A; LB = 1 H;
VBB = 5 V; Tj = 100 C
Measured with half sine-wave voltage (curve tracer).
IC
(mA)
50 V
100 Ω to 200 Ω
250
horizontal
oscilloscope
vertical
100
6V
300 Ω
1Ω
30 Hz to 60 Hz
001aab987
10
0
min
VCE (V)
VCEOsus
001aab988
Fig 3.
Test circuit for collector-emitter sustaining
voltage
BUJ103AD
Product data sheet
Fig 4.
Oscilloscope display for collector-emitter
sustaining voltage test waveform
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BUJ103AD
WeEn Semiconductors
Silicon diffused power transistor
IC
ICon
90 %
90 %
VCC
RL
VIM
0
10 %
RB
t
DUT
tf
tp
ts
IB
ton
T
toff
001aab989
IBon
10 %
t
VIM = 6 V to +8 V; VCC = 250 V; tp = 20 s;
= tp/T = 0.01.
tr ≤ 30 ns
−IBoff
RB and RL calculated from ICon and IBon requirements.
Fig 5.
Test circuit for resistive load switching
Fig 6.
001aab990
Switching times waveforms for resistive load
IC
ICon
90 %
VCC
LC
10 %
IBon
VBB
LB
DUT
tf
ts
toff
IB
001aab991
t
IBon
t
−IBoff
VCC = 300 V; VBB = 5 V; LC = 200 H; LB = 1 H.
Fig 7.
Test circuit for inductive load switching
BUJ103AD
Product data sheet
001aab992
Fig 8.
Switching times waveforms for inductive load
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BUJ103AD
WeEn Semiconductors
Silicon diffused power transistor
001aab994
102
001aab995
2.0
Tj = 25 °C
VCEsat
(V)
IC = 1 A
2A 3A
4A
1.6
hFE
VCE = 5 V
1.2
10
1V
0.8
0.4
1
10−2
10−1
1
0
10−2
10
10−1
1
IC (A)
10
IB (A)
Tj = 25 C.
Fig 9.
DC current gain as a function of collector
current; typical values
Fig 10. Collector-emitter saturation voltage as a
function of base current; typical values
001aab996
1.4
VBEsat
(V)
1.2
001aab997
VCEsat
(V) 0.5
0.4
1.0
0.8
0.3
0.6
0.2
0.4
0.1
0.2
0
10−1
1
0
10−1
10
1
IC (A)
IC/IB = 4.
IC/IB = 4.
Fig 11. Base-emitter saturation voltage as a function
of collector current; typical values
BUJ103AD
Product data sheet
10
IC (A)
Fig 12. Collector-emitter saturation voltage as a
function of collector current; typical values
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BUJ103AD
WeEn Semiconductors
Silicon diffused power transistor
001aac000
10
IC
(A)
8
VCC
6
LC
IBon
VBB
VCL(CE)
probe point
4
LB
DUT
001aab999
2
0
0
VCEclamp 1000 V; VCC = 150 V; VBB = 5 V; LB = 1 H;
LC = 200 H.
Fig 13. Test circuit for reverse bias safe operating
area
400
200
800
1000
VCEclamp (V)
600
Tj Tj(max).
Fig 14. Reverse bias safe operating area
001aac001
102
IC
(A)
duty cycle = 0.01
10
ICM(max)
IC(max)
II(3)
(1)
tp = 20 μs
50 μs
100 μs
200 μs
500 μs
DC
1
(2)
10−1
I(3)
10−2
III(3)
10−3
1
102
10
103
VCEclamp (V)
Tmb 25 C; Mounted with heatsink compound and 30 5 Newton force on the center of the envelope.
(1) Ptot maximum and Ptot peak maximum lines.
(2) Second breakdown limits.
(3) I = Region of permissible DC operation.
II = Extension for repetitive pulse operation.
III = Extension during turn-on in single transistor converters provided that RBE 100 and tp 0.6 s.
Fig 15. Forward bias safe operating area
7. Package information
Epoxy meets requirements of UL94 V-0 at 1⁄8 inch.
BUJ103AD
Product data sheet
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BUJ103AD
WeEn Semiconductors
Silicon diffused power transistor
8.
Package outline
Fig. 16. Package outline DPAK (SOT428)
BUJ103AD
Product data sheet
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BUJ103AD
WeEn Semiconductors
Silicon diffused power transistor
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Data sheet status
Document
status [1][2]
Product
status [3]
Objective
[short] data
sheet
Development This document contains data from
the objective specification for product
development.
Preliminary
[short] data
sheet
Qualification
This document contains data from the
preliminary specification.
Product
[short] data
sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Definition
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
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specified use without further testing or modification.
Please consult the most recently issued document before initiating or
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BUJ103AD
Product data sheet
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
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BUJ103AD
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Silicon diffused power transistor
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BUJ103AD
Product data sheet
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