BUJ105A,127

DISCRETE SEMICONDUCTORS DATA SHEET BUJ105A Silicon Diffused Power Transistor Product specification February 2018 WeEn Semiconductors Product specification Silicon Diffused Power Transistor BUJ105A GENERAL DESCRIPTION High-voltage, high-speed planar-passivated npn power switching transistor in TO220AB envelope intended for use in high frequency electronic lighting ballast applications, converters, inverters, switching regulators, motor control systems, etc. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS VCESM VCBO VCEO IC ICM Ptot VCEsat hFEsat tf Collector-emitter voltage peak value Collector-Base voltage (open emitter) Collector-emitter voltage (open base) Collector current (DC) Collector current peak value Total power dissipation Collector-emitter saturation voltage VBE = 0 V Fall time PINNING - TO220AB PIN base 2 collector 3 emitter mb PIN CONFIGURATION DESCRIPTION 1 Tmb ≤ 25 ˚C IC = 4.0 A;IB = 0.8 A IC = 4.0 A; VCE = 5 V IC = 5 A; IB1 = 1 A TYP. MAX. UNIT 0.3 11 20 700 700 400 8 16 80 1.0 15 50 V V V A A W V ns MIN. MAX. UNIT -65 - 700 400 700 8 16 4 8 80 150 150 V V V A A A A W ˚C ˚C TYP. MAX. UNIT - 1.56 K/W 60 - K/W SYMBOL mb collector 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER CONDITIONS VCESM VCEO VCBO IC ICM IB IBM Ptot Tstg Tj Collector to emitter voltage Collector to emitter voltage (open base) Collector to base voltage (open emitter) Collector current (DC) Collector current peak value Base current (DC) Base current peak value Total power dissipation Storage temperature Junction temperature VBE = 0 V Tmb ≤ 25 ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Junction to mounting base Rth j-a Junction to ambient February 2018 CONDITIONS in free air 1 Rev 1.100 WeEn Semiconductors Product specification Silicon Diffused Power Transistor BUJ105A STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS ICES,ICBO ICES Collector cut-off current 1 VBE = 0 V; VCE = VCESMmax VBE = 0 V; VCE = VCESMmax; Tj = 125 ˚C ICEO IEBO VCEOsust Collector cut-off current Emitter cut-off current Collector-emitter sustaining voltage VCEsat VBEsat hFE hFE hFEsat Collector-emitter saturation voltage Base-emitter saturation voltage DC current gain VCEO = VCEOMmax (400V) VEB = 9 V; IC = 0 A IB = 0 A; IC = 10 mA; L = 25 mH IC = 4.0 A;IB = 0.8 A IC = 4.0 A;IB = 0.8 A IC = 1 mA; VCE = 5 V IC = 500 mA; VCE = 5 V IC = 4.0 A; VCE = 5 V MIN. TYP. MAX. UNIT - - 0.2 0.5 mA mA 400 - 0.1 1 - mA mA V 10 13 8 0.3 1.0 14 23 11 1.0 1.5 34 36 15 V V TYP. MAX. UNIT 0.65 1.8 0.3 1 2.5 0.5 µs µs µs 1.2 20 1.7 50 µs ns 1.4 25 1.9 100 µs ns DYNAMIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL ton ts tf PARAMETER CONDITIONS Switching times (resistive load) ICon = 5 A; IBon = -IBoff = 1 A; RL = 75 ohms; VBB2 = 4 V; Turn-on time Turn-off storage time Turn-off fall time Switching times (inductive load) ts tf Turn-off storage time Turn-off fall time Switching times (inductive load) ts tf Turn-off storage time Turn-off fall time ICon = 5 A; IBon = 1 A; LB = 1 µH; -VBB = 5 V ICon = 5 A; IBon = 1 A; LB = 1 µH; -VBB = 5 V; Tj = 100 ˚C 1 Measured with half sine-wave voltage (curve tracer). February 2018 2 Rev 1.100 WeEn Semiconductors Product specification Silicon Diffused Power Transistor BUJ105A ICon 90 % + 50v 100-200R 90 % IC 10 % ts Horizontal ton tf toff Oscilloscope IBon IB Vertical 10 % 300R 1R tr 30ns 6V 30-60 Hz -IBoff Fig.1. Test circuit for VCEOsust. Fig.4. Switching times waveforms with resistive load. VCC IC / mA LC 250 IBon 100 LB T.U.T. 10 0 -VBB min VCE / V VCEOsust Fig.2. Oscilloscope display for VCEOsust. VCC Fig.5. Test circuit inductive load. = 300 V; -VBE = 5 V; LC = 200 uH; LB = 1 uH VCC ICon 90 % IC RL VIM 10 % RB 0 T.U.T. ts toff tp IB tf t IBon T t -IBoff Fig.3. Test circuit resistive load. VIM = -6 to +8 V VCC = 250 V; tp = 20 µs; δ = tp / T = 0.01. RB and RL calculated from ICon and IBon requirements. February 2018 Fig.6. Switching times waveforms with inductive load. 3 Rev 1.100 WeEn Semiconductors Product specification Silicon Diffused Power Transistor 120 BUJ105A Normalised Power Derating PD% VCEsat/V 110 2.0 100 90 1.6 80 IC=1A 70 2A 3A 4A 1.2 60 50 0.8 40 30 0.4 20 10 0 0 20 40 60 80 Tmb / C 100 120 0.0 0.01 140 0.10 1.00 10.00 IB/A Fig.7. Normalised power dissipation. PD% = 100⋅PD/PD 25˚C = f (Tmb) Fig.10. Collector-Emitter saturation voltage. Solid lines = typ values, VCEsat = f(IB); Tj=25˚C. VBESAT/V 1.4 HFE 50 1.3 30 Tj=100C 1.2 20 25C 15 1.1 -40C 10 1 0.9 5 -40C 0.8 Tj=100C 25C 0.7 2 VCE=1V 0.6 0.01 0.05 0.1 0.3 IC/A 1 2 3 5 0.5 0.1 10 Fig.8. Typical DC current gain. hFE = f(IC) parameter VCE 0.5 1 IC/A 2 5 10 Fig.11. Base-Emitter saturation voltage. Solid lines = typ values, VBEsat = f(IC); at IC/IB =4. HFE 50 VCESAT/V 0.6 30 0.5 Tj=100C Tj=100C 20 25C 0.4 15 -40C 0.3 10 25C 0.2 5 -40C VCE=5V 2 0.01 0.05 0.1 0.1 0.3 IC/A 1 2 3 5 0 0.2 10 0.6 1 IC/A 2 5 6 Fig.12. Collector-Emitter saturation voltage. Solid lines = typ values, VCEsat = f(IC); at IC/IB =4. Fig.9. Typical DC current gain. hFE = f(IC) parameter VCE February 2018 0.4 4 Rev 1.100 WeEn Semiconductors Product specification Silicon Diffused Power Transistor 10 BUJ105A IC/A 11 Zth / (K/W) 10 9 8 1 7 D= 0.5 6 0.1 0.2 0.1 0.05 0.02 0 5 tp PD D= 4 T -3V 3 t T 0.01 1E-06 -5V tp 2 -1V 1 1E-04 1E-02 t/s 1E+00 0 0 Fig.13. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 100 200 300 400 500 VCEclamp/V 600 700 800 Fig.15. Reverse bias safe operating area (Tj < Tjmax) for -VBE = 5V,3V & 1V. VCC LC IBon -VBB VCL LB T.U.T. Fig.14. Test circuit for reverse bias safe operating area. Vclamp < 700V; Vcc = 150V; -Vbe = 5V,3V & 1V; LB = 1µH; LC = 200µH. February 2018 5 Rev 1.100 WeEn Semiconductors Product specification Silicon Diffused Power Transistor BUJ105A MECHANICAL DATA Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 E A A1 p q mounting base D1 D L1(1) L2(1) Q L b1(2) (3×) b2(2) (2×) 1 2 3 c b(3×) e e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1(2) b2(2) c D D1 E e L L1(1) L2(1) max. p q Q mm 4.7 4.1 1.40 1.25 0.9 0.6 1.6 1.0 1.3 1.0 0.7 0.4 16.0 15.2 6.6 5.9 10.3 9.7 2.54 15.0 12.8 3.30 2.79 3.0 3.8 3.5 3.0 2.7 2.6 2.2 Notes 1. Lead shoulder designs may vary. 2. Dimension includes excess dambar. OUTLINE VERSION SOT78 February 2018 REFERENCES IEC JEDEC JEITA 3-lead TO-220AB SC-46 6 EUROPEAN PROJECTION ISSUE DATE 08-04-23 08-06-13 Rev 1.100 WeEn Semiconductors Legal information Data sheet status Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Definition Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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